Pico Computing Takes Scale-Up Approach to FPGAs

By Michael Feldman

February 17, 2010

As high performance computing vendors polish their server and workstation portfolios with the latest multicore CPU and GPGPU wonders, Pico Computing is quietly making inroads into the HPC application space with its FPGA-based platforms. By picking the spots where reconfigurable computing makes the most sense, the company is looking to leverage its scalable FPGA technology to greatest effect.
Pico Computing E-16 ExpressCard

Seattle-based Pico was formed in November 2004 by founder Robert Trout. Using internal funding, the startup spent a couple of years on product development and subsequently started bringing its Xilinx-based FPGA computing platforms to market in 2007 and 2008. True to its name, Pico is a small company, with a staff of a dozen or so full-timers. As a private entity, they are not obliged to release financial results, but according to Mark Hur, Pico’s director of sales and marketing, the company is profitable today.

The company currently offers a range of platforms from a single FPGA card to large-scale FPGA “clusters” that contain over 100 of the devices in a 4U chassis. The company’s flagship E-16 Virtex-5 FPGA card was released in 2007. “To this day, that’s been the most successful product we’ve launched thus far,” says Hur. According to him, there are now multiple clusters of E-16s in the marketplace.

Recently, Pico demonstrated a password recovery system using a cluster of 77 Virtex-5 FPGAs, housed in a 4U enclosure and consuming less than 900 watts of power. According to the company, the system provides the computational equivalent of about 1,000 dual-core CPUs (Intel Core 2 Duo) for different recovery algorithms, specifically FileVault, Wi-Fi Protected Access (WPA), and Wired Equivalent Privacy (WEP). In fact, for the WEP algorithm, the Pico cluster delivered a 4,620-fold performance improvement and a 1,000-fold decrease in power consumption compared to the dual-core CPU implementation.

That level of performance and compute density for cryptography applications helps explain why Pico’s most beloved market is data security. The three-letter federal agencies in the US government are the main customers here, and they buy both off-the-shelf and custom products from the company. Security still represents the majority of Pico’s business today, although you’re not likely to see an NSA code cracking case study on the company’s Web site anytime soon.

Other favorite application areas for Pico include bioinformatics, financial analytics, image processing, and certain other types of scientific computing. The reason that FPGAs are so adept at these types of applications, from both a performance and power consumption point of view, is their ability to morph their hardware structures to match operators and data types for a given algorithm. This is especially true when the underlying algorithms are not based on typical integer or floating point data types.

In genomics applications, for example, a lot of algorithms are based on the four fundamental nucleoside bases (adenine, thymine, guanine, cytosine) that make up RNA and DNA. Thus a nucleoside data type would only be two bits wide. And unlike CPUs and GPUs, you can map FPGA resources to match that data size exactly. “You don’t need full 32-bit or 64-bit data paths and operators,” explains David Pellerin, Pico’s director of strategic marketing. “It’s wasteful.” That’s why some applications that get 100-fold acceleration from a GPU can get 1,000-fold from an FPGA, when compared to a CPU.

Pellerin, who used to be the chief technology officer at Impulse Accelerated Technologies, the makers of FPGA programming language Impulse C, was brought aboard Pico to energize the company’s marketing story and get behind some of the new product rollouts they’ve launched over the past few months. The newest offerings are based on the latest Spartan-6 and Virtex-6 hardware from FPGA-maker Xilinx. Pico’s most recent addition, the M-series modules, allows customers to construct standard-sized PCIe cards with up to 12 FPGAs.

Pico’s flagship E-series cards, on the other hand, plug into PCIe slots on a desktop system. But like the M-series, they can also be scaled into multiple FPGA configurations to build a computationally-dense FPGA cluster inside a single compute node. For HPC workloads especially, up to seven of the latest E-18 cards can be plugged into a PCIe carrier card, and multiple carrier cards can be installed into a 4U rack-mounted chassis. The idea is for customers to begin development with a single card plugged into a laptop or desktop, and when it’s time to deploy the full configuration, multiple cards can be plugged into PCIe backplane and installed in rack-mounted appliance or server.

From the software side, Pico has a consistent set of APIs that apply across its entire product set, and these interfaces can be accessed from either low-level Verilog code, or an FPGA-friendly C language, like Impulse C. Most of Pico’s customers writing cryptography apps use Verilog, but Impulse C tends to be more popular in bioinformatics and more traditional HPC codes.

Unlike other FPGA board makers, where one or two devices is matched to a host processor, Pico builds modular devices and backplanes such that as many as 177 FPGAs can be connected to a single CPU. That level of scalability means customers can squeeze a huge amount of computing hardware into very small enclosures. Since the core of most of these algorithms is just highly parallelized bit arithmetic, the CPU’s role is limited to driving the sequential part of the application. “For many applications, certainly in areas like cryptography and bioinformatics, the more FPGAs you can throw at the problem, the better it’s going to be,” says Pellerin.

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