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March 16, 2010

AMD Touts Core Competency

Michael Feldman

Now that Intel’s 6-core Westmere EP processors are running loose, AMD felt it was a good time to remind everyone that it is outpacing its larger rival in the core count department. In a blog entry posted this week, John Fruehe, director of product marketing for AMD’s server/workstation products, contends Intel’s HyperThreading technology isn’t all that great. Not surprisingly, he contends that AMD’s strategy of boosting the core count offers the best bang for the buck.
Intel HyperThreading is the company’s SMT (simultaneous multithreading) technology that supports two software threads per core. It was reintroduced by the chip vendor in its Nehalem microarchitecture and is being carried forward into the Westmere line. According to Intel and other SMT fans, it will boost performance on many multithreaded apps by 10-30 percent, while using only about five percent more transistor real estate on the die. It is especially useful for applications where threads intermittently stall because they have to wait for a memory fetch or for an I/O device.

For some applications though, it can decrease performance, mainly due to cache thrashing. The extra logic also exacts a power penalty. Fortunately, for those cases where HyperThreading degrades performance, it can be turned off. In fact, when Intel runs Linpack, Stream MP, and a number of other HPC-type benchmarks, it executes them with HyperThreading disabled.

AMD passed on SMT because the engineers there felt actual cores provided the best approach to parallel thread execution. Says Fruehe:

So, if SMT (or “core sharing”) yields both positive and negative results, what is the better answer? How about more cores? When you add more cores, you add more throughput. Period.

Later this month, AMD is slated to launch Magny-Cours, its 8- and 12-core Opteron processors. Then in 2011 the company will deliver Interlagos, which will up the ante to 12 and 16 cores. So for the near-term at least, AMD looks like it’s going to stick with its hard-core computing architecture. Fruehe’s last thought:

Of course there are those that can say “well, things like SMT can be implemented inexpensively and don’t consume that much power.” To those, I ask you, historically hasn’t AMD been the one committed to deliver better value and lower power?

So I guess he’s saying that if it was such a great idea, AMD would already have implemented it. While you’re parsing that tidbit of circular logic, it’s worth remembering that AMD chastised Intel in 2007 for introducing its quad-core Harpertown Xeon CPUs in a dual-chip package. At the time, AMD could claim it had the only “native” (on-die) quad-core processor. Now that it’s 2010, AMD will be introducing Magny-Cours in its own dual-chip package. What a difference a few years makes.

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