Chipmakers Look to Rock High-End Server Biz

By Michael Feldman

April 1, 2010

The x86 CPU festivities are over for now, but the party’s just getting started. The debut of the latest Intel Xeon and AMD Opteron processors over the last few weeks marks something of a turning point for server makers. For one thing, the introduction of Intel’s 6-core Westmere EP and 8-core Nehalem EX CPUs, and AMD’s 12-core Magny-Cours processor marks the beginning of the end of the quad-core era. Given that, HPC servers with fewer than double-digit core counts will soon be the exception rather than the rule.

AMD and Intel are attacking the high-server space somewhat differently, though. With Westmere EP (now the Xeon 5600), Intel is continuing its traditional 2P server business. But with Nehalem EX (now the Xeon 7500), Intel is charting new territory — big shared memory SMP machines. Intel also introduced the Xeon 6500, a 2P-only variant of Nehalem EX, ostensibly aimed at the HPC market. Meanwhile AMD has consolidated its performance-oriented 2P and 4P products into a single Opteron 6000 product line, starting with Magny-Cours (now the Opteron 6100).

From a price-performance perspective AMD has a good story. With the 6100 Opterons, AMD will go head-to-head with the 2P 5600 Xeons, which have faster cores, but fewer of them. The mid-range Opteron 6174, which sports 12 cores and runs at 2.2 GHz, costs $1,165 in quantity. A Xeon with comparable performance is the 6-core X5680, which is clocked at 3.33 GHz and costs $1664. Although the individual Xeon cores run faster, for many types of parallel workloads, the additional six cores on the Opteron will make up the difference, and then some. The fact that the Intel architecture implements HyperThreading, which handles two threads per core, only boosts performance by 10 to 20 percent. And in some cases, such as Linpack, it doesn’t help at all. Since the 6100 Opterons have four channels of memory and support up to 12 DIMM slots per socket, compared to three channels and nine DIMMs for the Xeon 5600s, the AMD CPUs have an additional advantage on memory-loving apps.

The 6100 Opterons will also go up against the 6500 Xeons in the 2P arena, as well as the 7500 Xeons in the 4P space. Here the Xeons go up to eight cores, the memory channel differential has been equalized at four apiece, and the memory capacity advantage is now with Intel at 16 DIMMs per socket. But the EX-class parts are even more expensive than Xeon 5600 chips. For example, the 8-core 6500 and 7500 products cost between $2,461 and $3,692, which is more than two and three times the price, respectively, of the Opteron 6174 mentioned above. Even the least expensive 6-core EX, which is the 1.86 GHz Xeon x7530, costs $200 more than the 6174.

The bottom line is that the new Magny-Cours processors look like a very competitive solution for 2P and 4P servers. But the 4P story is particularly interesting. AMD is pushing this 6000 series as a platform that does away with the “4P tax.” The tax refers to the traditional premium vendors charged for CPUs and chipsets that support 4-socket servers. Since the 6000 hardware can be used in both 2P and 4P boxes, you can actually save money by consolidating dual-socket servers (as long as you don’t need to spread out the processors over more boxes to get at more I/O). “The only reason 4P processors have been priced like they have is because there’s a guy in the business who owns a large chunk of the market and has been pricing that way for 20 years,” says John Fruehe, who heads AMD’s Product Marketing of the Server and Workstation Division. “It’s more tradition than technology that has forced that price.”

That “guy,” that Fruehe is referring to is, of course, Intel. But prior to Magny-Cours, AMD also priced its 4P/8P Opteron 8000 CPUs at a premium in relation to its 2P Opteron 2000 parts. But according to him, they eventually came to the conclusion that the demand for 4P servers was being inhibited by this pricing model. In fact, according to Fruehe, the quad-socket Opteron-based supercomputers on the TOP500 list came about because AMD gave the system vendors a nice volume discount on Opteron 8000 CPUs. “Generally speaking those were deals where an 8000 processor was priced like a 2000,” he told me. “Suddenly the economics made sense.”

Although he wouldn’t point to any specific systems, the half-petaflop “Ranger” Sun Constellation cluster at TACC, which uses quad-socket Opteron-based blades, almost certainly fits in this category. Fruehe maintains AMD still turned a profit on these supercomputer deals, but it gave them the idea that it could move a lot more product by pricing 4P parts like 2P parts. They believe that this strategy will unleash this market in HPC and across enterprise computing.

On the other hand, AMD has decided leave the 8P (and above), at least for the time being. At 60K or so processors per year, the company has calculated this is too small a market to give special consideration to. One might ask, though: If the 4P servers are such a good idea, why not 8P, 16P and so on? As you keep adding processors, or cores for that matter, memory bandwidth and capacity become the limiting factor. As AMD and Intel keep pouring on the cores, they’re forced to rebalance the memory subsystem.

The idea behind the new Xeon 7500 line is to max out both compute and memory in a familiar x86 package. As of this week, OEMs can build 8-socket commodity boxes with 1 TB of memory. With this approach, not only does Intel think it can edge out proprietary RISC CPUs in SMP servers used for mission-critical computing, it also believes it can grow the SMP market overall.

According to David Kanter at Real World Technologies, that might indeed come to pass. Although in the past there were multiple reasons that 8P servers represented a specialty market, a confluence of commodity technologies, including the new Xeons themselves, are changing the economics. In a recent article, Kanter writes:

The primary barriers to adoption for large x86 servers are software, maturity and cost/benefit. Scalable applications that would benefit from 8S servers are not common. Some classic examples include I/O heavy workloads like ERP, transactional or analytic databases and also select HPC workloads that favor shared memory rather than message passing. More recently, server consolidation using virtualization has emerged as an important workload. In 2010, there are simply more scalable workloads than were previously available.

Kanter goes on to analyze how the different pieces of the enterprise ecosystem are evolving, and how they could favor a shift to commodity 8P servers. For now, AMD seems content to play it conservative and let Intel test the SMP waters. If successful, perhaps the junior member of the x86 franchise will jump in after Intel has built the market. In the meantime, AMD is focused on rebuilding its server mojo in the 2P and 4P sweet spots. Magny-Cours looks like a fine start.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

UCSD, AIST Forge Tighter Alliance with AI-Focused MOU

January 18, 2018

The rich history of collaboration between UC San Diego and AIST in Japan is getting richer. The organizations entered into a five-year memorandum of understanding on January 10. The MOU represents the continuation of a 1 Read more…

By Tiffany Trader

New Blueprint for Converging HPC, Big Data

January 18, 2018

After five annual workshops on Big Data and Extreme-Scale Computing (BDEC), a group of international HPC heavyweights including Jack Dongarra (University of Tennessee), Satoshi Matsuoka (Tokyo Institute of Technology), Read more…

By John Russell

Researchers Measure Impact of ‘Meltdown’ and ‘Spectre’ Patches on HPC Workloads

January 17, 2018

Computer scientists from the Center for Computational Research, State University of New York (SUNY), University at Buffalo have examined the effect of Meltdown and Spectre security updates on the performance of popular H Read more…

By Tiffany Trader

HPE Extreme Performance Solutions

HPE and NREL Take Steps to Create a Sustainable, Energy-Efficient Data Center with an H2 Fuel Cell

As enterprises attempt to manage rising volumes of data, unplanned data center outages are becoming more common and more expensive. As the cost of downtime rises, enterprises lose out on productivity and valuable competitive advantage without access to their critical data. Read more…

Fostering Lustre Advancement Through Development and Contributions

January 17, 2018

Six months after organizational changes at Intel's High Performance Data (HPDD) division, most in the Lustre community have shed any initial apprehension around the potential changes that could affect or disrupt Lustre Read more…

By Carlos Aoki Thomaz

UCSD, AIST Forge Tighter Alliance with AI-Focused MOU

January 18, 2018

The rich history of collaboration between UC San Diego and AIST in Japan is getting richer. The organizations entered into a five-year memorandum of understandi Read more…

By Tiffany Trader

New Blueprint for Converging HPC, Big Data

January 18, 2018

After five annual workshops on Big Data and Extreme-Scale Computing (BDEC), a group of international HPC heavyweights including Jack Dongarra (University of Te Read more…

By John Russell

Researchers Measure Impact of ‘Meltdown’ and ‘Spectre’ Patches on HPC Workloads

January 17, 2018

Computer scientists from the Center for Computational Research, State University of New York (SUNY), University at Buffalo have examined the effect of Meltdown Read more…

By Tiffany Trader

Fostering Lustre Advancement Through Development and Contributions

January 17, 2018

Six months after organizational changes at Intel's High Performance Data (HPDD) division, most in the Lustre community have shed any initial apprehension aroun Read more…

By Carlos Aoki Thomaz

When the Chips Are Down

January 11, 2018

In the last article, "The High Stakes Semiconductor Game that Drives HPC Diversity," I alluded to the challenges facing the semiconductor industry and how that may impact the evolution of HPC systems over the next few years. I thought I’d lift the covers a little and look at some of the commercial challenges that impact the component technology we use in HPC. Read more…

By Dairsie Latimer

How Meltdown and Spectre Patches Will Affect HPC Workloads

January 10, 2018

There have been claims that the fixes for the Meltdown and Spectre security vulnerabilities, named the KPTI (aka KAISER) patches, are going to affect applicatio Read more…

By Rosemary Francis

Momentum Builds for US Exascale

January 9, 2018

2018 looks to be a great year for the U.S. exascale program. The last several months of 2017 revealed a number of important developments that help put the U.S. Read more…

By Alex R. Larzelere

ANL’s Rick Stevens on CANDLE, ARM, Quantum, and More

January 8, 2018

Late last year HPCwire caught up with Rick Stevens, associate laboratory director for computing, environment and life Sciences at Argonne National Laboratory, f Read more…

By John Russell

Inventor Claims to Have Solved Floating Point Error Problem

January 17, 2018

"The decades-old floating point error problem has been solved," proclaims a press release from inventor Alan Jorgensen. The computer scientist has filed for and Read more…

By Tiffany Trader

US Coalesces Plans for First Exascale Supercomputer: Aurora in 2021

September 27, 2017

At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, in Arlington, Va., yesterday (Sept. 26), it was revealed that the "Aurora" supercompute Read more…

By Tiffany Trader

Japan Unveils Quantum Neural Network

November 22, 2017

The U.S. and China are leading the race toward productive quantum computing, but it's early enough that ultimate leadership is still something of an open questi Read more…

By Tiffany Trader

AMD Showcases Growing Portfolio of EPYC and Radeon-based Systems at SC17

November 13, 2017

AMD’s charge back into HPC and the datacenter is on full display at SC17. Having launched the EPYC processor line in June along with its MI25 GPU the focus he Read more…

By John Russell

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

IBM Begins Power9 Rollout with Backing from DOE, Google

December 6, 2017

After over a year of buildup, IBM is unveiling its first Power9 system based on the same architecture as the Department of Energy CORAL supercomputers, Summit a Read more…

By Tiffany Trader

Fast Forward: Five HPC Predictions for 2018

December 21, 2017

What’s on your list of high (and low) lights for 2017? Volta 100’s arrival on the heels of the P100? Appearance, albeit late in the year, of IBM’s Power9? Read more…

By John Russell

Chip Flaws ‘Meltdown’ and ‘Spectre’ Loom Large

January 4, 2018

The HPC and wider tech community have been abuzz this week over the discovery of critical design flaws that impact virtually all contemporary microprocessors. T Read more…

By Tiffany Trader

Leading Solution Providers

Perspective: What Really Happened at SC17?

November 22, 2017

SC is over. Now comes the myriad of follow-ups. Inboxes are filled with templated emails from vendors and other exhibitors hoping to win a place in the post-SC thinking of booth visitors. Attendees of tutorials, workshops and other technical sessions will be inundated with requests for feedback. Read more…

By Andrew Jones

Tensors Come of Age: Why the AI Revolution Will Help HPC

November 13, 2017

Thirty years ago, parallel computing was coming of age. A bitter battle began between stalwart vector computing supporters and advocates of various approaches to parallel computing. IBM skeptic Alan Karp, reacting to announcements of nCUBE’s 1024-microprocessor system and Thinking Machines’ 65,536-element array, made a public $100 wager that no one could get a parallel speedup of over 200 on real HPC workloads. Read more…

By John Gustafson & Lenore Mullin

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Flipping the Flops and Reading the Top500 Tea Leaves

November 13, 2017

The 50th edition of the Top500 list, the biannual publication of the world’s fastest supercomputers based on public Linpack benchmarking results, was released Read more…

By Tiffany Trader

How Meltdown and Spectre Patches Will Affect HPC Workloads

January 10, 2018

There have been claims that the fixes for the Meltdown and Spectre security vulnerabilities, named the KPTI (aka KAISER) patches, are going to affect applicatio Read more…

By Rosemary Francis

GlobalFoundries, Ayar Labs Team Up to Commercialize Optical I/O

December 4, 2017

GlobalFoundries (GF) and Ayar Labs, a startup focused on using light, instead of electricity, to transfer data between chips, today announced they've entered in Read more…

By Tiffany Trader

HPC Chips – A Veritable Smorgasbord?

October 10, 2017

For the first time since AMD's ill-fated launch of Bulldozer the answer to the question, 'Which CPU will be in my next HPC system?' doesn't have to be 'Whichever variety of Intel Xeon E5 they are selling when we procure'. Read more…

By Dairsie Latimer

Nvidia, Partners Announce Several V100 Servers

September 27, 2017

Here come the Volta 100-based servers. Nvidia today announced an impressive line-up of servers from major partners – Dell EMC, Hewlett Packard Enterprise, IBM Read more…

By John Russell

  • arrow
  • Click Here for More Headlines
  • arrow
Share This