Chipmakers Look to Rock High-End Server Biz

By Michael Feldman

April 1, 2010

The x86 CPU festivities are over for now, but the party’s just getting started. The debut of the latest Intel Xeon and AMD Opteron processors over the last few weeks marks something of a turning point for server makers. For one thing, the introduction of Intel’s 6-core Westmere EP and 8-core Nehalem EX CPUs, and AMD’s 12-core Magny-Cours processor marks the beginning of the end of the quad-core era. Given that, HPC servers with fewer than double-digit core counts will soon be the exception rather than the rule.

AMD and Intel are attacking the high-server space somewhat differently, though. With Westmere EP (now the Xeon 5600), Intel is continuing its traditional 2P server business. But with Nehalem EX (now the Xeon 7500), Intel is charting new territory — big shared memory SMP machines. Intel also introduced the Xeon 6500, a 2P-only variant of Nehalem EX, ostensibly aimed at the HPC market. Meanwhile AMD has consolidated its performance-oriented 2P and 4P products into a single Opteron 6000 product line, starting with Magny-Cours (now the Opteron 6100).

From a price-performance perspective AMD has a good story. With the 6100 Opterons, AMD will go head-to-head with the 2P 5600 Xeons, which have faster cores, but fewer of them. The mid-range Opteron 6174, which sports 12 cores and runs at 2.2 GHz, costs $1,165 in quantity. A Xeon with comparable performance is the 6-core X5680, which is clocked at 3.33 GHz and costs $1664. Although the individual Xeon cores run faster, for many types of parallel workloads, the additional six cores on the Opteron will make up the difference, and then some. The fact that the Intel architecture implements HyperThreading, which handles two threads per core, only boosts performance by 10 to 20 percent. And in some cases, such as Linpack, it doesn’t help at all. Since the 6100 Opterons have four channels of memory and support up to 12 DIMM slots per socket, compared to three channels and nine DIMMs for the Xeon 5600s, the AMD CPUs have an additional advantage on memory-loving apps.

The 6100 Opterons will also go up against the 6500 Xeons in the 2P arena, as well as the 7500 Xeons in the 4P space. Here the Xeons go up to eight cores, the memory channel differential has been equalized at four apiece, and the memory capacity advantage is now with Intel at 16 DIMMs per socket. But the EX-class parts are even more expensive than Xeon 5600 chips. For example, the 8-core 6500 and 7500 products cost between $2,461 and $3,692, which is more than two and three times the price, respectively, of the Opteron 6174 mentioned above. Even the least expensive 6-core EX, which is the 1.86 GHz Xeon x7530, costs $200 more than the 6174.

The bottom line is that the new Magny-Cours processors look like a very competitive solution for 2P and 4P servers. But the 4P story is particularly interesting. AMD is pushing this 6000 series as a platform that does away with the “4P tax.” The tax refers to the traditional premium vendors charged for CPUs and chipsets that support 4-socket servers. Since the 6000 hardware can be used in both 2P and 4P boxes, you can actually save money by consolidating dual-socket servers (as long as you don’t need to spread out the processors over more boxes to get at more I/O). “The only reason 4P processors have been priced like they have is because there’s a guy in the business who owns a large chunk of the market and has been pricing that way for 20 years,” says John Fruehe, who heads AMD’s Product Marketing of the Server and Workstation Division. “It’s more tradition than technology that has forced that price.”

That “guy,” that Fruehe is referring to is, of course, Intel. But prior to Magny-Cours, AMD also priced its 4P/8P Opteron 8000 CPUs at a premium in relation to its 2P Opteron 2000 parts. But according to him, they eventually came to the conclusion that the demand for 4P servers was being inhibited by this pricing model. In fact, according to Fruehe, the quad-socket Opteron-based supercomputers on the TOP500 list came about because AMD gave the system vendors a nice volume discount on Opteron 8000 CPUs. “Generally speaking those were deals where an 8000 processor was priced like a 2000,” he told me. “Suddenly the economics made sense.”

Although he wouldn’t point to any specific systems, the half-petaflop “Ranger” Sun Constellation cluster at TACC, which uses quad-socket Opteron-based blades, almost certainly fits in this category. Fruehe maintains AMD still turned a profit on these supercomputer deals, but it gave them the idea that it could move a lot more product by pricing 4P parts like 2P parts. They believe that this strategy will unleash this market in HPC and across enterprise computing.

On the other hand, AMD has decided leave the 8P (and above), at least for the time being. At 60K or so processors per year, the company has calculated this is too small a market to give special consideration to. One might ask, though: If the 4P servers are such a good idea, why not 8P, 16P and so on? As you keep adding processors, or cores for that matter, memory bandwidth and capacity become the limiting factor. As AMD and Intel keep pouring on the cores, they’re forced to rebalance the memory subsystem.

The idea behind the new Xeon 7500 line is to max out both compute and memory in a familiar x86 package. As of this week, OEMs can build 8-socket commodity boxes with 1 TB of memory. With this approach, not only does Intel think it can edge out proprietary RISC CPUs in SMP servers used for mission-critical computing, it also believes it can grow the SMP market overall.

According to David Kanter at Real World Technologies, that might indeed come to pass. Although in the past there were multiple reasons that 8P servers represented a specialty market, a confluence of commodity technologies, including the new Xeons themselves, are changing the economics. In a recent article, Kanter writes:

The primary barriers to adoption for large x86 servers are software, maturity and cost/benefit. Scalable applications that would benefit from 8S servers are not common. Some classic examples include I/O heavy workloads like ERP, transactional or analytic databases and also select HPC workloads that favor shared memory rather than message passing. More recently, server consolidation using virtualization has emerged as an important workload. In 2010, there are simply more scalable workloads than were previously available.

Kanter goes on to analyze how the different pieces of the enterprise ecosystem are evolving, and how they could favor a shift to commodity 8P servers. For now, AMD seems content to play it conservative and let Intel test the SMP waters. If successful, perhaps the junior member of the x86 franchise will jump in after Intel has built the market. In the meantime, AMD is focused on rebuilding its server mojo in the 2P and 4P sweet spots. Magny-Cours looks like a fine start.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Nvidia Shares Recipe to Accelerate AI Cloud Adoption

May 29, 2017

In March, Nvidia revealed blueprints for a new open source Tesla GPU-based accelerator – HGX-1 – developed for clouds with Microsoft under its Project Olym Read more…

By Tiffany Trader

Doug Kothe on the Race to Build Exascale Applications

May 29, 2017

Ensuring there are applications ready to churn out useful science when the first U.S. exascale computers arrive in the 2021-2023 timeframe is Doug Kothe’s job Read more…

By John Russell

PRACEdays Reflects Europe’s HPC Commitment

May 25, 2017

More than 250 attendees and participants came together for PRACEdays17 in Barcelona last week, part of the European HPC Summit Week 2017, held May 15-19 at t Read more…

By Tiffany Trader

Russian Researchers Claim First Quantum-Safe Blockchain

May 25, 2017

The Russian Quantum Center today announced it has overcome the threat of quantum cryptography by creating the first quantum-safe blockchain, securing cryptocurr Read more…

By Doug Black

HPE Extreme Performance Solutions

Exploring the Three Models of Remote Visualization

The explosion of data and advancement of digital technologies are dramatically changing the way many companies do business. With the help of high performance computing (HPC) solutions and data analytics platforms, manufacturers are developing products faster, healthcare providers are improving patient care, and energy companies are improving planning, exploration, and production. Read more…

Google Debuts TPU v2 and will Add to Google Cloud

May 25, 2017

Not long after stirring attention in the deep learning/AI community by revealing the details of its Tensor Processing Unit (TPU), Google last week announced the Read more…

By John Russell

Nvidia CEO Predicts AI ‘Cambrian Explosion’

May 25, 2017

The processing power and cloud access to developer tools used to train machine-learning models are making artificial intelligence ubiquitous across computing pl Read more…

By George Leopold

PGAS Use will Rise on New H/W Trends, Says Reinders

May 25, 2017

If you have not already tried using PGAS, it is time to consider adding PGAS to the programming techniques you know. Partitioned Global Array Space, commonly kn Read more…

By James Reinders

Exascale Escapes 2018 Budget Axe; Rest of Science Suffers

May 23, 2017

President Trump's proposed $4.1 trillion FY 2018 budget is good for U.S. exascale computing development, but grim for the rest of science and technology spend Read more…

By Tiffany Trader

Nvidia Shares Recipe to Accelerate AI Cloud Adoption

May 29, 2017

In March, Nvidia revealed blueprints for a new open source Tesla GPU-based accelerator – HGX-1 – developed for clouds with Microsoft under its Project Olym Read more…

By Tiffany Trader

Doug Kothe on the Race to Build Exascale Applications

May 29, 2017

Ensuring there are applications ready to churn out useful science when the first U.S. exascale computers arrive in the 2021-2023 timeframe is Doug Kothe’s job Read more…

By John Russell

PRACEdays Reflects Europe’s HPC Commitment

May 25, 2017

More than 250 attendees and participants came together for PRACEdays17 in Barcelona last week, part of the European HPC Summit Week 2017, held May 15-19 at t Read more…

By Tiffany Trader

PGAS Use will Rise on New H/W Trends, Says Reinders

May 25, 2017

If you have not already tried using PGAS, it is time to consider adding PGAS to the programming techniques you know. Partitioned Global Array Space, commonly kn Read more…

By James Reinders

Exascale Escapes 2018 Budget Axe; Rest of Science Suffers

May 23, 2017

President Trump's proposed $4.1 trillion FY 2018 budget is good for U.S. exascale computing development, but grim for the rest of science and technology spend Read more…

By Tiffany Trader

Cray Offers Supercomputing as a Service, Targets Biotechs First

May 16, 2017

Leading supercomputer vendor Cray and datacenter/cloud provider the Markley Group today announced plans to jointly deliver supercomputing as a service. The init Read more…

By John Russell

HPE’s Memory-centric The Machine Coming into View, Opens ARMs to 3rd-party Developers

May 16, 2017

Announced three years ago, HPE’s The Machine is said to be the largest R&D program in the venerable company’s history, one that could be progressing tow Read more…

By Doug Black

What’s Up with Hyperion as It Transitions From IDC?

May 15, 2017

If you’re wondering what’s happening with Hyperion Research – formerly the IDC HPC group – apparently you are not alone, says Steve Conway, now senior V Read more…

By John Russell

Quantum Bits: D-Wave and VW; Google Quantum Lab; IBM Expands Access

March 21, 2017

For a technology that’s usually characterized as far off and in a distant galaxy, quantum computing has been steadily picking up steam. Just how close real-wo Read more…

By John Russell

Trump Budget Targets NIH, DOE, and EPA; No Mention of NSF

March 16, 2017

President Trump’s proposed U.S. fiscal 2018 budget issued today sharply cuts science spending while bolstering military spending as he promised during the cam Read more…

By John Russell

Google Pulls Back the Covers on Its First Machine Learning Chip

April 6, 2017

This week Google released a report detailing the design and performance characteristics of the Tensor Processing Unit (TPU), its custom ASIC for the inference Read more…

By Tiffany Trader

HPC Compiler Company PathScale Seeks Life Raft

March 23, 2017

HPCwire has learned that HPC compiler company PathScale has fallen on difficult times and is asking the community for help or actively seeking a buyer for its a Read more…

By Tiffany Trader

CPU-based Visualization Positions for Exascale Supercomputing

March 16, 2017

Since our first formal product releases of OSPRay and OpenSWR libraries in 2016, CPU-based Software Defined Visualization (SDVis) has achieved wide-spread adopt Read more…

By Jim Jeffers, Principal Engineer and Engineering Leader, Intel

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Last week, Google reported that its custom ASIC Tensor Processing Unit (TPU) was 15-30x faster for inferencing workloads than Nvidia's K80 GPU (see our coverage Read more…

By Tiffany Trader

Nvidia’s Mammoth Volta GPU Aims High for AI, HPC

May 10, 2017

At Nvidia's GPU Technology Conference (GTC17) in San Jose, Calif., this morning, CEO Jensen Huang announced the company's much-anticipated Volta architecture a Read more…

By Tiffany Trader

TSUBAME3.0 Points to Future HPE Pascal-NVLink-OPA Server

February 17, 2017

Since our initial coverage of the TSUBAME3.0 supercomputer yesterday, more details have come to light on this innovative project. Of particular interest is a ne Read more…

By Tiffany Trader

Leading Solution Providers

Facebook Open Sources Caffe2; Nvidia, Intel Rush to Optimize

April 18, 2017

From its F8 developer conference in San Jose, Calif., today, Facebook announced Caffe2, a new open-source, cross-platform framework for deep learning. Caffe2 is Read more…

By Tiffany Trader

Tokyo Tech’s TSUBAME3.0 Will Be First HPE-SGI Super

February 16, 2017

In a press event Friday afternoon local time in Japan, Tokyo Institute of Technology (Tokyo Tech) announced its plans for the TSUBAME3.0 supercomputer, which w Read more…

By Tiffany Trader

Is Liquid Cooling Ready to Go Mainstream?

February 13, 2017

Lost in the frenzy of SC16 was a substantial rise in the number of vendors showing server oriented liquid cooling technologies. Three decades ago liquid cooling Read more…

By Steve Campbell

MIT Mathematician Spins Up 220,000-Core Google Compute Cluster

April 21, 2017

On Thursday, Google announced that MIT math professor and computational number theorist Andrew V. Sutherland had set a record for the largest Google Compute Eng Read more…

By Tiffany Trader

US Supercomputing Leaders Tackle the China Question

March 15, 2017

As China continues to prove its supercomputing mettle via the Top500 list and the forward march of its ambitious plans to stand up an exascale machine by 2020, Read more…

By Tiffany Trader

HPC Technique Propels Deep Learning at Scale

February 21, 2017

Researchers from Baidu's Silicon Valley AI Lab (SVAIL) have adapted a well-known HPC communication technique to boost the speed and scale of their neural networ Read more…

By Tiffany Trader

DOE Supercomputer Achieves Record 45-Qubit Quantum Simulation

April 13, 2017

In order to simulate larger and larger quantum systems and usher in an age of "quantum supremacy," researchers are stretching the limits of today's most advance Read more…

By Tiffany Trader

Knights Landing Processor with Omni-Path Makes Cloud Debut

April 18, 2017

HPC cloud specialist Rescale is partnering with Intel and HPC resource provider R Systems to offer first-ever cloud access to Xeon Phi "Knights Landing" process Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This