One Group’s Answer to Transistors Behaving Badly

By Michael Feldman

May 11, 2010

Over the last 50 years, the semiconductor business has enjoyed what is perhaps the most thrilling ride of any industry ever conceived. Today semiconductors are a $250 billion business that account for nearly 10 percent of the world’s GDP. At the foundation of its success is Moore’s Law, the chipmaker’s mantra that promises better, faster and cheaper transistors every 18 to 24 months. But the laws of physics are conspiring to bring this ride to an end.

The problems are well known. CMOS-based transistors are increasingly harder to manufacture at nanometer scale. And even as technologies are perfected to do so, the materials themselves are becoming unsuitable for such small geometries. At 22 nm, Intel’s process node slated for 2011, gate oxide will be only 4 to 5 atoms thick and the gates themselves will be 42 atoms across. Manufacturing these devices in reasonable volumes and within reasonable power envelopes is going to be a challenge.

In fact, the analyst team at iSuppli has predicted that the expense of manufacturing sub-20nm devices would not be economically feasible. That is, the cost of the fabs could not be recouped by the volume of chips produced at those process nodes. Thus, they concluded, Moore’s Law would be repealed in about five years.

Most of the efforts to address the problem of shrinking transistor geometries have focused on making the devices behave more precisely, using technologies like X-ray lithography and hafnium insulators, to name just two. But what if instead of trying to make the transistors better, we purposefully try to make them worse.

Although it sounds counter-intuitive, developing processors that are naturally error-prone is exactly what one team of researchers from the University of Illinois and the University of California, San Diego has set out to do. Called stochastic processors, the idea is to under-design the hardware, such that it is allowed to behave non-deterministically under both stressful and nominal conditions. Error tolerance can be provided by either the hardware or the software.

The rationale is that by relaxing the design and manufacturing constraints, it will be much simpler and much cheaper to produce such processors in volume. And because voltage scaling and clock frequency restrictions are eased, significant power savings and performance increases can be realized.

The stochastic model would represent a significant departure from the way semiconductor devices are designed today. Even though processors have evolved significantly over the decades — scalar to superscalar, single-core to multicore, etc. — the basic assumption has always been that the hardware must behave flawlessly. “It’s the contract that the hardware provides to the software today,” says Rakesh Kumar, a computer scientist at the University of Illinois, Urbana-Champaign, who is part of the Stochastic Processor Research group there. The research is being funded by Intel, DARPA, the NSF, and the GigaScale Systems Research Center (GSRC), a consortium of academic, government and industry organizations devoted to next-generation hardware and software.

The idea behind stochastic processors is relatively simple: Build a chip that computes correctly, say, 99 percent of the time. Such a device is specifically designed to let errors occur under both worst-case and nominal conditions. The advantage of this model is that, compared to a 100 percent error-free processor, a stochastic implementation requires a lot less manufacturing precision and takes a lot less power to run.

Kumar’s stochastic research group has designed a Niagara processor (an open source processor design developed by Sun Microsystems) that allows for a 1 to 4 percent error rate. Based on circuit level simulation with CAD design tools, the researchers determined they could save between 25 to 40 percent on power compared to the default (deterministic) design. That might seem like a lot, but it points to how much of a traditional processor design is now being devoted to keeping the transistors from throwing off errors.

It also explains why multicore designs introduce another level of challenges for chipmakers. For example, if two of the cores on a quad-core processor can run (flawlessly) at 2.0 GHz, one can run at 1.5 GHz, and the last core can only run error-free at 1.0 GHz, the chip has to be binned at 1.0 GHz. That’s money down the drain as far as the chipmaker is concerned. Ideally, they would like to ship a 2.0 GHz product and use some sort of scheme to compensate for the variability in the other two cores. A stochastic design would make this possible.

Of course, compensating for that variability is the tricky part. Kumar says error tolerance can be accomplished in hardware or in software. Hardware correction would be the most obvious and, from the programmer’s perspective, the most palatable way to ensure correct program execution. But error tolerance in software provides more flexibility.

“Our vision is that all the errors that are produced get tolerated by the software,” says Kumar. Part of the group’s research involves how to write application software in such a way that takes into account a non-deterministic processor. Kumar believes this shift in thinking is inevitable. Because the hardware variability problem is going to keep getting worse as process geometries shrink, it will eventually make more sense for the programmer to code for non-determinism rather that write the software for the least common denominator hardware. On balance, Kumar believes the ideal would be to employ hardware correction only when it is too onerous to compensate for the errors in software.

HPC applications might be especially at home on stochastic processors since many of these codes are fundamentally optimization problems. In other words, they are noise tolerant to a great extent, relying on probability distributions rather than a single correct computation. Monte Carlo methods are just one example of a class of algorithms used in HPC that rely on optimization techniques, but almost any simulation or matrix math-based code has some level of optimization built in — think climate modeling, data mining, and object recognition apps. In these cases, says Kumar, “you’re not going after one answer, you’re going after a good answer.”

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

RSC Reports 500Tflops, Hot Water Cooled System Deployed at JINR

April 18, 2018

RSC, developer of supercomputers and advanced HPC systems based in Russia, today reported deployment of “the world's first 100% ‘hot water’ liquid cooled supercomputer” at Joint Institute for Nuclear Research (JI Read more…

By Staff

New Device Spots Quantum Particle ‘Fingerprint’

April 18, 2018

Majorana particles have been observed by university researchers employing a device consisting of layers of magnetic insulators on a superconducting material. The advance opens the door to controlling the elusive particle Read more…

By George Leopold

Cray Rolls Out AMD-Based CS500; More to Follow?

April 18, 2018

Cray was the latest OEM to bring AMD back into the fold with introduction today of a CS500 option based on AMD’s Epyc processor line. The move follows Cray’s introduction of an ARM-based system (XC-50) last November. Read more…

By John Russell

HPE Extreme Performance Solutions

Hybrid HPC is Speeding Time to Insight and Revolutionizing Medicine

High performance computing (HPC) is a key driver of success in many verticals today, and health and life science industries are extensively leveraging these capabilities. Read more…

Hennessy & Patterson: A New Golden Age for Computer Architecture

April 17, 2018

On Monday June 4, 2018, 2017 A.M. Turing Award Winners John L. Hennessy and David A. Patterson will deliver the Turing Lecture at the 45th International Symposium on Computer Architecture (ISCA) in Los Angeles. The Read more…

By Staff

Cray Rolls Out AMD-Based CS500; More to Follow?

April 18, 2018

Cray was the latest OEM to bring AMD back into the fold with introduction today of a CS500 option based on AMD’s Epyc processor line. The move follows Cray’ Read more…

By John Russell

IBM: Software Ecosystem for OpenPOWER is Ready for Prime Time

April 16, 2018

With key pieces of the IBM/OpenPOWER versus Intel/x86 gambit settling into place – e.g., the arrival of Power9 chips and Power9-based systems, hyperscaler sup Read more…

By John Russell

US Plans $1.8 Billion Spend on DOE Exascale Supercomputing

April 11, 2018

On Monday, the United States Department of Energy announced its intention to procure up to three exascale supercomputers at a cost of up to $1.8 billion with th Read more…

By Tiffany Trader

Cloud-Readiness and Looking Beyond Application Scaling

April 11, 2018

There are two aspects to consider when determining if an application is suitable for running in the cloud. The first, which we will discuss here under the title Read more…

By Chris Downing

Transitioning from Big Data to Discovery: Data Management as a Keystone Analytics Strategy

April 9, 2018

The past 10-15 years has seen a stark rise in the density, size, and diversity of scientific data being generated in every scientific discipline in the world. Key among the sciences has been the explosion of laboratory technologies that generate large amounts of data in life-sciences and healthcare research. Large amounts of data are now being stored in very large storage name spaces, with little to no organization and a general unease about how to approach analyzing it. Read more…

By Ari Berman, BioTeam, Inc.

IBM Expands Quantum Computing Network

April 5, 2018

IBM is positioning itself as a first mover in establishing the era of commercial quantum computing. The company believes in order for quantum to work, taming qu Read more…

By Tiffany Trader

FY18 Budget & CORAL-2 – Exascale USA Continues to Move Ahead

April 2, 2018

It was not pretty. However, despite some twists and turns, the federal government’s Fiscal Year 2018 (FY18) budget is complete and ended with some very positi Read more…

By Alex R. Larzelere

Nvidia Ups Hardware Game with 16-GPU DGX-2 Server and 18-Port NVSwitch

March 27, 2018

Nvidia unveiled a raft of new products from its annual technology conference in San Jose today, and despite not offering up a new chip architecture, there were still a few surprises in store for HPC hardware aficionados. Read more…

By Tiffany Trader

Inventor Claims to Have Solved Floating Point Error Problem

January 17, 2018

"The decades-old floating point error problem has been solved," proclaims a press release from inventor Alan Jorgensen. The computer scientist has filed for and Read more…

By Tiffany Trader

Researchers Measure Impact of ‘Meltdown’ and ‘Spectre’ Patches on HPC Workloads

January 17, 2018

Computer scientists from the Center for Computational Research, State University of New York (SUNY), University at Buffalo have examined the effect of Meltdown Read more…

By Tiffany Trader

Russian Nuclear Engineers Caught Cryptomining on Lab Supercomputer

February 12, 2018

Nuclear scientists working at the All-Russian Research Institute of Experimental Physics (RFNC-VNIIEF) have been arrested for using lab supercomputing resources to mine crypto-currency, according to a report in Russia’s Interfax News Agency. Read more…

By Tiffany Trader

How the Cloud Is Falling Short for HPC

March 15, 2018

The last couple of years have seen cloud computing gradually build some legitimacy within the HPC world, but still the HPC industry lies far behind enterprise I Read more…

By Chris Downing

Chip Flaws ‘Meltdown’ and ‘Spectre’ Loom Large

January 4, 2018

The HPC and wider tech community have been abuzz this week over the discovery of critical design flaws that impact virtually all contemporary microprocessors. T Read more…

By Tiffany Trader

Fast Forward: Five HPC Predictions for 2018

December 21, 2017

What’s on your list of high (and low) lights for 2017? Volta 100’s arrival on the heels of the P100? Appearance, albeit late in the year, of IBM’s Power9? Read more…

By John Russell

How Meltdown and Spectre Patches Will Affect HPC Workloads

January 10, 2018

There have been claims that the fixes for the Meltdown and Spectre security vulnerabilities, named the KPTI (aka KAISER) patches, are going to affect applicatio Read more…

By Rosemary Francis

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Leading Solution Providers

Deep Learning at 15 PFlops Enables Training for Extreme Weather Identification at Scale

March 19, 2018

Petaflop per second deep learning training performance on the NERSC (National Energy Research Scientific Computing Center) Cori supercomputer has given climate Read more…

By Rob Farber

Lenovo Unveils Warm Water Cooled ThinkSystem SD650 in Rampup to LRZ Install

February 22, 2018

This week Lenovo took the wraps off the ThinkSystem SD650 high-density server with third-generation direct water cooling technology developed in tandem with par Read more…

By Tiffany Trader

AI Cloud Competition Heats Up: Google’s TPUs, Amazon Building AI Chip

February 12, 2018

Competition in the white hot AI (and public cloud) market pits Google against Amazon this week, with Google offering AI hardware on its cloud platform intended Read more…

By Doug Black

HPC and AI – Two Communities Same Future

January 25, 2018

According to Al Gara (Intel Fellow, Data Center Group), high performance computing and artificial intelligence will increasingly intertwine as we transition to Read more…

By Rob Farber

New Blueprint for Converging HPC, Big Data

January 18, 2018

After five annual workshops on Big Data and Extreme-Scale Computing (BDEC), a group of international HPC heavyweights including Jack Dongarra (University of Te Read more…

By John Russell

US Plans $1.8 Billion Spend on DOE Exascale Supercomputing

April 11, 2018

On Monday, the United States Department of Energy announced its intention to procure up to three exascale supercomputers at a cost of up to $1.8 billion with th Read more…

By Tiffany Trader

Momentum Builds for US Exascale

January 9, 2018

2018 looks to be a great year for the U.S. exascale program. The last several months of 2017 revealed a number of important developments that help put the U.S. Read more…

By Alex R. Larzelere

Google Chases Quantum Supremacy with 72-Qubit Processor

March 7, 2018

Google pulled ahead of the pack this week in the race toward "quantum supremacy," with the introduction of a new 72-qubit quantum processor called Bristlecone. Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This