Over the last 50 years, the semiconductor business has enjoyed what is perhaps the most thrilling ride of any industry ever conceived. Today semiconductors are a $250 billion business that account for nearly 10 percent of the world’s GDP. At the foundation of its success is Moore’s Law, the chipmaker’s mantra that promises better, faster and cheaper transistors every 18 to 24 months. But the laws of physics are conspiring to bring this ride to an end.
The problems are well known. CMOS-based transistors are increasingly harder to manufacture at nanometer scale. And even as technologies are perfected to do so, the materials themselves are becoming unsuitable for such small geometries. At 22 nm, Intel’s process node slated for 2011, gate oxide will be only 4 to 5 atoms thick and the gates themselves will be 42 atoms across. Manufacturing these devices in reasonable volumes and within reasonable power envelopes is going to be a challenge.
In fact, the analyst team at iSuppli has predicted that the expense of manufacturing sub-20nm devices would not be economically feasible. That is, the cost of the fabs could not be recouped by the volume of chips produced at those process nodes. Thus, they concluded, Moore’s Law would be repealed in about five years.
Most of the efforts to address the problem of shrinking transistor geometries have focused on making the devices behave more precisely, using technologies like X-ray lithography and hafnium insulators, to name just two. But what if instead of trying to make the transistors better, we purposefully try to make them worse.
Although it sounds counter-intuitive, developing processors that are naturally error-prone is exactly what one team of researchers from the University of Illinois and the University of California, San Diego has set out to do. Called stochastic processors, the idea is to under-design the hardware, such that it is allowed to behave non-deterministically under both stressful and nominal conditions. Error tolerance can be provided by either the hardware or the software.
The rationale is that by relaxing the design and manufacturing constraints, it will be much simpler and much cheaper to produce such processors in volume. And because voltage scaling and clock frequency restrictions are eased, significant power savings and performance increases can be realized.
The stochastic model would represent a significant departure from the way semiconductor devices are designed today. Even though processors have evolved significantly over the decades — scalar to superscalar, single-core to multicore, etc. — the basic assumption has always been that the hardware must behave flawlessly. “It’s the contract that the hardware provides to the software today,” says Rakesh Kumar, a computer scientist at the University of Illinois, Urbana-Champaign, who is part of the Stochastic Processor Research group there. The research is being funded by Intel, DARPA, the NSF, and the GigaScale Systems Research Center (GSRC), a consortium of academic, government and industry organizations devoted to next-generation hardware and software.
The idea behind stochastic processors is relatively simple: Build a chip that computes correctly, say, 99 percent of the time. Such a device is specifically designed to let errors occur under both worst-case and nominal conditions. The advantage of this model is that, compared to a 100 percent error-free processor, a stochastic implementation requires a lot less manufacturing precision and takes a lot less power to run.
Kumar’s stochastic research group has designed a Niagara processor (an open source processor design developed by Sun Microsystems) that allows for a 1 to 4 percent error rate. Based on circuit level simulation with CAD design tools, the researchers determined they could save between 25 to 40 percent on power compared to the default (deterministic) design. That might seem like a lot, but it points to how much of a traditional processor design is now being devoted to keeping the transistors from throwing off errors.
It also explains why multicore designs introduce another level of challenges for chipmakers. For example, if two of the cores on a quad-core processor can run (flawlessly) at 2.0 GHz, one can run at 1.5 GHz, and the last core can only run error-free at 1.0 GHz, the chip has to be binned at 1.0 GHz. That’s money down the drain as far as the chipmaker is concerned. Ideally, they would like to ship a 2.0 GHz product and use some sort of scheme to compensate for the variability in the other two cores. A stochastic design would make this possible.
Of course, compensating for that variability is the tricky part. Kumar says error tolerance can be accomplished in hardware or in software. Hardware correction would be the most obvious and, from the programmer’s perspective, the most palatable way to ensure correct program execution. But error tolerance in software provides more flexibility.
“Our vision is that all the errors that are produced get tolerated by the software,” says Kumar. Part of the group’s research involves how to write application software in such a way that takes into account a non-deterministic processor. Kumar believes this shift in thinking is inevitable. Because the hardware variability problem is going to keep getting worse as process geometries shrink, it will eventually make more sense for the programmer to code for non-determinism rather that write the software for the least common denominator hardware. On balance, Kumar believes the ideal would be to employ hardware correction only when it is too onerous to compensate for the errors in software.
HPC applications might be especially at home on stochastic processors since many of these codes are fundamentally optimization problems. In other words, they are noise tolerant to a great extent, relying on probability distributions rather than a single correct computation. Monte Carlo methods are just one example of a class of algorithms used in HPC that rely on optimization techniques, but almost any simulation or matrix math-based code has some level of optimization built in — think climate modeling, data mining, and object recognition apps. In these cases, says Kumar, “you’re not going after one answer, you’re going after a good answer.”