Cray Unveils “Baker” Supercomputer

By Michael Feldman

May 25, 2010

Supercomputer maker Cray did a pre-launch of sorts for its upcoming “Baker” supercomputer on Tuesday, giving the machine its official product designation: the XE6. Although the company won’t be shipping the hardware until later this year, there’s already a backlog of orders for the petascale machines, and Cray is setting the stage for a big debut.

The XE6 represents Cray’s next-generation supercomputer that is being billed as the first x86-based machine designed to deliver sustained petaflops performance across a range of HPC applications. Although the new super is employing the same AMD CPUs as the current generation XT6 (thus retaining the ‘6’ designation for the 6th generation Opterons), the new Gemini system network provides the foundation for much more scalability and performance.

Cray is saying the new architecture will scale up to 100 teraflops of raw performance and be able to offer multiple petaflops for those applications that can take advantage of hundreds of thousands or even a million CPU cores. As such, the XE6 becomes Cray’s top-end offering for production supercomputing, costing $2 million-plus for the privilege of owning one.

The XE6 inherits a lot of its basic features from the XT6 line. Most importantly, the Opteron 6100 (Magny-Cours) compute blades are shared between the two systems. As a consequence, an XT6 installation will be able to be upgraded to an XE6 by swapping out the SeaStar interconnect hardware with Gemini parts. Likewise, an XT5 system can be upgraded to an “XE5” in the same manner.

The recently retooled Cray Linux Environment (CLE), which includes a cluster compatibility mode for ISV codes, will also be the operating systems in the XE6. Although the new OS is advertised as supporting at least 500K cores, its true upper limit will probably be tested after the first big XE6 systems are deployed.

As mentioned above, the key new feature of the design is Gemini, which provides the foundation for the XE6’s high-end capabilities. “The Gemini interconnect is really the interconnect that we’ve designed for the multicore era,” says Barry Bolding, Cray vice president of the Scalable Systems group. “It pushes those boundaries much further than the older SeaStar interconnect could do.”

Gemini supports a “high-radix” network and delivers extreme messaging rates (100 times better than SeaStar) as well as much improved latency (three times better than SeaStar). In general, a high-radix router implementation uses many narrow ports rather than fewer, wider ports. Although there are some challenges involved, the design is more able to convert pin bandwidth to reduced latency, and do so at a reduced cost. In this case, the better performance allows the XE6 to scale up to a million CPU cores and beyond.

The switch from SeaStar to Gemini is a big move for Cray, representing the first such architectural change in five years. It is similar to the older SeaStar network only inasmuch as it shares the same 3D torus topology and switchless design. Gemini actually has much more in common with the interconnect used in Cray’s X2 (Black Widow) vector-based supercomputer, and is basically an updated version of that design. According to Bolding, the company believes this high-radix architecture will be one Cray relies on for the next decade or so in all its top-of-the line supers.

One of the more interesting features enabled by Gemini is support for a global address space. Global memory is a well-known feature in SMP machines, but for distributed memory systems, has only been accomplished through software/hardware virtualization (for example, ScaleMP and 3Leaf). According to Bolding, the XE6 will be the first HPC machine with a global addressing capability in an MPP design.

Global memory support in the Gemini hardware allows an application to grab a piece of memory on a non-local node and treat it as its own (and without having to bother the OS). PGAS languages like Co-Array Fortran (CAF) and Unified Parallel C (UPC) or even SHMEM, can be used to write parallel applications that take advantage of this shared memory layout. In general, these languages enable a more straightforward way to treat data on big memory machines compared to message passing. And although not nearly as popular as the MPI-style programming, PGAS languages may become more popular as systems scale beyond the practical capabilities of message shuffling codes. Cray’s Chapel language, developed under DARPA’s High Agency’s High Productivity Computing Systems program, represents the company’s own programming environment that supports a partitioned global address space.

Besides global address support, Gemini also has smarts in it to recover from link failures and perform adaptive routing. For example, since there are multiple communication channels per node, degradation on one channel can be accommodated by rerouting traffic. A related capability enables a warm swapping of blades (without a system shutdown). This is accomplished by quieting network traffic, rerouting the packets, replacing the blade, and then restoring network traffic.

The Gemini chip itself is built by TSMC on a 90nm process node. It’s larger than the SeaStar die, but each Gemini chip can manage two nodes, so it takes the place of two SeaStar processors. According to Bolding, Gemini does use slightly more power than the two chips it replaces, but the added functionality and performance are well worth the extra few watts.

Cray already has some deep-pocketed customers lined up for XE6 installations, including the DOE’s National Energy Research Scientific Computing Center (NERSC), the High-End Computing Terascale Resource (HECToR) in the UK, the Korea Meteorological Administration (KMA), the National Nuclear Security Administration (NNSA), and the National Oceanic and Atmospheric Administration (NOAA). Cray was also tapped to deliver three XE6 supers to the US Air Force Research Laboratory, the Arctic Region Supercomputing Center and the US Army Engineer Research and Development Center. All told, more than $200 million worth of XE6 systems are on backorder.

Although the exact date that the XE6 machines will be ready for shipment is still up in the air, Cray is sticking to its previous Q3 timeframe for a production launch. And since the company is trumpeting the new super this week, it’s a good bet that it doesn’t foresee any showstoppers that would derail this schedule.

That, of course, would be good news for the supercomputer maker. First quarter sales were off to a slow start, so if the company expects to hit its yearly revenue goal of $305 to $325 million, it’s going to need to realize a significant chunk of XE6 sales in the second half of the 2010. Since a number of the announced installations are scheduled for deployment toward the end of the year, it’s going to be a photo finish for Cray.

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