Intel Unveils Plans for HPC Coprocessor

By Michael Feldman

June 1, 2010

Chipmaker Intel is reviving the Larrabee technology for the HPC market, with plans to bring a manycore coprocessor to market in the next few years. During the ISC’10 opening keynote, Kirk Skaugen, vice president of Intel’s Architecture Group and general manager of the Data Center Group, announced the chipmaker is developing what they’re calling a “Many Integrated Core” (MIC) architecture, which will be the basis of a new line of processors aimed squarely at high performance technical computing applications.

The MIC architecture, like its Larrabee ancestor, will support the standard Intel Architecture (IA), the idea being to take advantage of the large software ecosystem for the x86. Coincident with the MIC chip development, Intel will be enhancing its parallel development tools and software libraries to support the new manycore coprocessor and the heterogeneous computing model.
 
Intel’s goal is for system vendors to construct Xeon-MIC servers (or workstations), similar to that of the current crop of x86-GPGPU hybrid systems. But in the case of Xeon-MIC, it’s not really a hybrid. Since both chips are based on standard x86 instructions, it’s more like a true processor-coprocessor model. And that’s what Skaugen said would differentiate the MIC accelerator from the GPGPU model of acceleration. In the later case, new programming environments like CUDA or OpenCL need to be employed to engage the GPU component.

Although the Larrabee architecture will be used as the base technology for the new coprocessor, according to Skaugen, it will also incorporate elements of Intel’s two previous experimental terascale processors: the 80-core “Polaris” chip first demonstrated in March 2007 and the 48-core “Single-chip Cloud Computer” (SCC) that introduced in December 2009. The general design of MIC will entail dozens of simple IA cores with big SIMD vector units, all linked together by an onchip interprocessor communications fabric.

The first product, codenamed “Knights Corner,” will be built on Intel’s 22nm process node and contain more than 50 IA cores. Intel is not specifying when that product will roll out, but Skaugen did say they are on schedule to hit the 22nm process node in 2011, so, at best, we’re at least a year away from any commercial release.

A 32-core development version of the MIC coprocessor, codenamed “Knights Ferry,” is now shipping to selected customers. A team at CERN has already migrated one of its parallel C++ codes to the coprocessor development platform in “just a few days.” Intel is promising more Knights Ferry hardware will be made available to qualified users throughout 2010.

The specs on the development platform are fairly impressive. The 32-core coprocessor runs a 1.2 GHz and supports 4 threads per core for a total of 128 threads per chip. The processor also has a large (8 MB) of shared coherent cache, and supports 1 to 2 GB of (graphics) GDDR5 memory. Although not mentioned in the announcement, it is almost certain the development platform, which is basically a Larrabee graphics system, does not support ECC memory. Since ECC is a must-have for many HPC applications (and since NVIDIA’s Fermi GPU accelerator products have already incorporated ECC), I would assume this capability will be available in the first commercial MIC products.

The development platform has the MIC coprocessor hooked up the Xeon CPU via a PCIe link, but Intel is not disclosing the coprocessor setup for the first real products. It’s not too big a stretch to think Intel will want use a standard Xeon socket for the MIC so that it can take advantage of the native QPI interconnect to link the processor and coprocessor.

At ISC, Skaugen showed a performance run on a Knights Ferry platform with LU factorization, which is used to implement Linpack. Running this code, the development chip hit 517 gigaflops, a mark Skaugen said was unmatched by any other platform. Skaugen later told me that this was single precision gigaflops, not double precision, which makes the “unmatched” claim somewhat questionable to me.

One big unknown with the MIC architecture is the vector instruction set. The original Larrabee design had its own vector instructions, so IA compatibility for that chip would only take you so far. The next-generation Sandy Bridge Xeons will incorporate the new AVX instructions, which are said to double the FLOPS/clock performance. It’s not clear if MIC will eventually support AVX as well, but Skaugen did say that they are “converging” their floating point instructions toward a common set that will be used in all IA platforms.

The chipmaker’s motivation to make MIC a commercial reality is compelling. According to Intel, about 25 percent of its server chips end up in HPC systems. If they can augment those sales with high value (although not overly expensive) coprocessors, that would be a nice new revenue source for the company. The trick, of course, is for Intel to sell enough of them so as to be able to recoup the hundreds of millions of dollars in chip and software development costs.

The other aspect to this is that most people now realize that standard x86 CPUs are not going to be able to scale efficiently to millions and billions of threads — the level needed for exascale HPC. This has made the idea of simpler manycore chips with big vector units very appealing.

Unfortunately for Intel, it’s a little late to the game, having watched the first wave of GPU acceleration from the sidelines. So once again, the company will have to hit a moving target. But if Intel can produce a true x86 coprocessor with terascale performance in a couple of years, and the software stack to back it up, it will be a very interesting solution for the HPC market.

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