Intel Unveils Plans for HPC Coprocessor

By Michael Feldman

June 1, 2010

Chipmaker Intel is reviving the Larrabee technology for the HPC market, with plans to bring a manycore coprocessor to market in the next few years. During the ISC’10 opening keynote, Kirk Skaugen, vice president of Intel’s Architecture Group and general manager of the Data Center Group, announced the chipmaker is developing what they’re calling a “Many Integrated Core” (MIC) architecture, which will be the basis of a new line of processors aimed squarely at high performance technical computing applications.

The MIC architecture, like its Larrabee ancestor, will support the standard Intel Architecture (IA), the idea being to take advantage of the large software ecosystem for the x86. Coincident with the MIC chip development, Intel will be enhancing its parallel development tools and software libraries to support the new manycore coprocessor and the heterogeneous computing model.
 
Intel’s goal is for system vendors to construct Xeon-MIC servers (or workstations), similar to that of the current crop of x86-GPGPU hybrid systems. But in the case of Xeon-MIC, it’s not really a hybrid. Since both chips are based on standard x86 instructions, it’s more like a true processor-coprocessor model. And that’s what Skaugen said would differentiate the MIC accelerator from the GPGPU model of acceleration. In the later case, new programming environments like CUDA or OpenCL need to be employed to engage the GPU component.

Although the Larrabee architecture will be used as the base technology for the new coprocessor, according to Skaugen, it will also incorporate elements of Intel’s two previous experimental terascale processors: the 80-core “Polaris” chip first demonstrated in March 2007 and the 48-core “Single-chip Cloud Computer” (SCC) that introduced in December 2009. The general design of MIC will entail dozens of simple IA cores with big SIMD vector units, all linked together by an onchip interprocessor communications fabric.
MIC Coprocessor

The first product, codenamed “Knights Corner,” will be built on Intel’s 22nm process node and contain more than 50 IA cores. Intel is not specifying when that product will roll out, but Skaugen did say they are on schedule to hit the 22nm process node in 2011, so, at best, we’re at least a year away from any commercial release.

A 32-core development version of the MIC coprocessor, codenamed “Knights Ferry,” is now shipping to selected customers. A team at CERN has already migrated one of its parallel C++ codes to the coprocessor development platform in “just a few days.” Intel is promising more Knights Ferry hardware will be made available to qualified users throughout 2010.

The specs on the development platform are fairly impressive. The 32-core coprocessor runs a 1.2 GHz and supports 4 threads per core for a total of 128 threads per chip. The processor also has a large (8 MB) of shared coherent cache, and supports 1 to 2 GB of (graphics) GDDR5 memory. Although not mentioned in the announcement, it is almost certain the development platform, which is basically a Larrabee graphics system, does not support ECC memory. Since ECC is a must-have for many HPC applications (and since NVIDIA’s Fermi GPU accelerator products have already incorporated ECC), I would assume this capability will be available in the first commercial MIC products.

The development platform has the MIC coprocessor hooked up the Xeon CPU via a PCIe link, but Intel is not disclosing the coprocessor setup for the first real products. It’s not too big a stretch to think Intel will want use a standard Xeon socket for the MIC so that it can take advantage of the native QPI interconnect to link the processor and coprocessor.

At ISC, Skaugen showed a performance run on a Knights Ferry platform with LU factorization, which is used to implement Linpack. Running this code, the development chip hit 517 gigaflops, a mark Skaugen said was unmatched by any other platform. Skaugen later told me that this was single precision gigaflops, not double precision, which makes the “unmatched” claim somewhat questionable to me.

One big unknown with the MIC architecture is the vector instruction set. The original Larrabee design had its own vector instructions, so IA compatibility for that chip would only take you so far. The next-generation Sandy Bridge Xeons will incorporate the new AVX instructions, which are said to double the FLOPS/clock performance. It’s not clear if MIC will eventually support AVX as well, but Skaugen did say that they are “converging” their floating point instructions toward a common set that will be used in all IA platforms.

The chipmaker’s motivation to make MIC a commercial reality is compelling. According to Intel, about 25 percent of its server chips end up in HPC systems. If they can augment those sales with high value (although not overly expensive) coprocessors, that would be a nice new revenue source for the company. The trick, of course, is for Intel to sell enough of them so as to be able to recoup the hundreds of millions of dollars in chip and software development costs.

The other aspect to this is that most people now realize that standard x86 CPUs are not going to be able to scale efficiently to millions and billions of threads — the level needed for exascale HPC. This has made the idea of simpler manycore chips with big vector units very appealing.

Unfortunately for Intel, it’s a little late to the game, having watched the first wave of GPU acceleration from the sidelines. So once again, the company will have to hit a moving target. But if Intel can produce a true x86 coprocessor with terascale performance in a couple of years, and the software stack to back it up, it will be a very interesting solution for the HPC market.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Fluid HPC: How Extreme-Scale Computing Should Respond to Meltdown and Spectre

February 15, 2018

The Meltdown and Spectre vulnerabilities are proving difficult to fix, and initial experiments suggest security patches will cause significant performance penalties to HPC applications. Even as these patches are rolled o Read more…

By Pete Beckman

Intel Touts Silicon Spin Qubits for Quantum Computing

February 14, 2018

Debate around what makes a good qubit and how best to manufacture them is a sprawling topic. There are many insistent voices favoring one or another approach. Referencing a paper published today in Nature, Intel has offe Read more…

By John Russell

Brookhaven Ramps Up Computing for National Security Effort

February 14, 2018

Last week, Dan Coats, the director of Director of National Intelligence for the U.S., warned the Senate Intelligence Committee that Russia was likely to meddle in the 2018 mid-term U.S. elections, much as it stands accused of doing in the 2016 Presidential election. Read more…

By John Russell

HPE Extreme Performance Solutions

Safeguard Your HPC Environment with the World’s Most Secure Industry Standard Servers

Today’s organizations operate in an environment with ever-evolving threats, and in order to protect themselves they must continuously bolster their security strategy. Hewlett Packard Enterprise (HPE) and Intel® are addressing modern security challenges with the world’s most secure industry standard servers powered by the latest generation of Intel® Xeon® Scalable processors. Read more…

AI Cloud Competition Heats Up: Google’s TPUs, Amazon Building AI Chip

February 12, 2018

Competition in the white hot AI (and public cloud) market pits Google against Amazon this week, with Google offering AI hardware on its cloud platform intended to make it easier, faster and cheaper to train and run machi Read more…

By Doug Black

Fluid HPC: How Extreme-Scale Computing Should Respond to Meltdown and Spectre

February 15, 2018

The Meltdown and Spectre vulnerabilities are proving difficult to fix, and initial experiments suggest security patches will cause significant performance penal Read more…

By Pete Beckman

Brookhaven Ramps Up Computing for National Security Effort

February 14, 2018

Last week, Dan Coats, the director of Director of National Intelligence for the U.S., warned the Senate Intelligence Committee that Russia was likely to meddle in the 2018 mid-term U.S. elections, much as it stands accused of doing in the 2016 Presidential election. Read more…

By John Russell

AI Cloud Competition Heats Up: Google’s TPUs, Amazon Building AI Chip

February 12, 2018

Competition in the white hot AI (and public cloud) market pits Google against Amazon this week, with Google offering AI hardware on its cloud platform intended Read more…

By Doug Black

Russian Nuclear Engineers Caught Cryptomining on Lab Supercomputer

February 12, 2018

Nuclear scientists working at the All-Russian Research Institute of Experimental Physics (RFNC-VNIIEF) have been arrested for using lab supercomputing resources to mine crypto-currency, according to a report in Russia’s Interfax News Agency. Read more…

By Tiffany Trader

The Food Industry’s Next Journey — from Mars to Exascale

February 12, 2018

Global food producer and one of the world's leading chocolate companies Mars Inc. has a unique perspective on the impact that exascale computing will have on the food industry. Read more…

By Scott Gibson, Oak Ridge National Laboratory

Singularity HPC Container Start-Up – Sylabs – Emerges from Stealth

February 8, 2018

The driving force behind Singularity, the popular HPC container technology, is bringing the open source platform to the enterprise with the launch of a new vent Read more…

By George Leopold

Dell EMC Debuts PowerEdge Servers with AMD EPYC Chips

February 6, 2018

AMD notched another EPYC processor win today with Dell EMC’s introduction of three PowerEdge servers (R6415, R7415, and R7425) based on the EPYC 7000-series p Read more…

By John Russell

‘Next Generation’ Universe Simulation Is Most Advanced Yet

February 5, 2018

The research group that gave us the most detailed time-lapse simulation of the universe’s evolution in 2014, spanning 13.8 billion years of cosmic evolution, is back in the spotlight with an even more advanced cosmological model that is providing new insights into how black holes influence the distribution of dark matter, how heavy elements are produced and distributed, and where magnetic fields originate. Read more…

By Tiffany Trader

Inventor Claims to Have Solved Floating Point Error Problem

January 17, 2018

"The decades-old floating point error problem has been solved," proclaims a press release from inventor Alan Jorgensen. The computer scientist has filed for and Read more…

By Tiffany Trader

Japan Unveils Quantum Neural Network

November 22, 2017

The U.S. and China are leading the race toward productive quantum computing, but it's early enough that ultimate leadership is still something of an open questi Read more…

By Tiffany Trader

AMD Showcases Growing Portfolio of EPYC and Radeon-based Systems at SC17

November 13, 2017

AMD’s charge back into HPC and the datacenter is on full display at SC17. Having launched the EPYC processor line in June along with its MI25 GPU the focus he Read more…

By John Russell

Researchers Measure Impact of ‘Meltdown’ and ‘Spectre’ Patches on HPC Workloads

January 17, 2018

Computer scientists from the Center for Computational Research, State University of New York (SUNY), University at Buffalo have examined the effect of Meltdown Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

IBM Begins Power9 Rollout with Backing from DOE, Google

December 6, 2017

After over a year of buildup, IBM is unveiling its first Power9 system based on the same architecture as the Department of Energy CORAL supercomputers, Summit a Read more…

By Tiffany Trader

Fast Forward: Five HPC Predictions for 2018

December 21, 2017

What’s on your list of high (and low) lights for 2017? Volta 100’s arrival on the heels of the P100? Appearance, albeit late in the year, of IBM’s Power9? Read more…

By John Russell

Russian Nuclear Engineers Caught Cryptomining on Lab Supercomputer

February 12, 2018

Nuclear scientists working at the All-Russian Research Institute of Experimental Physics (RFNC-VNIIEF) have been arrested for using lab supercomputing resources to mine crypto-currency, according to a report in Russia’s Interfax News Agency. Read more…

By Tiffany Trader

Leading Solution Providers

Chip Flaws ‘Meltdown’ and ‘Spectre’ Loom Large

January 4, 2018

The HPC and wider tech community have been abuzz this week over the discovery of critical design flaws that impact virtually all contemporary microprocessors. T Read more…

By Tiffany Trader

Perspective: What Really Happened at SC17?

November 22, 2017

SC is over. Now comes the myriad of follow-ups. Inboxes are filled with templated emails from vendors and other exhibitors hoping to win a place in the post-SC thinking of booth visitors. Attendees of tutorials, workshops and other technical sessions will be inundated with requests for feedback. Read more…

By Andrew Jones

How Meltdown and Spectre Patches Will Affect HPC Workloads

January 10, 2018

There have been claims that the fixes for the Meltdown and Spectre security vulnerabilities, named the KPTI (aka KAISER) patches, are going to affect applicatio Read more…

By Rosemary Francis

GlobalFoundries, Ayar Labs Team Up to Commercialize Optical I/O

December 4, 2017

GlobalFoundries (GF) and Ayar Labs, a startup focused on using light, instead of electricity, to transfer data between chips, today announced they've entered in Read more…

By Tiffany Trader

Tensors Come of Age: Why the AI Revolution Will Help HPC

November 13, 2017

Thirty years ago, parallel computing was coming of age. A bitter battle began between stalwart vector computing supporters and advocates of various approaches to parallel computing. IBM skeptic Alan Karp, reacting to announcements of nCUBE’s 1024-microprocessor system and Thinking Machines’ 65,536-element array, made a public $100 wager that no one could get a parallel speedup of over 200 on real HPC workloads. Read more…

By John Gustafson & Lenore Mullin

Flipping the Flops and Reading the Top500 Tea Leaves

November 13, 2017

The 50th edition of the Top500 list, the biannual publication of the world’s fastest supercomputers based on public Linpack benchmarking results, was released Read more…

By Tiffany Trader

V100 Good but not Great on Select Deep Learning Aps, Says Xcelerit

November 27, 2017

Wringing optimum performance from hardware to accelerate deep learning applications is a challenge that often depends on the specific application in use. A benc Read more…

By John Russell

2017 Gordon Bell Prize Finalists Named

October 23, 2017

The three finalists for this year’s Gordon Bell Prize in High Performance Computing have been announced. They include two papers on projects run on China’s Read more…

By John Russell

  • arrow
  • Click Here for More Headlines
  • arrow
Share This