Intel Unveils Plans for HPC Coprocessor

By Michael Feldman

June 1, 2010

Chipmaker Intel is reviving the Larrabee technology for the HPC market, with plans to bring a manycore coprocessor to market in the next few years. During the ISC’10 opening keynote, Kirk Skaugen, vice president of Intel’s Architecture Group and general manager of the Data Center Group, announced the chipmaker is developing what they’re calling a “Many Integrated Core” (MIC) architecture, which will be the basis of a new line of processors aimed squarely at high performance technical computing applications.

The MIC architecture, like its Larrabee ancestor, will support the standard Intel Architecture (IA), the idea being to take advantage of the large software ecosystem for the x86. Coincident with the MIC chip development, Intel will be enhancing its parallel development tools and software libraries to support the new manycore coprocessor and the heterogeneous computing model.
 
Intel’s goal is for system vendors to construct Xeon-MIC servers (or workstations), similar to that of the current crop of x86-GPGPU hybrid systems. But in the case of Xeon-MIC, it’s not really a hybrid. Since both chips are based on standard x86 instructions, it’s more like a true processor-coprocessor model. And that’s what Skaugen said would differentiate the MIC accelerator from the GPGPU model of acceleration. In the later case, new programming environments like CUDA or OpenCL need to be employed to engage the GPU component.

Although the Larrabee architecture will be used as the base technology for the new coprocessor, according to Skaugen, it will also incorporate elements of Intel’s two previous experimental terascale processors: the 80-core “Polaris” chip first demonstrated in March 2007 and the 48-core “Single-chip Cloud Computer” (SCC) that introduced in December 2009. The general design of MIC will entail dozens of simple IA cores with big SIMD vector units, all linked together by an onchip interprocessor communications fabric.
MIC Coprocessor

The first product, codenamed “Knights Corner,” will be built on Intel’s 22nm process node and contain more than 50 IA cores. Intel is not specifying when that product will roll out, but Skaugen did say they are on schedule to hit the 22nm process node in 2011, so, at best, we’re at least a year away from any commercial release.

A 32-core development version of the MIC coprocessor, codenamed “Knights Ferry,” is now shipping to selected customers. A team at CERN has already migrated one of its parallel C++ codes to the coprocessor development platform in “just a few days.” Intel is promising more Knights Ferry hardware will be made available to qualified users throughout 2010.

The specs on the development platform are fairly impressive. The 32-core coprocessor runs a 1.2 GHz and supports 4 threads per core for a total of 128 threads per chip. The processor also has a large (8 MB) of shared coherent cache, and supports 1 to 2 GB of (graphics) GDDR5 memory. Although not mentioned in the announcement, it is almost certain the development platform, which is basically a Larrabee graphics system, does not support ECC memory. Since ECC is a must-have for many HPC applications (and since NVIDIA’s Fermi GPU accelerator products have already incorporated ECC), I would assume this capability will be available in the first commercial MIC products.

The development platform has the MIC coprocessor hooked up the Xeon CPU via a PCIe link, but Intel is not disclosing the coprocessor setup for the first real products. It’s not too big a stretch to think Intel will want use a standard Xeon socket for the MIC so that it can take advantage of the native QPI interconnect to link the processor and coprocessor.

At ISC, Skaugen showed a performance run on a Knights Ferry platform with LU factorization, which is used to implement Linpack. Running this code, the development chip hit 517 gigaflops, a mark Skaugen said was unmatched by any other platform. Skaugen later told me that this was single precision gigaflops, not double precision, which makes the “unmatched” claim somewhat questionable to me.

One big unknown with the MIC architecture is the vector instruction set. The original Larrabee design had its own vector instructions, so IA compatibility for that chip would only take you so far. The next-generation Sandy Bridge Xeons will incorporate the new AVX instructions, which are said to double the FLOPS/clock performance. It’s not clear if MIC will eventually support AVX as well, but Skaugen did say that they are “converging” their floating point instructions toward a common set that will be used in all IA platforms.

The chipmaker’s motivation to make MIC a commercial reality is compelling. According to Intel, about 25 percent of its server chips end up in HPC systems. If they can augment those sales with high value (although not overly expensive) coprocessors, that would be a nice new revenue source for the company. The trick, of course, is for Intel to sell enough of them so as to be able to recoup the hundreds of millions of dollars in chip and software development costs.

The other aspect to this is that most people now realize that standard x86 CPUs are not going to be able to scale efficiently to millions and billions of threads — the level needed for exascale HPC. This has made the idea of simpler manycore chips with big vector units very appealing.

Unfortunately for Intel, it’s a little late to the game, having watched the first wave of GPU acceleration from the sidelines. So once again, the company will have to hit a moving target. But if Intel can produce a true x86 coprocessor with terascale performance in a couple of years, and the software stack to back it up, it will be a very interesting solution for the HPC market.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Summit Achieves 445 Petaflops on New HPL-AI Benchmark

June 19, 2019

Summit -- the world's the top-ranking supercomputer -- has been used to test-drive a new AI-targeted Linpack benchmark, called HPL-AI. Traditionally, supercomputer performance is measured using the High-Performance Li Read more…

By Oliver Peckham

By the Numbers: For the HPC Industry, These Are the Good Old Days

June 18, 2019

For technology vendors in HPC and HPC-related markets driven by increased demand for AI, enterprise and exascale solutions, this is the best of times – with better times likely in the offing. HPC analyst firm Hyperion Research took the occasion of its semi-annual HPC market update breakfast today in Frankfurt... Read more…

By Doug Black

Top500 Purely Petaflops; US Maintains Performance Lead

June 17, 2019

With the kick-off of the International Supercomputing Conference (ISC) in Frankfurt this morning, the 53rd Top500 list made its debut, and this one's for petafloppers only. The entry point for the new list is 1.022 petaf Read more…

By Tiffany Trader

HPE Extreme Performance Solutions

HPE and Intel® Omni-Path Architecture: How to Power a Cloud

Learn how HPE and Intel® Omni-Path Architecture provide critical infrastructure for leading Nordic HPC provider’s HPCFLOW cloud service.

For decades, HPE has been at the forefront of high-performance computing, and we’ve powered some of the fastest and most robust supercomputers in the world. Read more…

IBM Accelerated Insights

Avoid AI Redo’s by Starting with the Right Infrastructure

Do you know if you have the right infrastructure for AI? Many organizations don’t have it. In a recent IDC survey, “77.1% of respondents say they ran into one or more limitations with their AI infrastructure on-premise and 90.3% ran into compute limitations in the cloud.” Read more…

Nvidia Embraces Arm, Declares Intent to Accelerate All CPU Architectures

June 17, 2019

As the Top500 list was being announced at ISC in Frankfurt today with an upgraded petascale Arm supercomputer in the top third of the list, Nvidia announced its intention to make Arm a full citizen in the processing arch Read more…

By Tiffany Trader

Summit Achieves 445 Petaflops on New HPL-AI Benchmark

June 19, 2019

Summit -- the world's the top-ranking supercomputer -- has been used to test-drive a new AI-targeted Linpack benchmark, called HPL-AI. Traditionally, superco Read more…

By Oliver Peckham

By the Numbers: For the HPC Industry, These Are the Good Old Days

June 18, 2019

For technology vendors in HPC and HPC-related markets driven by increased demand for AI, enterprise and exascale solutions, this is the best of times – with better times likely in the offing. HPC analyst firm Hyperion Research took the occasion of its semi-annual HPC market update breakfast today in Frankfurt... Read more…

By Doug Black

Top500 Purely Petaflops; US Maintains Performance Lead

June 17, 2019

With the kick-off of the International Supercomputing Conference (ISC) in Frankfurt this morning, the 53rd Top500 list made its debut, and this one's for petafl Read more…

By Tiffany Trader

Nvidia Embraces Arm, Declares Intent to Accelerate All CPU Architectures

June 17, 2019

As the Top500 list was being announced at ISC in Frankfurt today with an upgraded petascale Arm supercomputer in the top third of the list, Nvidia announced its Read more…

By Tiffany Trader

Jack Wells Joins OpenACC; Arm Support Coming

June 17, 2019

Perhaps the most significant ISC19 news for OpenACC wasn’t in its official press release yesterday which touted growing user traction and the notable addition Read more…

By John Russell

DDN Launches EXA5 for AI, Big Data, HPC Workloads

June 17, 2019

DDN, for two decades competing at the headwaters of high performance storage, this morning announced an enterprise-oriented end-to-end high performance storage Read more…

By Doug Black

Final Countdown to ISC19: What to See

June 13, 2019

If you're attending the International Supercomputing Conference, taking place in Frankfurt next week (June 16-20), you're either packing, in transit, or are alr Read more…

By Tiffany Trader

The US Global Weather Forecast System Just Got a Major Upgrade

June 13, 2019

The United States’ Global Forecast System (GFS) has received a major upgrade to its modeling capabilities. The new dynamical core that has been added to the G Read more…

By Oliver Peckham

High Performance (Potato) Chips

May 5, 2006

In this article, we focus on how Procter & Gamble is using high performance computing to create some common, everyday supermarket products. Tom Lange, a 27-year veteran of the company, tells us how P&G models products, processes and production systems for the betterment of consumer package goods. Read more…

By Michael Feldman

Cray, AMD to Extend DOE’s Exascale Frontier

May 7, 2019

Cray and AMD are coming back to Oak Ridge National Laboratory to partner on the world’s largest and most expensive supercomputer. The Department of Energy’s Read more…

By Tiffany Trader

Graphene Surprises Again, This Time for Quantum Computing

May 8, 2019

Graphene is fascinating stuff with promise for use in a seeming endless number of applications. This month researchers from the University of Vienna and Institu Read more…

By John Russell

Why Nvidia Bought Mellanox: ‘Future Datacenters Will Be…Like High Performance Computers’

March 14, 2019

“Future datacenters of all kinds will be built like high performance computers,” said Nvidia CEO Jensen Huang during a phone briefing on Monday after Nvidia revealed scooping up the high performance networking company Mellanox for $6.9 billion. Read more…

By Tiffany Trader

AMD Verifies Its Largest 7nm Chip Design in Ten Hours

June 5, 2019

AMD announced last week that its engineers had successfully executed the first physical verification of its largest 7nm chip design – in just ten hours. The AMD Radeon Instinct Vega20 – which boasts 13.2 billion transistors – was tested using a TSMC-certified Calibre nmDRC software platform from Mentor. Read more…

By Oliver Peckham

It’s Official: Aurora on Track to Be First US Exascale Computer in 2021

March 18, 2019

The U.S. Department of Energy along with Intel and Cray confirmed today that an Intel/Cray supercomputer, "Aurora," capable of sustained performance of one exaf Read more…

By Tiffany Trader

Deep Learning Competitors Stalk Nvidia

May 14, 2019

There is no shortage of processing architectures emerging to accelerate deep learning workloads, with two more options emerging this week to challenge GPU leader Nvidia. First, Intel researchers claimed a new deep learning record for image classification on the ResNet-50 convolutional neural network. Separately, Israeli AI chip startup Hailo.ai... Read more…

By George Leopold

The Case Against ‘The Case Against Quantum Computing’

January 9, 2019

It’s not easy to be a physicist. Richard Feynman (basically the Jimi Hendrix of physicists) once said: “The first principle is that you must not fool yourse Read more…

By Ben Criger

Leading Solution Providers

SC 18 Virtual Booth Video Tour

Advania @ SC18 AMD @ SC18
ASRock Rack @ SC18
DDN Storage @ SC18
HPE @ SC18
IBM @ SC18
Lenovo @ SC18 Mellanox Technologies @ SC18
NVIDIA @ SC18
One Stop Systems @ SC18
Oracle @ SC18 Panasas @ SC18
Supermicro @ SC18 SUSE @ SC18 TYAN @ SC18
Verne Global @ SC18

TSMC and Samsung Moving to 5nm; Whither Moore’s Law?

June 12, 2019

With reports that Taiwan Semiconductor Manufacturing Co. (TMSC) and Samsung are moving quickly to 5nm manufacturing, it’s a good time to again ponder whither goes the venerable Moore’s law. Shrinking feature size has of course been the primary hallmark of achieving Moore’s law... Read more…

By John Russell

Intel Launches Cascade Lake Xeons with Up to 56 Cores

April 2, 2019

At Intel's Data-Centric Innovation Day in San Francisco (April 2), the company unveiled its second-generation Xeon Scalable (Cascade Lake) family and debuted it Read more…

By Tiffany Trader

Cray – and the Cray Brand – to Be Positioned at Tip of HPE’s HPC Spear

May 22, 2019

More so than with most acquisitions of this kind, HPE’s purchase of Cray for $1.3 billion, announced last week, seems to have elements of that overused, often Read more…

By Doug Black and Tiffany Trader

Nvidia Embraces Arm, Declares Intent to Accelerate All CPU Architectures

June 17, 2019

As the Top500 list was being announced at ISC in Frankfurt today with an upgraded petascale Arm supercomputer in the top third of the list, Nvidia announced its Read more…

By Tiffany Trader

Arm Unveils Neoverse N1 Platform with up to 128-Cores

February 20, 2019

Following on its Neoverse roadmap announcement last October, Arm today revealed its next-gen Neoverse microarchitecture with compute and throughput-optimized si Read more…

By Tiffany Trader

Announcing four new HPC capabilities in Google Cloud Platform

April 15, 2019

When you’re running compute-bound or memory-bound applications for high performance computing or large, data-dependent machine learning training workloads on Read more…

By Wyatt Gorman, HPC Specialist, Google Cloud; Brad Calder, VP of Engineering, Google Cloud; Bart Sano, VP of Platforms, Google Cloud

In Wake of Nvidia-Mellanox: Xilinx to Acquire Solarflare

April 25, 2019

With echoes of Nvidia’s recent acquisition of Mellanox, FPGA maker Xilinx has announced a definitive agreement to acquire Solarflare Communications, provider Read more…

By Doug Black

Nvidia Claims 6000x Speed-Up for Stock Trading Backtest Benchmark

May 13, 2019

A stock trading backtesting algorithm used by hedge funds to simulate trading variants has received a massive, GPU-based performance boost, according to Nvidia, Read more…

By Doug Black

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This