Cray Sets Sights On Cascade Supercomputer, Exascale Milestone

By Michael Feldman

June 10, 2010

Cray’s recent unveiling of its XE6 supercomputer, previously codenamed “Baker,” marks the beginning of a larger strategy that lays the foundation for the company’s future heterogeneous supercomputing products. At last week’s International Supercomputing Conference (ISC) in Hamburg, HPCwire sat down with Cray CTO Steve Scott to talk about life after Baker, where he revealed the company’s plans for its upcoming “Cascade” supercomputer and how the exascale landscape is shaping up.

Cascade will be Cray’s first capability supercomputer based on Intel x86 processors. Starting with the XT3 machine in 2004, all of the company’s non-proprietary top-end supers have been built with AMD Opteron CPUs. According to Scott, the first Cascade system delivered will sport Xeon-powered server blades, but the intention is to eventually support AMD Opteron processors on this architecture as well. Like most HPC vendors, Cray appears committed to following this dual-x86 product path.

The development of Cascade is being subsidized by DARPA’s HPCS (High Productivity Computing Systems) program. The third and final phase of the contract with Cray set aside $250 million to help the company complete development of the hardware and the supporting system software. (IBM was allocated $244 million for its corresponding PERCS system.) According to Scott, Cascade is currently on track to be delivered sometime in the second half of 2012. Specific product timetables for the Opteron version are still to be determined, and will ultimately depend upon customer demand as well as AMD’s processor schedule.

A new system interconnect, codenamed “Aries,” is being developed for the Cascade-class machines. To support a dual Intel-AMD strategy on this architecture, Cray is going to begin using PCI-Express as the processor interface to the interconnect ASIC. The current SeaStar, and now Gemini interconnect, are tied to Opteron’s native HyperTransport link. While it might seem natural to think that Cray would hook into Intel’s QPI for network connectivity on a Xeon-based machine, opting for PCI-Express meant Cray could support the same network across both processor architectures — and any future ones as well. According to Scott, they’re looking to tape out the Aries chip by the end of 2010.

For Cray, Cascade represents a fairly significant break with the XT/XE line of supercomputers, which have maintained a smooth hardware upgrade path for the past six years. Although the software stack and application codes can be carried forward onto Cascade, the reworked hardware architecture means users will no longer be able to extend their XT or XE infrastructure with this new technology.

Cascade will also have an accelerator blade to go along with the x86-based blades. Originally, this component was going to be developed under the HPCS contract, but for various reasons the work got canceled, which culminated in a contract renegotiation to reduce the scope of the contract late in 2009. According to Scott, Cray was working with Intel on the technology, but as of now they are undecided about which accelerator will end up in the Cascade product line. The most likely candidates include NVIDIA’s Tesla GPUs, AMD’s FireStream GPUs, and Intel’s “Many Integrated Core” (MIC) coprocessor, which was announced at ISC last week. At present, Cray is talking with all three vendors about the roadmaps for their respective accelerator solutions.

The XE6 supercomputer, slated for delivery in Q3 2010, will also get an accelerator blade, said Scott, who confirmed that it will be based on the latest NVIDIA Tesla-20 (Fermi) GPUs, which are just coming into production now. As of now, the release date for the XE6 accelerator blade option is still under wraps, but it’s reasonable to think that it will be announced before the end of the year. Cray also partnered with NVIDIA to put in a bid for DARPA’s Ubiquitous High Performance Computing (UHPC) program for “ExtremeScale architectures,” which is aimed at innovative terascale to petascale supercomputing systems.

Accelerators appear to be a big part of Cray’s strategy going forward. “In the long run we’re going to have to change the trajectory,” said Scott. “Plain old multicore x86 won’t do it. Most of the heavy lifting is going to have to be done by processors that are specifically designed, first order, for power efficiency, not for running single threads fast. So we’re going to need heterogeneity in some form.”

Right now, the software support for accelerators is in its infancy. So Scott is not expecting the HPC community to shift en masse to this new computing model overnight. Even after the XE6 accelerator blades hit the streets, Scott expects the majority of systems sold will be straight Opteron-based machines. “Over time that’s going to shift, said Scott. “I would predict five years from now, the bulk of serious HPC is going to be done with some kind of accelerated heterogeneous architecture.”

Further down the road, heterogeneous processing will form the foundation of Cray exascale architectures. In 2018, the year Scott predicts Cray will have a machine that can deliver a sustained application exaflop, heterogeneous computing will likely be much more highly integrated. According to Scott, CPU-GPU hybrid processors (or the equivalent), along the lines of AMD’s Fusion architecture, will be generally available and powerful enough to form the basis of HPC machines. He believes both NVIDIA and Intel will be offering their own versions of integrated CPU-accelerator chips. “That’s clearly the direction to take,” he asserted. “The more tightly you can couple those two different types of processors together, the better off we’ll be.”

He also foresees optical interconnects integrated directly into the chip package, with possibly some electrical interconnect on the board, as well as networks that are very low diameter so that you don’t have to expend a lot of power retransmitting data. In addition, Scott envisions another level of memory between the off-chip DIMMs and on-chip cache, implemented perhaps with 3D stacking technology — the idea being to substantially increase the bandwidth to the processors, while reducing power. “It’s not like it’s going to be easy,” noted Scott. “But I think there’s definitely a path.”

As far as what lies beyond exascale, Cray has nothing on the drawing board yet, but neither does anyone else. Assuming, historical trends hold, the first zettaflop systems will show up around 2028. But they are likely to be based on technologies that have yet to make it out of the research lab.

“I do think that exascale is going to be the last one that we’re going to get to with traditional silicon technology,” said Scott. “I don’t know what’s going to be next, but if you look back 100 years, we’ve gone from mechanical tabulating machines, to electro-mechanical relays, to vacuum tubes, to discrete transistors, to integrated circuits. If you look at that history you see a straight line of performance growth through multiple technology transitions. That doesn’t prove a damn thing. But it gives me some sort of hope that we’ll come up with something post-silicon ICs to take us forward.”

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