For AMD, All Paths Lead to CPU-GPU Fusion

By Michael Feldman

June 14, 2010

One of the more interesting aspects to the GPU computing craze is the diversity of solutions that are emerging from the chip vendors. NVIDIA is currently out in front of the pack with its CUDA-architected Tesla GPUs, purpose-built for HPC. Intel, with the reintroduction of its Larrabee technology (now known as the “Many Integrated Core” (MIC) architecture), is pursuing the un-GPU model of data parallel computing. That leaves AMD, with its dual path of FireStream GPUs for “stream computing” and CPU-GPU Fusion technology for everything else.

But its the Fusion technology that sets AMD apart from its chip-making rivals. Because of the 2006 acquisition of ATI, the company stands alone as the processor vendor with mature technologies for both CPUs and GPUs. This makes the integration of the two architectures onto the same piece of silicon a natural fit for the company.

AMD, of course, was looking to exploit that advantage from the start. They originally planned to push out the first Fusion parts in 2009, but the complexity of folding ATI into the company and the subsequent recession slowed down the effort considerably, delaying the roadmap for two years. AMD is only now gearing up to launch its first Fusion processors, also known as Accelerated Processing Units (APUs), sometime in 2011.

These first CPU-GPU products are aimed at the desktop and laptop market to improve the visual computing experience for PC users (mostly via Microsoft’s DirectX framework). But technical computing users are starting to look at the Fusion architecture as a way to bring GPU-style parallel processing much closer to the CPU.

To date, all serious GPU computing is being done on relatively high-end discrete graphics processors that are hooked up to a host CPU system via a PCI-express (PCIe) link. This is the case for both NVIDIA’s and AMD’s GPU computing products — Tesla and FireStream, respectively. Although some HPC applications have recorded performance gains on the order on of 10X to 1,000X, the overhead of shuttling data back and forth across the PCIe link and the clunky software used to support this model suggests that off-chip acceleration is just the first chapter of the GPU computing story.

Last week, Northeastern University, in Boston, held an academic research day for GPU computing to get the word out about how it’s being used for technical computing applications in the research community. The event was organized in conjunction with AMD’s External Research Office as part of an outreach to the other academicians, and to put forth the company’s vision of heterogeneous computing as well as its upcoming CPU-GPU products. HPCwire spoke with Dave Kaeli, the director of the Northeastern University’s Computer Architecture Research Laboratory, who gave the event’s opening talk on “Exploiting Heterogeneous CPUs/GPUs,” in which he talked about some of his experiences with the technology.

Much of Kaeli’s work is focused on using GPUs for biomedical imaging applications — work that is being funded by the NSF and by AMD itself. There are two classes of problems he’s working on. The first is for image-guided biopsies, where real-time visual processing and high data bandwidth are the principal requirements. The other is for the digital reconstruction of a single image, which can take on the order of tens of hours — certainly not real-time, but time-critical for certain medical scenarios.

In the latter case, Kaeli is using an ATI Radeon 5870 GPU, which boasts a raw performance of 2.72 teraflops (single precision floating point). Compared to a CPU-only implementation, an order of magnitude speed-up is possible for this type of image reconstruction. Detection of breast cancer and coronary blockage are two of the main applications here, and in this case, the patient goes home and then returns later for a second consultation. The reduced turnaround time has the potential to produce better outcomes as well as reduce costs.

Some of Kaeli’s effort has gone toward developing GPU-based biomedical imaging libraries in OpenCL, an open language standard for parallel processing across GPUs and CPUs. He says the work has reached the point where they’re now engaged with a major medical equipment manufacturer to help design the company’s next-generation ultrasound devices. The plan is to incorporate GPUs to support very high-resolution 3D ultrasound in a portable, low-power device.

Currently, the medical manufacturer is using a combination of FPGAs and DSPs for this class of device. Not only does that design stretch the power envelop for a mobile platform, but the lack of a commodity-driven solution makes the upgrade path problematic. Being able to write the application in a language like OpenCL, which is portable across multiple silicon generations (not to mention chip vendors), is a much more attractive proposition for manufacturers.

Initially the ultrasound appliance will be equipped with a discrete GPU, with the idea of migrating to a CPU-GPU processor later on. “The whole idea of moving from a high performance graphics card to an embedded GPU to a hybrid, heterogeneous Fusion chip is a very attractive in that domain,” explains Kaeli. “It’s really why we’re so engaged with AMD at this point. We recognize that they are providing leadership in this particular area right now.”

Kaeli says heterogeneous processing presents a lot of attractive features, both in terms of ease of coding and from a power-performance standpoint. On the power usage side, the benefits of CPU-GPU integration extends across both traditional and technical computing applications. For scientific codes though, the current process technology (45 nm) limits the size of the GPU that can fit on the same die as the CPU, and thus the ultimate performance of the chip. But as Moore’s Law works its magic, a very respectable-sized GPU will be able to be share the die with a CPU.

From a programmer’s point of view, having the CPU and GPU sharing the same RAM is a big improvement from the split memory model with discrete devices. And the latency associated with passing data back and forth between two separate devices is much better (i.e., lower) when the CPU and GPU are on the same die. This is especially true for real-time embedded applications, where latency is particularly critical.

Kaeli is also involved with a surgical simulator application for training doctors. In this case, finite element analysis (FEA) is used to simulate blood flow, cutting, skin tension, and so on. “We can’t do all of that on a GPU,” says Kaeli. “A lot of that has to be done on the CPU.”

Besides biomedical image research and other medical applications, Kaeli is involved with GPU compiler work, developing techniques for efficient mapping of algorithms onto GPUs, and looking at virtualization technology that leverages multiple GPUs. His group is also researching cross compilers that can take CUDA applications for NVIDIA GPUs and convert the source code to OpenCL. “We actually have working examples of that already,” he says.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “pre-exascale” award), parsed out additional information ab Read more…

By Tiffany Trader

Tsinghua Crowned Eight-Time Student Cluster Champions at ISC

June 22, 2017

Always a hard-fought competition, the Student Cluster Competition awards were announced Wednesday, June 21, at the ISC High Performance Conference 2017. Amid whoops and hollers from the crowd, Thomas Sterling presented t Read more…

By Kim McMahon

GPUs, Power9, Figure Prominently in IBM’s Bet on Weather Forecasting

June 22, 2017

IBM jumped into the weather forecasting business roughly a year and a half ago by purchasing The Weather Company. This week at ISC 2017, Big Blue rolled out plans to push deeper into climate science and develop more gran Read more…

By John Russell

Intersect 360 at ISC: HPC Industry at $44B by 2021

June 22, 2017

The care, feeding and sustained growth of the HPC industry increasingly is in the hands of the commercial market sector – in particular, it’s the hyperscale companies and their embrace of AI and deep learning – tha Read more…

By Doug Black

HPE Extreme Performance Solutions

Creating a Roadmap for HPC Innovation at ISC 2017

In an era where technological advancements are driving innovation to every sector, and powering major economic and scientific breakthroughs, high performance computing (HPC) is crucial to tackle the challenges of today and tomorrow. Read more…

At ISC – Goh on Go: Humans Can’t Scale, the Data-Centric Learning Machine Can

June 22, 2017

I've seen the future this week at ISC, it’s on display in prototype or Powerpoint form, and it’s going to dumbfound you. The future is an AI neural network designed to emulate and compete with the human brain. In thi Read more…

By Doug Black

Cray Brings AI and HPC Together on Flagship Supers

June 20, 2017

Cray took one more step toward the convergence of big data and high performance computing (HPC) today when it announced that it’s adding a full suite of big data and artificial intelligence software to its top-of-the-l Read more…

By Alex Woodie

AMD Charges Back into the Datacenter and HPC Workflows with EPYC Processor

June 20, 2017

AMD is charging back into the enterprise datacenter and select HPC workflows with its new EPYC 7000 processor line, code-named Naples, announced today at a “global” launch event in Austin TX. In many ways it was a fu Read more…

By John Russell

Hyperion: Deep Learning, AI Helping Drive Healthy HPC Industry Growth

June 20, 2017

To be at the ISC conference in Frankfurt this week is to experience deep immersion in deep learning. Users want to learn about it, vendors want to talk about it, analysts and journalists want to report on it. Deep learni Read more…

By Doug Black

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Tsinghua Crowned Eight-Time Student Cluster Champions at ISC

June 22, 2017

Always a hard-fought competition, the Student Cluster Competition awards were announced Wednesday, June 21, at the ISC High Performance Conference 2017. Amid wh Read more…

By Kim McMahon

GPUs, Power9, Figure Prominently in IBM’s Bet on Weather Forecasting

June 22, 2017

IBM jumped into the weather forecasting business roughly a year and a half ago by purchasing The Weather Company. This week at ISC 2017, Big Blue rolled out pla Read more…

By John Russell

Intersect 360 at ISC: HPC Industry at $44B by 2021

June 22, 2017

The care, feeding and sustained growth of the HPC industry increasingly is in the hands of the commercial market sector – in particular, it’s the hyperscale Read more…

By Doug Black

At ISC – Goh on Go: Humans Can’t Scale, the Data-Centric Learning Machine Can

June 22, 2017

I've seen the future this week at ISC, it’s on display in prototype or Powerpoint form, and it’s going to dumbfound you. The future is an AI neural network Read more…

By Doug Black

Cray Brings AI and HPC Together on Flagship Supers

June 20, 2017

Cray took one more step toward the convergence of big data and high performance computing (HPC) today when it announced that it’s adding a full suite of big d Read more…

By Alex Woodie

AMD Charges Back into the Datacenter and HPC Workflows with EPYC Processor

June 20, 2017

AMD is charging back into the enterprise datacenter and select HPC workflows with its new EPYC 7000 processor line, code-named Naples, announced today at a “g Read more…

By John Russell

Hyperion: Deep Learning, AI Helping Drive Healthy HPC Industry Growth

June 20, 2017

To be at the ISC conference in Frankfurt this week is to experience deep immersion in deep learning. Users want to learn about it, vendors want to talk about it Read more…

By Doug Black

Quantum Bits: D-Wave and VW; Google Quantum Lab; IBM Expands Access

March 21, 2017

For a technology that’s usually characterized as far off and in a distant galaxy, quantum computing has been steadily picking up steam. Just how close real-wo Read more…

By John Russell

Trump Budget Targets NIH, DOE, and EPA; No Mention of NSF

March 16, 2017

President Trump’s proposed U.S. fiscal 2018 budget issued today sharply cuts science spending while bolstering military spending as he promised during the cam Read more…

By John Russell

HPC Compiler Company PathScale Seeks Life Raft

March 23, 2017

HPCwire has learned that HPC compiler company PathScale has fallen on difficult times and is asking the community for help or actively seeking a buyer for its a Read more…

By Tiffany Trader

Google Pulls Back the Covers on Its First Machine Learning Chip

April 6, 2017

This week Google released a report detailing the design and performance characteristics of the Tensor Processing Unit (TPU), its custom ASIC for the inference Read more…

By Tiffany Trader

CPU-based Visualization Positions for Exascale Supercomputing

March 16, 2017

In this contributed perspective piece, Intel’s Jim Jeffers makes the case that CPU-based visualization is now widely adopted and as such is no longer a contrarian view, but is rather an exascale requirement. Read more…

By Jim Jeffers, Principal Engineer and Engineering Leader, Intel

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Nvidia’s Mammoth Volta GPU Aims High for AI, HPC

May 10, 2017

At Nvidia's GPU Technology Conference (GTC17) in San Jose, Calif., this morning, CEO Jensen Huang announced the company's much-anticipated Volta architecture a Read more…

By Tiffany Trader

Facebook Open Sources Caffe2; Nvidia, Intel Rush to Optimize

April 18, 2017

From its F8 developer conference in San Jose, Calif., today, Facebook announced Caffe2, a new open-source, cross-platform framework for deep learning. Caffe2 is the successor to Caffe, the deep learning framework developed by Berkeley AI Research and community contributors. Read more…

By Tiffany Trader

Leading Solution Providers

MIT Mathematician Spins Up 220,000-Core Google Compute Cluster

April 21, 2017

On Thursday, Google announced that MIT math professor and computational number theorist Andrew V. Sutherland had set a record for the largest Google Compute Engine (GCE) job. Sutherland ran the massive mathematics workload on 220,000 GCE cores using preemptible virtual machine instances. Read more…

By Tiffany Trader

Google Debuts TPU v2 and will Add to Google Cloud

May 25, 2017

Not long after stirring attention in the deep learning/AI community by revealing the details of its Tensor Processing Unit (TPU), Google last week announced the Read more…

By John Russell

US Supercomputing Leaders Tackle the China Question

March 15, 2017

Joint DOE-NSA report responds to the increased global pressures impacting the competitiveness of U.S. supercomputing. Read more…

By Tiffany Trader

Russian Researchers Claim First Quantum-Safe Blockchain

May 25, 2017

The Russian Quantum Center today announced it has overcome the threat of quantum cryptography by creating the first quantum-safe blockchain, securing cryptocurrencies like Bitcoin, along with classified government communications and other sensitive digital transfers. Read more…

By Doug Black

Groq This: New AI Chips to Give GPUs a Run for Deep Learning Money

April 24, 2017

CPUs and GPUs, move over. Thanks to recent revelations surrounding Google’s new Tensor Processing Unit (TPU), the computing world appears to be on the cusp of Read more…

By Alex Woodie

DOE Supercomputer Achieves Record 45-Qubit Quantum Simulation

April 13, 2017

In order to simulate larger and larger quantum systems and usher in an age of “quantum supremacy,” researchers are stretching the limits of today’s most advanced supercomputers. Read more…

By Tiffany Trader

Messina Update: The US Path to Exascale in 16 Slides

April 26, 2017

Paul Messina, director of the U.S. Exascale Computing Project, provided a wide-ranging review of ECP’s evolving plans last week at the HPC User Forum. Read more…

By John Russell

Knights Landing Processor with Omni-Path Makes Cloud Debut

April 18, 2017

HPC cloud specialist Rescale is partnering with Intel and HPC resource provider R Systems to offer first-ever cloud access to Xeon Phi "Knights Landing" processors. The infrastructure is based on the 68-core Intel Knights Landing processor with integrated Omni-Path fabric (the 7250F Xeon Phi). Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This