For AMD, All Paths Lead to CPU-GPU Fusion

By Michael Feldman

June 14, 2010

One of the more interesting aspects to the GPU computing craze is the diversity of solutions that are emerging from the chip vendors. NVIDIA is currently out in front of the pack with its CUDA-architected Tesla GPUs, purpose-built for HPC. Intel, with the reintroduction of its Larrabee technology (now known as the “Many Integrated Core” (MIC) architecture), is pursuing the un-GPU model of data parallel computing. That leaves AMD, with its dual path of FireStream GPUs for “stream computing” and CPU-GPU Fusion technology for everything else.

But its the Fusion technology that sets AMD apart from its chip-making rivals. Because of the 2006 acquisition of ATI, the company stands alone as the processor vendor with mature technologies for both CPUs and GPUs. This makes the integration of the two architectures onto the same piece of silicon a natural fit for the company.

AMD, of course, was looking to exploit that advantage from the start. They originally planned to push out the first Fusion parts in 2009, but the complexity of folding ATI into the company and the subsequent recession slowed down the effort considerably, delaying the roadmap for two years. AMD is only now gearing up to launch its first Fusion processors, also known as Accelerated Processing Units (APUs), sometime in 2011.

These first CPU-GPU products are aimed at the desktop and laptop market to improve the visual computing experience for PC users (mostly via Microsoft’s DirectX framework). But technical computing users are starting to look at the Fusion architecture as a way to bring GPU-style parallel processing much closer to the CPU.

To date, all serious GPU computing is being done on relatively high-end discrete graphics processors that are hooked up to a host CPU system via a PCI-express (PCIe) link. This is the case for both NVIDIA’s and AMD’s GPU computing products — Tesla and FireStream, respectively. Although some HPC applications have recorded performance gains on the order on of 10X to 1,000X, the overhead of shuttling data back and forth across the PCIe link and the clunky software used to support this model suggests that off-chip acceleration is just the first chapter of the GPU computing story.

Last week, Northeastern University, in Boston, held an academic research day for GPU computing to get the word out about how it’s being used for technical computing applications in the research community. The event was organized in conjunction with AMD’s External Research Office as part of an outreach to the other academicians, and to put forth the company’s vision of heterogeneous computing as well as its upcoming CPU-GPU products. HPCwire spoke with Dave Kaeli, the director of the Northeastern University’s Computer Architecture Research Laboratory, who gave the event’s opening talk on “Exploiting Heterogeneous CPUs/GPUs,” in which he talked about some of his experiences with the technology.

Much of Kaeli’s work is focused on using GPUs for biomedical imaging applications — work that is being funded by the NSF and by AMD itself. There are two classes of problems he’s working on. The first is for image-guided biopsies, where real-time visual processing and high data bandwidth are the principal requirements. The other is for the digital reconstruction of a single image, which can take on the order of tens of hours — certainly not real-time, but time-critical for certain medical scenarios.

In the latter case, Kaeli is using an ATI Radeon 5870 GPU, which boasts a raw performance of 2.72 teraflops (single precision floating point). Compared to a CPU-only implementation, an order of magnitude speed-up is possible for this type of image reconstruction. Detection of breast cancer and coronary blockage are two of the main applications here, and in this case, the patient goes home and then returns later for a second consultation. The reduced turnaround time has the potential to produce better outcomes as well as reduce costs.

Some of Kaeli’s effort has gone toward developing GPU-based biomedical imaging libraries in OpenCL, an open language standard for parallel processing across GPUs and CPUs. He says the work has reached the point where they’re now engaged with a major medical equipment manufacturer to help design the company’s next-generation ultrasound devices. The plan is to incorporate GPUs to support very high-resolution 3D ultrasound in a portable, low-power device.

Currently, the medical manufacturer is using a combination of FPGAs and DSPs for this class of device. Not only does that design stretch the power envelop for a mobile platform, but the lack of a commodity-driven solution makes the upgrade path problematic. Being able to write the application in a language like OpenCL, which is portable across multiple silicon generations (not to mention chip vendors), is a much more attractive proposition for manufacturers.

Initially the ultrasound appliance will be equipped with a discrete GPU, with the idea of migrating to a CPU-GPU processor later on. “The whole idea of moving from a high performance graphics card to an embedded GPU to a hybrid, heterogeneous Fusion chip is a very attractive in that domain,” explains Kaeli. “It’s really why we’re so engaged with AMD at this point. We recognize that they are providing leadership in this particular area right now.”

Kaeli says heterogeneous processing presents a lot of attractive features, both in terms of ease of coding and from a power-performance standpoint. On the power usage side, the benefits of CPU-GPU integration extends across both traditional and technical computing applications. For scientific codes though, the current process technology (45 nm) limits the size of the GPU that can fit on the same die as the CPU, and thus the ultimate performance of the chip. But as Moore’s Law works its magic, a very respectable-sized GPU will be able to be share the die with a CPU.

From a programmer’s point of view, having the CPU and GPU sharing the same RAM is a big improvement from the split memory model with discrete devices. And the latency associated with passing data back and forth between two separate devices is much better (i.e., lower) when the CPU and GPU are on the same die. This is especially true for real-time embedded applications, where latency is particularly critical.

Kaeli is also involved with a surgical simulator application for training doctors. In this case, finite element analysis (FEA) is used to simulate blood flow, cutting, skin tension, and so on. “We can’t do all of that on a GPU,” says Kaeli. “A lot of that has to be done on the CPU.”

Besides biomedical image research and other medical applications, Kaeli is involved with GPU compiler work, developing techniques for efficient mapping of algorithms onto GPUs, and looking at virtualization technology that leverages multiple GPUs. His group is also researching cross compilers that can take CUDA applications for NVIDIA GPUs and convert the source code to OpenCL. “We actually have working examples of that already,” he says.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

TACC Helps ROSIE Bioscience Gateway Expand its Impact

April 26, 2017

Biomolecule structure prediction has long been challenging not least because the relevant software and workflows often require high-end HPC systems that many bioscience researchers lack easy access to. Read more…

By John Russell

Messina Update: The US Path to Exascale in 16 Slides

April 26, 2017

Paul Messina, director of the U.S. Exascale Computing Project, provided a wide-ranging review of ECP’s evolving plans last week at the HPC User Forum. Read more…

By John Russell

IBM, Nvidia, Stone Ridge Claim Gas & Oil Simulation Record

April 25, 2017

IBM, Nvidia, and Stone Ridge Technology today reported setting the performance record for a “billion cell” oil and gas reservoir simulation. Read more…

By John Russell

ASC17 Makes Splash at Wuxi Supercomputing Center

April 24, 2017

A record-breaking twenty student teams plus scores of company representatives, media professionals, staff and student volunteers transformed a formerly empty hall inside the Wuxi Supercomputing Center into a bustling hub of HPC activity, kicking off day one of 2017 Asia Student Supercomputer Challenge (ASC17). Read more…

By Tiffany Trader

HPE Extreme Performance Solutions

Remote Visualization Optimizing Life Sciences Operations and Care Delivery

As patients continually demand a better quality of care and increasingly complex workloads challenge healthcare organizations to innovate, investing in the right technologies is key to ensuring growth and success. Read more…

Groq This: New AI Chips to Give GPUs a Run for Deep Learning Money

April 24, 2017

CPUs and GPUs, move over. Thanks to recent revelations surrounding Google’s new Tensor Processing Unit (TPU), the computing world appears to be on the cusp of a new generation of chips designed specifically for deep learning workloads. Read more…

By Alex Woodie

Musk’s Latest Startup Eyes Brain-Computer Links

April 21, 2017

Elon Musk, the auto and space entrepreneur and severe critic of artificial intelligence, is forming a new venture that reportedly will seek to develop an interface between the human brain and computers. Read more…

By George Leopold

MIT Mathematician Spins Up 220,000-Core Google Compute Cluster

April 21, 2017

On Thursday, Google announced that MIT math professor and computational number theorist Andrew V. Sutherland had set a record for the largest Google Compute Engine (GCE) job. Sutherland ran the massive mathematics workload on 220,000 GCE cores using preemptible virtual machine instances. Read more…

By Tiffany Trader

NERSC Cori Shows the World How Many-Cores for the Masses Works

April 21, 2017

As its mission, the high performance computing center for the U.S. Department of Energy Office of Science, NERSC (the National Energy Research Supercomputer Center), supports a broad spectrum of forefront scientific research across diverse areas that includes climate, material science, chemistry, fusion energy, high-energy physics and many others. Read more…

By Rob Farber

Messina Update: The US Path to Exascale in 16 Slides

April 26, 2017

Paul Messina, director of the U.S. Exascale Computing Project, provided a wide-ranging review of ECP’s evolving plans last week at the HPC User Forum. Read more…

By John Russell

ASC17 Makes Splash at Wuxi Supercomputing Center

April 24, 2017

A record-breaking twenty student teams plus scores of company representatives, media professionals, staff and student volunteers transformed a formerly empty hall inside the Wuxi Supercomputing Center into a bustling hub of HPC activity, kicking off day one of 2017 Asia Student Supercomputer Challenge (ASC17). Read more…

By Tiffany Trader

Groq This: New AI Chips to Give GPUs a Run for Deep Learning Money

April 24, 2017

CPUs and GPUs, move over. Thanks to recent revelations surrounding Google’s new Tensor Processing Unit (TPU), the computing world appears to be on the cusp of a new generation of chips designed specifically for deep learning workloads. Read more…

By Alex Woodie

NERSC Cori Shows the World How Many-Cores for the Masses Works

April 21, 2017

As its mission, the high performance computing center for the U.S. Department of Energy Office of Science, NERSC (the National Energy Research Supercomputer Center), supports a broad spectrum of forefront scientific research across diverse areas that includes climate, material science, chemistry, fusion energy, high-energy physics and many others. Read more…

By Rob Farber

Hyperion (IDC) Paints a Bullish Picture of HPC Future

April 20, 2017

Hyperion Research – formerly IDC’s HPC group – yesterday painted a fascinating and complicated portrait of the HPC community’s health and prospects at the HPC User Forum held in Albuquerque, NM. HPC sales are up and growing ($22 billion, all HPC segments, 2016). Read more…

By John Russell

Knights Landing Processor with Omni-Path Makes Cloud Debut

April 18, 2017

HPC cloud specialist Rescale is partnering with Intel and HPC resource provider R Systems to offer first-ever cloud access to Xeon Phi "Knights Landing" processors. The infrastructure is based on the 68-core Intel Knights Landing processor with integrated Omni-Path fabric (the 7250F Xeon Phi). Read more…

By Tiffany Trader

CERN openlab Explores New CPU/FPGA Processing Solutions

April 14, 2017

Through a CERN openlab project known as the ‘High-Throughput Computing Collaboration,’ researchers are investigating the use of various Intel technologies in data filtering and data acquisition systems. Read more…

By Linda Barney

DOE Supercomputer Achieves Record 45-Qubit Quantum Simulation

April 13, 2017

In order to simulate larger and larger quantum systems and usher in an age of “quantum supremacy,” researchers are stretching the limits of today’s most advanced supercomputers. Read more…

By Tiffany Trader

Google Pulls Back the Covers on Its First Machine Learning Chip

April 6, 2017

This week Google released a report detailing the design and performance characteristics of the Tensor Processing Unit (TPU), its custom ASIC for the inference phase of neural networks (NN). Read more…

By Tiffany Trader

Quantum Bits: D-Wave and VW; Google Quantum Lab; IBM Expands Access

March 21, 2017

For a technology that’s usually characterized as far off and in a distant galaxy, quantum computing has been steadily picking up steam. Read more…

By John Russell

Trump Budget Targets NIH, DOE, and EPA; No Mention of NSF

March 16, 2017

President Trump’s proposed U.S. fiscal 2018 budget issued today sharply cuts science spending while bolstering military spending as he promised during the campaign. Read more…

By John Russell

HPC Compiler Company PathScale Seeks Life Raft

March 23, 2017

HPCwire has learned that HPC compiler company PathScale has fallen on difficult times and is asking the community for help or actively seeking a buyer for its assets. Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

CPU-based Visualization Positions for Exascale Supercomputing

March 16, 2017

In this contributed perspective piece, Intel’s Jim Jeffers makes the case that CPU-based visualization is now widely adopted and as such is no longer a contrarian view, but is rather an exascale requirement. Read more…

By Jim Jeffers, Principal Engineer and Engineering Leader, Intel

For IBM/OpenPOWER: Success in 2017 = (Volume) Sales

January 11, 2017

To a large degree IBM and the OpenPOWER Foundation have done what they said they would – assembling a substantial and growing ecosystem and bringing Power-based products to market, all in about three years. Read more…

By John Russell

TSUBAME3.0 Points to Future HPE Pascal-NVLink-OPA Server

February 17, 2017

Since our initial coverage of the TSUBAME3.0 supercomputer yesterday, more details have come to light on this innovative project. Of particular interest is a new board design for NVLink-equipped Pascal P100 GPUs that will create another entrant to the space currently occupied by Nvidia's DGX-1 system, IBM's "Minsky" platform and the Supermicro SuperServer (1028GQ-TXR). Read more…

By Tiffany Trader

Leading Solution Providers

Tokyo Tech’s TSUBAME3.0 Will Be First HPE-SGI Super

February 16, 2017

In a press event Friday afternoon local time in Japan, Tokyo Institute of Technology (Tokyo Tech) announced its plans for the TSUBAME3.0 supercomputer, which will be Japan’s “fastest AI supercomputer,” Read more…

By Tiffany Trader

Is Liquid Cooling Ready to Go Mainstream?

February 13, 2017

Lost in the frenzy of SC16 was a substantial rise in the number of vendors showing server oriented liquid cooling technologies. Three decades ago liquid cooling was pretty much the exclusive realm of the Cray-2 and IBM mainframe class products. That’s changing. We are now seeing an emergence of x86 class server products with exotic plumbing technology ranging from Direct-to-Chip to servers and storage completely immersed in a dielectric fluid. Read more…

By Steve Campbell

IBM Wants to be “Red Hat” of Deep Learning

January 26, 2017

IBM today announced the addition of TensorFlow and Chainer deep learning frameworks to its PowerAI suite of deep learning tools, which already includes popular offerings such as Caffe, Theano, and Torch. Read more…

By John Russell

Facebook Open Sources Caffe2; Nvidia, Intel Rush to Optimize

April 18, 2017

From its F8 developer conference in San Jose, Calif., today, Facebook announced Caffe2, a new open-source, cross-platform framework for deep learning. Caffe2 is the successor to Caffe, the deep learning framework developed by Berkeley AI Research and community contributors. Read more…

By Tiffany Trader

BioTeam’s Berman Charts 2017 HPC Trends in Life Sciences

January 4, 2017

Twenty years ago high performance computing was nearly absent from life sciences. Today it’s used throughout life sciences and biomedical research. Genomics and the data deluge from modern lab instruments are the main drivers, but so is the longer-term desire to perform predictive simulation in support of Precision Medicine (PM). There’s even a specialized life sciences supercomputer, ‘Anton’ from D.E. Shaw Research, and the Pittsburgh Supercomputing Center is standing up its second Anton 2 and actively soliciting project proposals. There’s a lot going on. Read more…

By John Russell

HPC Startup Advances Auto-Parallelization’s Promise

January 23, 2017

The shift from single core to multicore hardware has made finding parallelism in codes more important than ever, but that hasn’t made the task of parallel programming any easier. Read more…

By Tiffany Trader

HPC Technique Propels Deep Learning at Scale

February 21, 2017

Researchers from Baidu’s Silicon Valley AI Lab (SVAIL) have adapted a well-known HPC communication technique to boost the speed and scale of their neural network training and now they are sharing their implementation with the larger deep learning community. Read more…

By Tiffany Trader

IDG to Be Bought by Chinese Investors; IDC to Spin Out HPC Group

January 19, 2017

US-based publishing and investment firm International Data Group, Inc. (IDG) will be acquired by a pair of Chinese investors, China Oceanwide Holdings Group Co., Ltd. Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This