In my last column, I reviewed the architecture of the Intel Larrabee processor, comparing it to a quad-core Nehalem, and considering possible follow-on designs. Larrabee was initially designed as a discrete graphics engine that would also address highly-parallel applications while preserving x86 programmability. It was demonstrated with much fanfare at Justin Rattner’s SC09 opening keynote talk. However, within a month, Intel announced that Larrabee products would be deferred, though it seems the architecture was not entirely cancelled. In May, Intel announced the Many Integrated Core (MIC, pronounced “Mike”) architecture, with a development kit codenamed Knights Ferry. The Knights Ferry chip was described broadly by Kirk Skaugen at his ISC’10 keynote talk in Hamburg, Germany. Slide 33 from his presentation makes the Knights Ferry design look remarkably like the graphic in the 2008 SIGGRAPH article describing Larrabee. The Knights Corner, the first real product based on the MIC architecture, will use Intel’s 22nm process and include more than 50 x86 cores. Perhaps Intel will insert other architectural changes along the way.
In the meantime, NVIDIA has announced and started to deliver its next-generation architecture, Fermi. In that previous column, I had promised a comparison of the Larrabee architectural features to those of the NVIDIA Tesla and Fermi; however, when Intel pulled the plug on Larrabee, such a comparison seemed moot. With Larrabee’s resurrection and rebranding, perhaps it’s an appropriate topic again. So let’s start with a short architecture review of the Intel MIC and NVIDIA Fermi (aka Tesla-20 series).
Review: Intel MIC
The Knights Ferry has 32 x86 cores on chip, each with 32KB L1 instruction cache, 32KB L1 data cache, and 256KB L2 cache. I will refer to them as 32 processors. Each processor has a vector unit, essentially a very wide (512 bits or 16 floats) SSE unit, allowing 16 single precision floating point operations in a single instruction. Double-precision compute throughput is half that of single-precision. The 32 data caches are kept coherent by a ring network, which is also the connection to the on-chip memory interface(s). Each processor supports a multithreading depth of four, enough to keep the processor busy while filling an L1 cache miss. The Knights Ferry is implemented on a PCI card, and has its own memory, connected to the host memory through PCI DMA operations. This interface may change in future editions, but Intel advertises the MIC as “an Intel Co-Processor Architecture.” This could be taken as acknowledgement that accelerators can play a legitimate role in the high performance market.
Review: NVIDIA Fermi
The new NVIDIA Fermi architecture has up to 512 CUDA cores, though the largest cards being delivered to date have 480 or 448. These are organized into 14 streaming multiprocessors, each with two sets of 16 thread processors. I will call this 14 dual processors, or 28 processors, each with 16 thread processors, allowing 16 single precision floating point operations in a single cycle in each processor. Double precision throughput is half that of single precision, like current CPUs. Each processor has a 64KB data cache, part of which is hardware managed, like the MIC, and part software managed. Exactly how much is hardware vs. software managed is selectable by the program. There is also 768KB shared L2 data cache. Each streaming multiprocessor supports a multithreading depth of 48, though that must keep two processors busy, so we’ll call this a depth of 24 for each processor.
So now we can start to compare the designs. Here we’ll focus on Intel Knights Ferry and NVIDIA Fermi. Fermi is available now, and Knights Ferry is being provided to selected Intel customers for experimentation and evaluation. The MIMD parallelism level is about the same, 32 for the MIC and 28 for current Fermi chips. The SIMD parallelism is also the same, at 16. The multithreading context parallelism favors Fermi, 24 vs. 4. Keep in mind that the multithreading contexts don’t actually compute in parallel; multithreading only comes into play when one thread is stalled on memory or some other long latency operation. Intel is likely depending on its larger cache memory to satisfy most memory operations quickly, whereas NVIDIA uses a high multithreading degree instead. If Knights Ferry is similar to Larrabee, it has a dual-issue control unit, for two-wide instruction-level parallelism, something the current Fermi does not. Both use in-order instruction issue, simplifying the control unit, leaving more silicon real estate for functional units, registers, memory, and so on. This puts more emphasis on the compiler, since instruction count again becomes an important metric for performance.
Comparison: Parallelism Model
Both architectures support a shared-memory programming model, though they are quite different in the details. The MIC supports a more classical coherent shared-memory parallel programming paradigm. All memory accesses through the cache are kept coherent through the fast interprocessor ring network. Dynamic parallelism, where parallel threads spawn new parallel threads, is fully supported.
The NVIDIA GPUs require very structured parallelism. The program must be divided into kernels, where each kernel executes on a multidimensional rectangular domain. The domain has MIMD dimensions and SIMD dimensions. The parallel MIMD dimension, which is spread across the processors, can only synchronize at the implicit barrier between kernels. If two threads on different processors try to communicate through the shared memory, no result is guaranteed.
Comparison: Memory Organization
Let’s look at the memory organization. The Intel MIC uses a classical two-level cache per core, whereas Fermi uses a combination of software-managed and hardware-managed data cache. The effectiveness of a software-managed data cache depends on the ability of the programmer or compiler to take advantage of it. The effectiveness of a hardware cache depends on the locality of data accesses. For many applications, hardware caches work quite well. For stream processing on large data sets, they are less useful. Fermi has a very high bandwidth path (140GB/sec) to the main memory. It’s unlikely that the current Intel MIC can compete on raw bandwidth. The above-mentioned 2008 SIGGRAPH article about Larrabee describes some of the algorithmic details used to make effective use of the caches.
Both cards have a separate memory from the host and function as attached processors. For NVIDIA, the program allocates memory in the device memory, copies data from the host to device across the PCI bus, launches kernels on the device, and copies results back to the host. There is no virtual memory support on the GPU, and addresses on the host and the device are distinct. This means the program must manage host and GPU addresses separately.
Assuming the Intel MIC is similar to Larrabee, the same sequence of operations must take place. However, the x86 cores support full virtual memory translation, and the cores run a reasonably complete microkernel operating system. The support software allows a shared address space across the host and the accelerator. Note: this is easily confused with shared memory, which it is not. When the accelerator gets a page fault for data shared with the host, the operating system will move the page from the host to the device memory, marking it read-only or unavailable on the host side. Similarly, if the host gets a page fault on a shared page, the operating system will move the page back. In both cases, the data is being moved across the relatively slow PCI bus, but since it occurs without programmer intervention, it simulates shared memory. The real advantage of this approach isn’t that the data gets automatically moved, but that the same address can be used on the MIC as on the host. For high performance, the programmer should insert API calls to tell the support software when to move what data to which memory, so as to amortize the data movement latency. This is essentially the same work the NVIDIA programmer has to do, except the same address pointer can be used on both sides.
Comparison: Support for Parallelism
There are four issues with parallelism support: What is a thread? How are the parallel threads created? How are the threads scheduled across the processors, and is there support for user control (tuning)? How do the threads synchronize?
Fermi is designed to run parallel algorithms, and includes built-in support for parallelism control and synchronization. When you launch a parallel kernel, the program gives the shape of the rectangular domain and the address of the kernel code. The NVIDIA hardware creates and distributes the parallel instances of the kernel across the processors, initiating new instances as they complete or to take advantage of multithreading parallelism. The threads are fine-grained and short-lived; new threads are created as fast as old ones complete. In addition, there is hardware support for fast barrier synchronization among SIMD threads in the same thread group (and on the same processor). So thread creation and scheduling is fast, but there is no real support for tuning, and synchronization is very fast, but limited.
The MIC uses classical software thread creation, scheduling and synchronization. As with common multiprocessor and multicore implementations, threads are coarse grain and have a long lifetime. Thread creation is relatively inexpensive, but it’s likely that parking and recycling threads will be much more efficient than recreating threads each time they are needed. Scheduling is done by the operating system, but a lightweight task scheduling API, such as was provided for Larrabee, will allow user tuning. Synchronization is done in software using memory semaphores, depending on the hardware cache coherence ring. Here, Intel trades performance for flexibility and standardization.
Comparison: Programming Tools
Fermi is programmed through several specialty languages. OpenGL and DirectX are used for graphics, but most compute programming is done using the extended C CUDA language. Reprogramming for the NVIDIA requires a substantial effort in extracting the computational kernels, inserting device memory management, and adding the control code in the host program. For many applications, the performance payoff is worth the effort. There are several other products (including one from PGI) and development efforts using directives or language primitives to ease the coding effort, and the OpenCL standardization effort as well.
The Intel MIC will be programmed using native C/C++ compilers from Intel, and presumably from other sources as well. If the program is already parallelized with threads and the compiler vectorizes the code successfully, then the program may be ported with nothing more than a recompile (or so we can dream, anyway). In any case, the amount of restructuring to get started is likely to be quite a bit less intrusive than for NVIDIA. Getting high performance requires exploiting the two levels of parallelism (multicore and wide SSE), optimizing for memory strides and locality, and minimizing data communication between the host and MIC coprocessor, exactly the same problems you have coding for a GPU with CUDA or OpenCL.
NVIDIA has been delivering the Fermi for some months, using a 40nm TSMC process with a 1.1GHz clock. We can expect NVIDIA to have a new spin of their product in the 2011 time frame, ready to compete with the Knights Ferry, by which time TSMC is reported to be delivering its 28nm process in bulk.
The Intel Knights Ferry MIC is being initially introduced in a 32-core version using a 45nm process, reportedly with a 1.2GHz clock. Intel is already delivering CPU chips with its 32nm process. The Knights Corner product will use Intel’s upcoming 22nm process, with more than 50 cores. It’s hard to compete with Intel’s technology. Few companies have the capital to experiment and develop new technology, and build the new chip fabrication plants to use it. Intel is perhaps foremost among them.
Intel can afford to stay ahead of the competition in silicon technology. NVIDIA and other competitors have to make up the difference with architecture.
My scorecard on the Intel MIC vs. NVIDIA Fermi battle shows them addressing the same problems (highly parallel applications) with some of the same features (many processors with wide SIMD operations), but with significant differences. Intel lives and breathes with x86 compatibility, and this is a new avenue for the x86 instruction set. NVIDIA has the luxury of more flexibility with instruction set and design parameters.
|Intel MIC||NVIDIA Fermi|
|programming model||posix threads||CUDA kernels|
|memory shared with host||no||no|
|hardware parallelism support||no||yes|
It will be even more interesting to see this comparison in 18-24 months, when the Intel Knights Corner is available, and NVIDIA has had time for another successor. Will Intel opt to put the Knights Corner in a QuickPath Interconnect slot? Will the memory bandwidth requirements of a manycore chip require a separate memory interface? At the same time, AMD is promising to deliver its Fusion chip, with a CPU and GPU on the same die. Will it intermix host virtual memory with high bandwidth GPU memory?
Accelerators in HPC
It’s clear that compute accelerators will play a role in high performance computing. All the vendors have gone or are going down that route. The questions are which applications will be able to make effective use of accelerators, which accelerator architectures will survive and thrive, and, most interesting to me, how will we program them? A programming model that allows or even promotes both functional and performance portability across a range of accelerators is in order now.
There are at least four general approaches to parallel programming, all of which apply to accelerators.
- You can use optimized libraries. This is the basis of the BLAS and LAPACK libraries, among many (many) others. You program with calls to the library, and depend on the vendor or other provider to optimize the library for your machine. There are already several versions of linear algebra routines for CUDA targets, for instance. The routines in the library essentially become the vocabulary of your language. Programs that can be expressed in this vocabulary can achieve high performance. The performance of your own code becomes unimportant, assuming most of the computation is done in the library routines. The downside is that the library calls are opaque, not only to the programmer, but to each other. A library can’t take advantage of a sequence of operations, such as a matrix transpose followed by a matrix product, that could be optimized together.
- In an object-oriented language, you can use optimized class libraries. The advantage of a class library is the ability to use your own data types and operators in the scope of the class. It does require coding to the class, and the class author must provide source code to get the full benefit, which is usually not a problem in the open source science community. Optimized class libraries have the advantage that the compiler can use function inlining to generate better code. However, this is the only trick that compilers have. A class library has no semantic advantage. There is nothing you can implement with a class library that you couldn’t have written in C, although it would take much, much more effort in C. Also, the class methods don’t compose well unless they can be inlined and optimized together.
- There are new languages targeting parallel programming or accelerator programming. Here we have CUDA (C and Fortran) for NVIDIA GPUs, and OpenCL being proposed as a more general solution. OpenCL solves part of the problem, providing functional and programming skill portability. But OpenCL is intentionally very low level; programs tuned for architecture A may not perform so well on machines B, C or D.
- Finally, we have compiler-based programming, using either automatic or semi-automatic (directive-based) analysis. There are several research and commercial efforts in this direction, and the OpenMP language committee has a subgroup working on standardizing a set of accelerator directives, based largely on proposals by PGI and Cray, to allow programming and tuning across a wide range of accelerators. One advantage of using compilers is they can give performance prediction feedback, something no library will do. The disadvantage is that compilers are large and complex pieces of software, and it’s challenging to mesh a new programming model seamlessly into an existing language.
A successful programming model will allow tuning for the critical performance features in a portable way. Common themes across the accelerator architectures we see today include managing data transfers between memory spaces (host and accelerator), exploiting two levels of parallelism (MIMD or multicore, and SIMD or vector), and optimizing memory strides and locality. CUDA and OpenCL allow for performance tuning, but portability is in question. The best overall solution will be a high level programming model that interoperates with highly-tuned low-level kernels, in the same way that we use high level languages today with highly tuned mathematics and statistics libraries, often written in assembly language.
About the Author
Michael Wolfe has developed compilers for over 30 years in both academia and industry, and is now a senior compiler engineer at The Portland Group, Inc. (www.pgroup.com), a wholly-owned subsidiary of STMicroelectronics, Inc. The opinions stated here are those of the author, and do not represent opinions of The Portland Group, Inc. or STMicroelectronics, Inc.