Intel Flexes Parallel Programming Muscles

By Michael Feldman

September 2, 2010

Intel Corp has released Parallel Studio 2011, a set of four tools designed to mainstream software development on multicore x86 architectures. This is the second version of the software development suite, building on top of the original Parallel Studio offering introduced in May 2009. The update folds in a number of parallel programming technologies that the company has acquired or developed independently over the past few years, including the Cilk Arts and RapidMind technologies, and Intel’s own Ct data parallel language framework.

Like its predecessor, Parallel Studio 2011 is available as a set of plug-ins to Microsoft’s Visual Studio. As such, it is aimed at the Windows C/ C++ crowd, but some of the technology will soon migrate into Intel’s purpose-built HPC offerings as well. More about that in a bit.

The new release is designed as a soup to nuts development suite that encompasses the entire programming workflow: design, build, debug, verify and tune. To support that range of capabilities, Intel has brought over the three original tools, Parallel Inspector, Parallel Amplifier, and Parallel Composer; thrown in an additional one, Parallel Advisor; and introduced an integrated multicore programming environment, known as Parallel Building Blocks (PBB).

Looking at the elements inherited from the original suite, Composer is still the central development tool, and includes the compilers and libraries needed for code production. It now also incorporates the aforementioned PBB, which is new for this release. The Amplifier tool is used to find hot spots and make sure application performance scales properly when parallelization is applied. Finally, the Inspector tool performs memory checking and uncovers thread error conditions, specifically, data races and deadlocks.

The most notable new capability of the 2011 offering is wrapped up in Parallel Building Blocks. Prior to this release, Parallel Studio apps could use Intel’s Threading Building Blocks (TBB), OpenMP, or the Windows threading API to parallelize software. In the new release, Intel has retained the TBB framework and added two other parallel frameworks: Cilk Plus and Array Building Blocks (ABB). All three are built on top of top of Microsoft’s Concurrency Runtime, which was introduced with Visual Studio 2010. The runtime acts as a resource manager that glues all these frameworks together so they can play nicely with one another within the same app.

Threading Building Blocks is Intel’s original high-level framework for task parallelism on multicore x86. It was introduced three years ago, and is now considered one of the leading parallel development environments for C/C++. It’s implemented as a C++ template library and is used across many computing segments, including technical computing. To complement TBB, Intel has added Array Building Blocks, another C++ template library, but in this case for data parallelism.

If this sounds a bit like Intel’s Ct (C/C++ for throughput computing), that’s because it essentially is. Intel has folded their Ct language technology, along with the RapidMind technology they acquired a year ago, into ABB. Currently in beta, Intel is planning the full ABB product release for next year.

Cilk Plus is the other programming framework that has been productized for Parallel Studio. It’s sort of the odd one out. The technology was acquired when Intel bought Cilk Arts at about the same time as the RapidMind buy. Cilk, the language, is an extension of C/C++ that includes extra keywords to specify parallelism. Cilk Plus adds C/C++ extensions for array notation and represents a solution that incorporates both task and data parallelism. In this framework, the source code is statically compiled (which differentiates it from the more dynamic runtime implementations of TBB and ABB), making it the first choice if lower runtime overhead and a less intrusive coding model is preferred.

Finally, the new Advisor tool helps programmers expedite the design phase of parallel programming. It has been available in beta (as Parallel Advisor Lite) since last May, but is now ready for prime time. Its central purpose is to guide developers through a process that helps them transition their sequential codes into parallel ones.

Each tool can be purchased separately for $399 or bought as a complete package for $799. At that price, the package deal obviously makes sense if you buy two or more tools. And since Composer, which contains the parallel compilers and libraries, is mandatory for code development, once you opt for an additional tool, you might as well take the whole package.

Although Parallel Studio is targeted to C/C++ developers on the Windows client, some of the technology will end up in Intel’s HPC cluster toolset as well. According to Bill Savage, Intel’s vice president and general manager of the General Products Division, Software and Services Group, the Parallel Building Blocks programming frameworks, in particular, will be integrated into Intel’s compilers and runtime libraries aimed at high performance computing applications . The idea is to be able to use the PBB technology for programming the multicore nodes within a distributed MPI-type application. That will entail making these frameworks Fortran- and Linux-friendly, and at some point, adding compiler support for Intel’s Many Integrated Core (MIC), aka Knights Ferry, architecture. Savage said some of this technology will show up in Intel’s HPC portfolio later this year.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

ISC18’s Industrial Day Slate: Digital Twins, CFD for Automotive, HPC for SMEs

June 23, 2018

For enterprise IT strategists, this year’s Industrial Day (Tuesday, June 26) at ISC18 in Frankfurt will cover a range of topics – digital twins, AI and machine learning in automotive design, HPC for SME’s and deve Read more…

By Doug Black

What’s Hot and What’s Not at ISC 2018?

June 22, 2018

As the calendar rolls around to late June we see the ISC conference, held in Frankfurt (June 24th-28th), heave into view. With some of the pre-show announcements already starting to roll out, what do we think some of the Read more…

By Dairsie Latimer

Servers in Orbit, HPE Apollos Make 4,500 Trips Around Earth

June 22, 2018

The International Space Station shines a little brighter in the night sky thanks to what amounts to an orbiting supercomputer lofted to the outpost last year as part of a year-long experiment to determine if high-end com Read more…

By George Leopold

HPE Extreme Performance Solutions

HPC and AI Convergence is Accelerating New Levels of Intelligence

Data analytics is the most valuable tool in the digital marketplace – so much so that organizations are employing high performance computing (HPC) capabilities to rapidly collect, share, and analyze endless streams of data. Read more…

IBM Accelerated Insights

Taking the AI Training Wheels Off: From PoC to Production

Even though it seems simple now, there were a lot of skills to master in learning to ride a bike. From balancing on two wheels, and steering in a straight line, to going around corners and stopping before running over the dog, it took lots of practice to master these skills. Read more…

HPCwire Readers’ and Editors’ Choice Awards Turns 15

June 22, 2018

A hallmark of sustainability is this: If you are not serving a need effectively and efficiently you do not last. The HPCwire Readers’ and Editors’ Choice awards program has stood the test of time. Each year, our read Read more…

By Tiffany Trader

What’s Hot and What’s Not at ISC 2018?

June 22, 2018

As the calendar rolls around to late June we see the ISC conference, held in Frankfurt (June 24th-28th), heave into view. With some of the pre-show announcement Read more…

By Dairsie Latimer

Servers in Orbit, HPE Apollos Make 4,500 Trips Around Earth

June 22, 2018

The International Space Station shines a little brighter in the night sky thanks to what amounts to an orbiting supercomputer lofted to the outpost last year as Read more…

By George Leopold

HPCwire Readers’ and Editors’ Choice Awards Turns 15

June 22, 2018

A hallmark of sustainability is this: If you are not serving a need effectively and efficiently you do not last. The HPCwire Readers’ and Editors’ Choice aw Read more…

By Tiffany Trader

ISC 2018 Preview from @hpcnotes

June 21, 2018

Prepare for your social media feed to be saturated with #HPC, #ISC18, #Top500, etc. Prepare for your mainstream media to talk about supercomputers (in between t Read more…

By Andrew Jones

AMD’s EPYC Road to Redemption in Six Slides

June 21, 2018

A year ago AMD returned to the server market with its EPYC processor line. The earth didn’t tremble but folks took notice. People remember the Opteron fondly Read more…

By John Russell

European HPC Summit Week and PRACEdays 2018: Slaying Dragons and SHAPEing Futures One SME at a Time

June 20, 2018

The University of Ljubljana in Slovenia hosted the third annual EHPCSW18 and fifth annual PRACEdays18 events which opened May 29, 2018. The conference was chair Read more…

By Elizabeth Leake (STEM-Trek for HPCwire)

Cray Introduces All Flash Lustre Storage Solution Targeting HPC

June 19, 2018

Citing the rise of IOPS-intensive workflows and more affordable flash technology, Cray today introduced the L300F, a scalable all-flash storage solution whose p Read more…

By John Russell

Sandia to Take Delivery of World’s Largest Arm System

June 18, 2018

While the enterprise remains circumspect on prospects for Arm servers in the datacenter, the leadership HPC community is taking a bolder, brighter view of the x86 server CPU alternative. Amongst current and planned Arm HPC installations – i.e., the innovative Mont-Blanc project, led by Bull/Atos, the 'Isambard’ Cray XC50 going into the University of Bristol, and commitments from both Japan and France among others -- HPE is announcing that it will be supply the United States National Nuclear Security Administration (NNSA) with a 2.3 petaflops peak Arm-based system, named Astra. Read more…

By Tiffany Trader

MLPerf – Will New Machine Learning Benchmark Help Propel AI Forward?

May 2, 2018

Let the AI benchmarking wars begin. Today, a diverse group from academia and industry – Google, Baidu, Intel, AMD, Harvard, and Stanford among them – releas Read more…

By John Russell

How the Cloud Is Falling Short for HPC

March 15, 2018

The last couple of years have seen cloud computing gradually build some legitimacy within the HPC world, but still the HPC industry lies far behind enterprise I Read more…

By Chris Downing

US Plans $1.8 Billion Spend on DOE Exascale Supercomputing

April 11, 2018

On Monday, the United States Department of Energy announced its intention to procure up to three exascale supercomputers at a cost of up to $1.8 billion with th Read more…

By Tiffany Trader

Deep Learning at 15 PFlops Enables Training for Extreme Weather Identification at Scale

March 19, 2018

Petaflop per second deep learning training performance on the NERSC (National Energy Research Scientific Computing Center) Cori supercomputer has given climate Read more…

By Rob Farber

ORNL Summit Supercomputer Is Officially Here

June 8, 2018

Oak Ridge National Laboratory (ORNL) together with IBM and Nvidia celebrated the official unveiling of the Department of Energy (DOE) Summit supercomputer toda Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Hennessy & Patterson: A New Golden Age for Computer Architecture

April 17, 2018

On Monday June 4, 2018, 2017 A.M. Turing Award Winners John L. Hennessy and David A. Patterson will deliver the Turing Lecture at the 45th International Sympo Read more…

By Staff

Google Chases Quantum Supremacy with 72-Qubit Processor

March 7, 2018

Google pulled ahead of the pack this week in the race toward "quantum supremacy," with the introduction of a new 72-qubit quantum processor called Bristlecone. Read more…

By Tiffany Trader

Leading Solution Providers

SC17 Booth Video Tours Playlist

Altair @ SC17

Altair

AMD @ SC17

AMD

ASRock Rack @ SC17

ASRock Rack

CEJN @ SC17

CEJN

DDN Storage @ SC17

DDN Storage

Huawei @ SC17

Huawei

IBM @ SC17

IBM

IBM Power Systems @ SC17

IBM Power Systems

Intel @ SC17

Intel

Lenovo @ SC17

Lenovo

Mellanox Technologies @ SC17

Mellanox Technologies

Microsoft @ SC17

Microsoft

Penguin Computing @ SC17

Penguin Computing

Pure Storage @ SC17

Pure Storage

Supericro @ SC17

Supericro

Tyan @ SC17

Tyan

Univa @ SC17

Univa

Google I/O 2018: AI Everywhere; TPU 3.0 Delivers 100+ Petaflops but Requires Liquid Cooling

May 9, 2018

All things AI dominated discussion at yesterday’s opening of Google’s I/O 2018 developers meeting covering much of Google's near-term product roadmap. The e Read more…

By John Russell

Pattern Computer – Startup Claims Breakthrough in ‘Pattern Discovery’ Technology

May 23, 2018

If it weren’t for the heavy-hitter technology team behind start-up Pattern Computer, which emerged from stealth today in a live-streamed event from San Franci Read more…

By John Russell

Nvidia Ups Hardware Game with 16-GPU DGX-2 Server and 18-Port NVSwitch

March 27, 2018

Nvidia unveiled a raft of new products from its annual technology conference in San Jose today, and despite not offering up a new chip architecture, there were still a few surprises in store for HPC hardware aficionados. Read more…

By Tiffany Trader

Sandia to Take Delivery of World’s Largest Arm System

June 18, 2018

While the enterprise remains circumspect on prospects for Arm servers in the datacenter, the leadership HPC community is taking a bolder, brighter view of the x86 server CPU alternative. Amongst current and planned Arm HPC installations – i.e., the innovative Mont-Blanc project, led by Bull/Atos, the 'Isambard’ Cray XC50 going into the University of Bristol, and commitments from both Japan and France among others -- HPE is announcing that it will be supply the United States National Nuclear Security Administration (NNSA) with a 2.3 petaflops peak Arm-based system, named Astra. Read more…

By Tiffany Trader

AMD’s EPYC Road to Redemption in Six Slides

June 21, 2018

A year ago AMD returned to the server market with its EPYC processor line. The earth didn’t tremble but folks took notice. People remember the Opteron fondly Read more…

By John Russell

Part One: Deep Dive into 2018 Trends in Life Sciences HPC

March 1, 2018

Life sciences is an interesting lens through which to see HPC. It is perhaps not an obvious choice, given life sciences’ relative newness as a heavy user of H Read more…

By John Russell

Intel Pledges First Commercial Nervana Product ‘Spring Crest’ in 2019

May 24, 2018

At its AI developer conference in San Francisco yesterday, Intel embraced a holistic approach to AI and showed off a broad AI portfolio that includes Xeon processors, Movidius technologies, FPGAs and Intel’s Nervana Neural Network Processors (NNPs), based on the technology it acquired in 2016. Read more…

By Tiffany Trader

Google Charts Two-Dimensional Quantum Course

April 26, 2018

Quantum error correction, essential for achieving universal fault-tolerant quantum computation, is one of the main challenges of the quantum computing field and it’s top of mind for Google’s John Martinis. At a presentation last week at the HPC User Forum in Tucson, Martinis, one of the world's foremost experts in quantum computing, emphasized... Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This