Intel Flexes Parallel Programming Muscles

By Michael Feldman

September 2, 2010

Intel Corp has released Parallel Studio 2011, a set of four tools designed to mainstream software development on multicore x86 architectures. This is the second version of the software development suite, building on top of the original Parallel Studio offering introduced in May 2009. The update folds in a number of parallel programming technologies that the company has acquired or developed independently over the past few years, including the Cilk Arts and RapidMind technologies, and Intel’s own Ct data parallel language framework.

Like its predecessor, Parallel Studio 2011 is available as a set of plug-ins to Microsoft’s Visual Studio. As such, it is aimed at the Windows C/ C++ crowd, but some of the technology will soon migrate into Intel’s purpose-built HPC offerings as well. More about that in a bit.

The new release is designed as a soup to nuts development suite that encompasses the entire programming workflow: design, build, debug, verify and tune. To support that range of capabilities, Intel has brought over the three original tools, Parallel Inspector, Parallel Amplifier, and Parallel Composer; thrown in an additional one, Parallel Advisor; and introduced an integrated multicore programming environment, known as Parallel Building Blocks (PBB).

Looking at the elements inherited from the original suite, Composer is still the central development tool, and includes the compilers and libraries needed for code production. It now also incorporates the aforementioned PBB, which is new for this release. The Amplifier tool is used to find hot spots and make sure application performance scales properly when parallelization is applied. Finally, the Inspector tool performs memory checking and uncovers thread error conditions, specifically, data races and deadlocks.

The most notable new capability of the 2011 offering is wrapped up in Parallel Building Blocks. Prior to this release, Parallel Studio apps could use Intel’s Threading Building Blocks (TBB), OpenMP, or the Windows threading API to parallelize software. In the new release, Intel has retained the TBB framework and added two other parallel frameworks: Cilk Plus and Array Building Blocks (ABB). All three are built on top of top of Microsoft’s Concurrency Runtime, which was introduced with Visual Studio 2010. The runtime acts as a resource manager that glues all these frameworks together so they can play nicely with one another within the same app.

Threading Building Blocks is Intel’s original high-level framework for task parallelism on multicore x86. It was introduced three years ago, and is now considered one of the leading parallel development environments for C/C++. It’s implemented as a C++ template library and is used across many computing segments, including technical computing. To complement TBB, Intel has added Array Building Blocks, another C++ template library, but in this case for data parallelism.

If this sounds a bit like Intel’s Ct (C/C++ for throughput computing), that’s because it essentially is. Intel has folded their Ct language technology, along with the RapidMind technology they acquired a year ago, into ABB. Currently in beta, Intel is planning the full ABB product release for next year.

Cilk Plus is the other programming framework that has been productized for Parallel Studio. It’s sort of the odd one out. The technology was acquired when Intel bought Cilk Arts at about the same time as the RapidMind buy. Cilk, the language, is an extension of C/C++ that includes extra keywords to specify parallelism. Cilk Plus adds C/C++ extensions for array notation and represents a solution that incorporates both task and data parallelism. In this framework, the source code is statically compiled (which differentiates it from the more dynamic runtime implementations of TBB and ABB), making it the first choice if lower runtime overhead and a less intrusive coding model is preferred.

Finally, the new Advisor tool helps programmers expedite the design phase of parallel programming. It has been available in beta (as Parallel Advisor Lite) since last May, but is now ready for prime time. Its central purpose is to guide developers through a process that helps them transition their sequential codes into parallel ones.

Each tool can be purchased separately for $399 or bought as a complete package for $799. At that price, the package deal obviously makes sense if you buy two or more tools. And since Composer, which contains the parallel compilers and libraries, is mandatory for code development, once you opt for an additional tool, you might as well take the whole package.

Although Parallel Studio is targeted to C/C++ developers on the Windows client, some of the technology will end up in Intel’s HPC cluster toolset as well. According to Bill Savage, Intel’s vice president and general manager of the General Products Division, Software and Services Group, the Parallel Building Blocks programming frameworks, in particular, will be integrated into Intel’s compilers and runtime libraries aimed at high performance computing applications . The idea is to be able to use the PBB technology for programming the multicore nodes within a distributed MPI-type application. That will entail making these frameworks Fortran- and Linux-friendly, and at some point, adding compiler support for Intel’s Many Integrated Core (MIC), aka Knights Ferry, architecture. Savage said some of this technology will show up in Intel’s HPC portfolio later this year.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Tuning InfiniBand Interconnects Using Congestion Control

July 26, 2017

InfiniBand is among the most common and well-known cluster interconnect technologies. However, the complexities of an InfiniBand (IB) network can frustrate the most experienced cluster administrators. Maintaining a balan Read more…

By Adam Dorsey

NSF Project Sets Up First Machine Learning Cyberinfrastructure – CHASE-CI

July 25, 2017

Earlier this month, the National Science Foundation issued a $1 million grant to Larry Smarr, director of Calit2, and a group of his colleagues to create a community infrastructure in support of machine learning research Read more…

By John Russell

DARPA Continues Investment in Post-Moore’s Technologies

July 24, 2017

The U.S. military long ago ceded dominance in electronics innovation to Silicon Valley, the DoD-backed powerhouse that has driven microelectronic generation for decades. With Moore's Law clearly running out of steam, the Read more…

By George Leopold

HPE Extreme Performance Solutions

HPE Servers Deliver High Performance Remote Visualization

Whether generating seismic simulations, locating new productive oil reservoirs, or constructing complex models of the earth’s subsurface, energy, oil, and gas (EO&G) is a highly data-driven industry. Read more…

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in 2017 with scale-up production for enterprise datacenters and Read more…

By Tiffany Trader

Tuning InfiniBand Interconnects Using Congestion Control

July 26, 2017

InfiniBand is among the most common and well-known cluster interconnect technologies. However, the complexities of an InfiniBand (IB) network can frustrate the Read more…

By Adam Dorsey

NSF Project Sets Up First Machine Learning Cyberinfrastructure – CHASE-CI

July 25, 2017

Earlier this month, the National Science Foundation issued a $1 million grant to Larry Smarr, director of Calit2, and a group of his colleagues to create a comm Read more…

By John Russell

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in Read more…

By Tiffany Trader

Fujitsu Continues HPC, AI Push

July 19, 2017

Summer is well under way, but the so-called summertime slowdown, linked with hot temperatures and longer vacations, does not seem to have impacted Fujitsu's out Read more…

By Tiffany Trader

Researchers Use DNA to Store and Retrieve Digital Movie

July 18, 2017

From abacus to pencil and paper to semiconductor chips, the technology of computing has always been an ever-changing target. The human brain is probably the com Read more…

By John Russell

The Exascale FY18 Budget – The Next Step

July 17, 2017

On July 12, 2017, the U.S. federal budget for its Exascale Computing Initiative (ECI) took its next step forward. On that day, the full Appropriations Committee Read more…

By Alex R. Larzelere

Women in HPC Luncheon Shines Light on Female-Friendly Hiring Practices

July 13, 2017

The second annual Women in HPC luncheon was held on June 20, 2017, during the International Supercomputing Conference in Frankfurt, Germany. The luncheon provid Read more…

By Tiffany Trader

Satellite Advances, NSF Computation Power Rapid Mapping of Earth’s Surface

July 13, 2017

New satellite technologies have completely changed the game in mapping and geographical data gathering, reducing costs and placing a new emphasis on time series Read more…

By Ken Chiacchia and Tiffany Jolley

Google Pulls Back the Covers on Its First Machine Learning Chip

April 6, 2017

This week Google released a report detailing the design and performance characteristics of the Tensor Processing Unit (TPU), its custom ASIC for the inference Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Quantum Bits: D-Wave and VW; Google Quantum Lab; IBM Expands Access

March 21, 2017

For a technology that’s usually characterized as far off and in a distant galaxy, quantum computing has been steadily picking up steam. Just how close real-wo Read more…

By John Russell

HPC Compiler Company PathScale Seeks Life Raft

March 23, 2017

HPCwire has learned that HPC compiler company PathScale has fallen on difficult times and is asking the community for help or actively seeking a buyer for its a Read more…

By Tiffany Trader

Trump Budget Targets NIH, DOE, and EPA; No Mention of NSF

March 16, 2017

President Trump’s proposed U.S. fiscal 2018 budget issued today sharply cuts science spending while bolstering military spending as he promised during the cam Read more…

By John Russell

CPU-based Visualization Positions for Exascale Supercomputing

March 16, 2017

In this contributed perspective piece, Intel’s Jim Jeffers makes the case that CPU-based visualization is now widely adopted and as such is no longer a contrarian view, but is rather an exascale requirement. Read more…

By Jim Jeffers, Principal Engineer and Engineering Leader, Intel

Nvidia’s Mammoth Volta GPU Aims High for AI, HPC

May 10, 2017

At Nvidia's GPU Technology Conference (GTC17) in San Jose, Calif., this morning, CEO Jensen Huang announced the company's much-anticipated Volta architecture a Read more…

By Tiffany Trader

Facebook Open Sources Caffe2; Nvidia, Intel Rush to Optimize

April 18, 2017

From its F8 developer conference in San Jose, Calif., today, Facebook announced Caffe2, a new open-source, cross-platform framework for deep learning. Caffe2 is the successor to Caffe, the deep learning framework developed by Berkeley AI Research and community contributors. Read more…

By Tiffany Trader

Leading Solution Providers

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

Russian Researchers Claim First Quantum-Safe Blockchain

May 25, 2017

The Russian Quantum Center today announced it has overcome the threat of quantum cryptography by creating the first quantum-safe blockchain, securing cryptocurrencies like Bitcoin, along with classified government communications and other sensitive digital transfers. Read more…

By Doug Black

MIT Mathematician Spins Up 220,000-Core Google Compute Cluster

April 21, 2017

On Thursday, Google announced that MIT math professor and computational number theorist Andrew V. Sutherland had set a record for the largest Google Compute Engine (GCE) job. Sutherland ran the massive mathematics workload on 220,000 GCE cores using preemptible virtual machine instances. Read more…

By Tiffany Trader

Google Debuts TPU v2 and will Add to Google Cloud

May 25, 2017

Not long after stirring attention in the deep learning/AI community by revealing the details of its Tensor Processing Unit (TPU), Google last week announced the Read more…

By John Russell

Groq This: New AI Chips to Give GPUs a Run for Deep Learning Money

April 24, 2017

CPUs and GPUs, move over. Thanks to recent revelations surrounding Google’s new Tensor Processing Unit (TPU), the computing world appears to be on the cusp of Read more…

By Alex Woodie

Six Exascale PathForward Vendors Selected; DoE Providing $258M

June 15, 2017

The much-anticipated PathForward awards for hardware R&D in support of the Exascale Computing Project were announced today with six vendors selected – AMD Read more…

By John Russell

Top500 Results: Latest List Trends and What’s in Store

June 19, 2017

Greetings from Frankfurt and the 2017 International Supercomputing Conference where the latest Top500 list has just been revealed. Although there were no major Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This