The Week in Review

By Tiffany Trader

October 14, 2010

Here is a collection of highlights from this week’s news stream as reported by HPCwire.

Teams Gear Up for SC10 Student Cluster Competition

Ixia’s High Speed Ethernet Test Solutions Validate Mellanox ConnectX-2 NIC

Astronomer Employs HPC to Peer into Cosmic Mysteries

Nimbis Services Announces Cloud Services for Mathematica

Extreme Networks, SARA and CERN Complete First Long-Haul 40 GbE Link Across Europe

Ontario Advanced Network First to Launch Operational 100G Network

NOAA Establishes Supercomputing Center in West Virginia

Platform Computing, Excelian Partner to Deliver High Performance Analytics for Financial Services

AMAX Partners with Bright Computing to Maximize HPC Throughput

Ciena, Mellanox, SURFnet and University of Amsterdam Complete 40 Gbps, Long-Haul Optics Demonstration

Intel Reports First $11 Billion Revenue Quarter

SGI Announces Support and Record Benchmarks for VoltDB Database

Appro HF1 Server Targets High Frequency Traders

NEC Selects PBS Works as the Workload Management Tool for TSUBAME 2.0

Pittsburgh Supercomputing Center Boots Up ‘Blacklight’

Nimbis Services Launches HPC Workbook for Desktop Users

Deterministic Parallel Java Brings Safety and Modularity to Parallel Programming

Multicore Processors Key to Increasing Flexibility in High-Performance Networking, Report Finds

BLADE Switch Delivers One Terabit of Throughput

Switch maker BLADE Network Technologies (BLADE) today unveiled the RackSwitch G8264, a single-chip 40 Gigabit Ethernet (GbE) top-of-rack switch. The switch delivers more than one terabit of low-latency throughput to the datacenter. This is the first time that a single-chip switch is available for terabit-scale deployment of 10GbE.

The new switch touts 64-10GbE ports, up to four-40GbE ports and 1.28 terabits of non-blocking throughput. Designed to handle I/O-intensive and highly virtualized workloads, the switch is well suited for HPC clusters, cloud computing, and algorithmic trading.

BLADE is aiming to fulfill the needs of mainstream enterprise datacenters, which are responding to increased data demands by increasingly deploying servers equipped with 10GbE. BLADE is going forward with the belief that 40GbE is the next logical step. Higher speed uplinks, such as 10/40 Gigabit Ethernet switches, will be required to handle the increased network bandwidth of the next-generation of datacenters.

According to Vikram Mehta, president and CEO, BLADE Network Technologies:

“BLADE is proud to break the terabit barrier in a single-chip design with the RackSwitch G8264. Our new switch is designed for today’s most demanding requirements at the datacenter edge to interconnect highly utilized servers equipped with 10 Gigabit Ethernet and provide seamless migration to 40 Gigabit upstream networks.”

The RackSwitch G8264 will be available in November at a cost of $22,500 USD. Interested parties can view the product at the upcoming Supercomputing Conference (SC10).2

UC Riverside Physicists Advance Spin Computing

“Spin computing” — aka “spintronics” offers great potential for the future of computing — think superfast computers that can overcome present Moore’s Law limitations while using less energy and generating less heat than the current batch of number crunchers.

Here’s how it works: electrons can be polarized so that they have a particular directional orientation, called spin. An electron can either be polarized so attain two states, called “spin up” or “spin down.” Storing data with spin would effectively double the amount of data a computer could store since it allows two pieces of data to be stored on an electron instead of just one, as is currently the case.

While researchers have been working on the technology for about four decades, it’s not quite ready for primetime. This week, however, Physicists at the University of California, Riverside have taken spintronics to the next level by successfully achieving “tunneling spin injection” into graphene. Their study results appear this week in Physical Review Letters.

From the announcement:

Tunneling spin injection is a term used to describe conductivity through an insulator. Graphene, brought into the limelight by this year’s Nobel Prize in physics, is a single-atom-thick sheet of carbon atoms arrayed in a honeycomb pattern. Extremely strong and flexible, it is a good conductor of electricity and capable of resisting heat.

While graphene has characteristics that make it a very promising candidate for use in spin computers, the electrical spin injection from a ferromagnetic electrode into graphene is inefficient. Additionally, and even more troubling to the research team, observed spin lifetimes are thousands of times shorter than expected theoretically. Longer spin lifetimes are important because they allow for more computational operations.

The research team, led by Roland Kawakami, an associate professor of physics and astronomy, was able to dramatically increase the spin injection efficiency by inserting an insulating layer, known as a “tunnel barrier,” in between the electrode and the graphene layer. The team thus achieved the first demonstration of tunneling spin injection into graphene, and the 30-fold increase spin injection efficiency set a world record.

The Kawakami lab was also to reconcile the short spin lifetimes of electrons in graphene. They discovered that using the tunnel barrier increased the spin lifetime. According to Kawakami, graphene has the potential for extremely long spin lifetimes.

The next step for the Kawakami lab is to demonstrate a working spin logic device. Ultimately, a chip capable of manipulating the spin of a single electron could pave the way for futuristic quantum computers.

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Graphcore Readies Launch of 16nm Colossus-IPU Chip

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Fujitsu Continues HPC, AI Push

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HPE Extreme Performance Solutions

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Researchers Use DNA to Store and Retrieve Digital Movie

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Summer Reading: IEEE Spectrum’s Chip Hall of Fame

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Women in HPC Luncheon Shines Light on Female-Friendly Hiring Practices

July 13, 2017

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Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in Read more…

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Fine-Tuning Severe Hail Forecasting with Machine Learning

July 20, 2017

Depending on whether you’ve been caught outside during a severe hail storm, the sight of greenish tinted clouds on the horizon may cause serious knots in the Read more…

By Sean Thielen

Fujitsu Continues HPC, AI Push

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Researchers Use DNA to Store and Retrieve Digital Movie

July 18, 2017

From abacus to pencil and paper to semiconductor chips, the technology of computing has always been an ever-changing target. The human brain is probably the com Read more…

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The Exascale FY18 Budget – The Next Step

July 17, 2017

On July 12, 2017, the U.S. federal budget for its Exascale Computing Initiative (ECI) took its next step forward. On that day, the full Appropriations Committee Read more…

By Alex R. Larzelere

Women in HPC Luncheon Shines Light on Female-Friendly Hiring Practices

July 13, 2017

The second annual Women in HPC luncheon was held on June 20, 2017, during the International Supercomputing Conference in Frankfurt, Germany. The luncheon provid Read more…

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Satellite Advances, NSF Computation Power Rapid Mapping of Earth’s Surface

July 13, 2017

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Intel Skylake: Xeon Goes from Chip to Platform

July 13, 2017

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HPC Compiler Company PathScale Seeks Life Raft

March 23, 2017

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Quantum Bits: D-Wave and VW; Google Quantum Lab; IBM Expands Access

March 21, 2017

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Google Pulls Back the Covers on Its First Machine Learning Chip

April 6, 2017

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Nvidia Responds to Google TPU Benchmarking

April 10, 2017

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Trump Budget Targets NIH, DOE, and EPA; No Mention of NSF

March 16, 2017

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CPU-based Visualization Positions for Exascale Supercomputing

March 16, 2017

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Nvidia’s Mammoth Volta GPU Aims High for AI, HPC

May 10, 2017

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Facebook Open Sources Caffe2; Nvidia, Intel Rush to Optimize

April 18, 2017

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Leading Solution Providers

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Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

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MIT Mathematician Spins Up 220,000-Core Google Compute Cluster

April 21, 2017

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Google Debuts TPU v2 and will Add to Google Cloud

May 25, 2017

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Russian Researchers Claim First Quantum-Safe Blockchain

May 25, 2017

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By Doug Black

Groq This: New AI Chips to Give GPUs a Run for Deep Learning Money

April 24, 2017

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Six Exascale PathForward Vendors Selected; DoE Providing $258M

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