HPC Movers and Shakers: Thomas Sterling

By Nicole Hemsoth

October 29, 2010

Ah, New Orleans. The Big Easy. What a great selection for this year’s Supercomputing Conference. It was, in fact, in New Orleans where I first met Thomas Sterling. Thomas, or “Tron” to his friends, graciously invited me to join a small group for dinner one evening during an IEEE conference last summer. We dined at one of the city’s sumptuous restaurants in the Quarter, of course. It was over dinner that warm summer evening that I discovered that this highly respected man, the “father of Beowulf clusters,” has a sharp wit and irrepressible sense of humor that I found absolutely irresistible. There was no doubt in my mind about who my next column would feature as we head to the home of Louisiana State University for SC10.

HPCwire: Thomas, I love your nickname, “Tron.” How did you come by that handle?

Thomas: I had a feeling you were going to bring this up. My nickname Tron goes way back to my Navy days where I was a “tweet”, or aviation electronics technician, repairing F4 Phantom aircraft avionics. When something went really screwy with the electronics, the guys in the shop would blame the “tron god”. Now, I may not have been the most motivated squid in the “nav”, but when there was a really hard problem I was usually the one to tackle it. That’s where “tron” came from; some association with this notional tron god. It’s kind of a compliment, I guess. Later, when serving as an editor on my school paper I used “Tron” as a pen name, and then as my login at MIT, as well as my email address for the inchoate ARPAnet. It’s stayed with me ever since. As Herman Melville might have written, “Call me Tron”.

HPCwire: Speaking of names, you are highly regarded as “the father of Beowulf clusters” and for your research on petaflops computing architecture. I remember that Woody Allen once said you should never take a course where they make you read “Beowulf.” (Laughs) Seriously, though, why did you pick that name for your approach to commodity clusters?

Thomas: (Chuckling) The name was, I should be embarrassed to admit, a complete accident. I was sitting in my office at the Goddard Space Flight Center, and the Program Manager called saying they were sending in the paperwork for my new project and they needed a name for it. I had been putting her off for close to a month. She said she would not hang up until she had a name, or there would not be a project.

I respond well to threats. I needed inspiration and looked around my office in desperation when I noticed at the top of a stack of books my mother’s old copy of Beowulf. I remember saying to the PM, and this is a quote: “Oh hell, just call it ‘Beowulf’; nobody will ever hear of it anyway!” And seriously, that’s how it happened. Someone in the press started calling our Linux clusters “Beowulf-class systems,” so they, whoever they were, get credit for giving the actual clusters that name.

I think there is a lesson here; I’m just not sure what it is.

HPCwire: What’s your stance on shared versus distributed memory? Will we continue to build petascale computers with global shared memory, similar to the legacy products from Sun or SGI, or do you think the programming will be different?

Thomas: This is an important topic and reflects the diversity of experiences that drive perspective, and hence conflict. A major problem is our terminology; our words do not provide us with an effective lexicon to consider all possibilities. For example: “distributed memory.” Does this mean physically separate with intervening distance, blocks of memory not sharing a unified name space, both, or something else? When memory access times are dominated not by the DRAM cycle time but the latency of communication, it is distributed memory. I expect this to be the case for the largest machines of the future. I also expect that hardware support for global address space and unified name spaces are required for efficiency, programmability, and scalability. That sounds like “shared memory.” But now there is that last issue: is it cache coherent? And the answer there is: No, not in the usual sense. But the full explanation to this is too long for a brief interview!

HPCwire: Speaking of which, there are still people out there who long for the days when supercomputers were specialized custom designs and not built out of consumer-grade electronics like Beowulf clusters. What do you say to those people? Will we ever return to using technology specifically crafted for HPC?

Thomas: I am among those who feel that design driven by HPC requirements is essential to advance the field towards Exascale. However, those same changes will be useful for general-purpose and commercial computing as well.

Many ideas first realized in “specialized” HPC designs have migrated into the common general-purpose microprocessor of today. My expectation is that we will continue to use general-purpose devices, but they will change in accordance with the needs of scalability, efficiency, and parallel programmability.

HPCwire: I’ve heard you refer to new “execution models” too. What does that mean? What’s wrong with the current execution models?

Thomas: An execution model is a set of governing principles guiding the co-design and operation of the many interoperable layers of a computing system. It permits the use of the notion of the “decision chain” that recognizes a set of contributing influences. Understanding the decision chain contributes to determining why the operation was performed where and when it was.

Throughout the extraordinary evolution of supercomputing, spanning twelve orders of magnitude in a single lifetime, advancing technologies have required adjustments to the way we organize structures and methods of operation. For instance, a change of balance in bandwidth versus capacity. At least five times we have experienced a revolution in supercomputing. A “6th phase change” is due, and is best represented as a new model of computation.

HPC is in the midst of such a phase change because the technologies are already seen to require different ways of organizing systems, such as multi-core and GPU accelerators. CSP and MPI will not fulfill the needs of all applications on all system classes.

HPCwire: So, you agree with the people who think that MPI is at the end of its rope, and that we need something new, soon. Are you working on alternative programming models?

Thomas: MPI is not near the end of its rope, but we do need something new soon. MPI even in its current form will serve many applications on many systems for many years.

HPCwire: One of your Caltech friends put me up to asking you this one; what do you miss about Caltech?

Thomas: No question, Caltech is a special place, and even after five years I get homesick for it occasionally. There is a mindset there that any fundamental question in science or engineering can be investigated by bright minds to reveal some, if not all, of its secrets. It is the right to strive, to exceed, to understand, that I miss most. Oh, and the strawberry lemonades at the Athenaeum, of course.

HPCwire: So, are there things you can do at LSU that are easier than if you were still at Caltech?

Thomas: Joining the faculty at LSU was a risk, both for LSU and for me! A large state school is a very different environment than boutique intellectual environments such as Caltech, and that concerned me. I had not served as a tenured Professor before and that was a risk for LSU as well. They wanted someone who would rapidly expand their research program in the area of HPC systems with high national exposure. LSU, with support of the state of Louisiana, established the Center for Computation and Technology that complemented the capabilities of the academic departments by providing an advanced environment for interdisciplinary research to foster the goals of both LSU and Louisiana. This has turned out to be a great fit and both LSU and I have benefitted from this new relationship.

HPCwire: What can you share with us about the research you are doing at LSU with “ParalleX”?

Thomas: The research we have undertaken at LSU is risky and driven by the premise that the field of HPC is in that 6th phase change, as discussed above. The ParalleX execution model is a new synthesis of a collection of abstract constructs, relationships, and functional mechanisms to address starvation, latency, overhead, and contention in systems comprising more than a billion simultaneous executing entities with worst-case latencies on the order of a hundred thousand cycles. Recently, the LSU group has teamed with Guang Gao at the University of Delaware, an expert in many related fields, to expand and improve the product of this research under the auspices of the DARPA UHPC Program, the Sandia-led X-Caliber team, and the Intel-led Runnemede team.

HPCwire: This is my ‘live your dream question’: If you could wave a wand and change something about the way HPC is today, what would that thing be?

Thomas: (pause) It basically comes down to having cores designed to operate efficiently in the context of a billion other like cores on a single computational problem, returning us to the notion of a single computer rather than merely a large loose collection of cores using software-managed I/O.

Maybe this does sound like something out of Hogwarts.

HPCwire: I have experienced firsthand your irrepressible sense of humor. What’s the funniest thing you’ve seen in this business?

Thomas: (Laughs) I always get into trouble when I think something is funny but the humor is often lost on others. One time when giving a talk at Los Alamos, I brought up the early energy-efficient computer, “Green Destiny” which, unfortunately, did not perform well, at least initially. I commented: “I don’t get it. Why don’t they just unplug the thing? They’d save even more power and get almost the same performance!” I was never invited back.

At a panel at the Supercomputing conference one year, a member of the audience asked about multithreading and I (without thinking of the consequences) commented that “we can thank Intel for associating the word ‘hyper’ with the number ‘2’.”

I didn’t get invited to a single whisper suite session that year.

HPCwire: Can you share with me two or three interesting things about you that relatively few (or none) of your colleagues or friends know?

Thomas: Attempting to find a human side of me may be a futile endeavor. It may not exist, and I am doubtful that your readers will find anything but my contributions of any interest. However, here goes. One: I love sailing; I used to have a J-105 sloop named “No Compromise.” Two: I am fascinated with the history of Bronze Age cultures and how emerging technologies drive them to ever more complex structures of civilization. Three: I used to enjoy long-distance river kayaking in the Arctic; and I still kayak today, though not to the extent that I used to.

HPCwire: Lastly, what do you consider to be your greatest personal achievement?

Thomas: Not to be trite, but I don’t believe I’ve done it yet. I expect to contribute to the new class of systems capable of Exaflops performance and effective dynamic graph processing for symbolic computing. I believe that such contributions will take the form of the new model of computation such as ParalleX, as a guiding abstraction and its manifestation as a new system software structure and new core architecture for symbiotic operation among billions of executing elements. If I can contribute in some small way to this “6th Phase of HPC,” I will consider that my best personal achievement.

About the Author

An avid HPC watcher and established technology marketing professional; Caroline resides in the California Bay Area and recently joined the HPCwire team as a contributing editor. You can reach her at caroline.connor@longstonegroup.com.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

PRACEdays Reflects Europe’s HPC Commitment

May 25, 2017

More than 250 attendees and participants came together for PRACEdays17 in Barcelona last week, part of the European HPC Summit Week 2017, held May 15-19 at t Read more…

By Tiffany Trader

Russian Researchers Claim First Quantum-Safe Blockchain

May 25, 2017

The Russian Quantum Center today announced it has overcome the threat of quantum cryptography by creating the first quantum-safe blockchain, securing cryptocurr Read more…

By Doug Black

Google Debuts TPU v2 and will Add to Google Cloud

May 25, 2017

Not long after stirring attention in the deep learning/AI community by revealing the details of its Tensor Processing Unit (TPU), Google last week announced the Read more…

By John Russell

Nvidia CEO Predicts AI ‘Cambrian Explosion’

May 25, 2017

The processing power and cloud access to developer tools used to train machine-learning models are making artificial intelligence ubiquitous across computing pl Read more…

By George Leopold

HPE Extreme Performance Solutions

Exploring the Three Models of Remote Visualization

The explosion of data and advancement of digital technologies are dramatically changing the way many companies do business. With the help of high performance computing (HPC) solutions and data analytics platforms, manufacturers are developing products faster, healthcare providers are improving patient care, and energy companies are improving planning, exploration, and production. Read more…

PGAS Use will Rise on New H/W Trends, Says Reinders

May 25, 2017

If you have not already tried using PGAS, it is time to consider adding PGAS to the programming techniques you know. Partitioned Global Array Space, commonly kn Read more…

By James Reinders

Exascale Escapes 2018 Budget Axe; Rest of Science Suffers

May 23, 2017

President Trump's proposed $4.1 trillion FY 2018 budget is good for U.S. exascale computing development, but grim for the rest of science and technology spend Read more…

By Tiffany Trader

Hedge Funds (with Supercomputing help) Rank First Among Investors

May 22, 2017

In case you didn’t know, The Quants Run Wall Street Now, or so says a headline in today’s Wall Street Journal. Quant-run hedge funds now control the largest Read more…

By John Russell

IBM, D-Wave Report Quantum Computing Advances

May 18, 2017

IBM said this week it has built and tested a pair of quantum computing processors, including a prototype of a commercial version. That progress follows an an Read more…

By George Leopold

PRACEdays Reflects Europe’s HPC Commitment

May 25, 2017

More than 250 attendees and participants came together for PRACEdays17 in Barcelona last week, part of the European HPC Summit Week 2017, held May 15-19 at t Read more…

By Tiffany Trader

PGAS Use will Rise on New H/W Trends, Says Reinders

May 25, 2017

If you have not already tried using PGAS, it is time to consider adding PGAS to the programming techniques you know. Partitioned Global Array Space, commonly kn Read more…

By James Reinders

Exascale Escapes 2018 Budget Axe; Rest of Science Suffers

May 23, 2017

President Trump's proposed $4.1 trillion FY 2018 budget is good for U.S. exascale computing development, but grim for the rest of science and technology spend Read more…

By Tiffany Trader

Cray Offers Supercomputing as a Service, Targets Biotechs First

May 16, 2017

Leading supercomputer vendor Cray and datacenter/cloud provider the Markley Group today announced plans to jointly deliver supercomputing as a service. The init Read more…

By John Russell

HPE’s Memory-centric The Machine Coming into View, Opens ARMs to 3rd-party Developers

May 16, 2017

Announced three years ago, HPE’s The Machine is said to be the largest R&D program in the venerable company’s history, one that could be progressing tow Read more…

By Doug Black

What’s Up with Hyperion as It Transitions From IDC?

May 15, 2017

If you’re wondering what’s happening with Hyperion Research – formerly the IDC HPC group – apparently you are not alone, says Steve Conway, now senior V Read more…

By John Russell

Nvidia’s Mammoth Volta GPU Aims High for AI, HPC

May 10, 2017

At Nvidia's GPU Technology Conference (GTC17) in San Jose, Calif., this morning, CEO Jensen Huang announced the company's much-anticipated Volta architecture a Read more…

By Tiffany Trader

HPE Launches Servers, Services, and Collaboration at GTC

May 10, 2017

Hewlett Packard Enterprise (HPE) today launched a new liquid cooled GPU-driven Apollo platform based on SGI ICE architecture, a new collaboration with NVIDIA, a Read more…

By John Russell

Quantum Bits: D-Wave and VW; Google Quantum Lab; IBM Expands Access

March 21, 2017

For a technology that’s usually characterized as far off and in a distant galaxy, quantum computing has been steadily picking up steam. Just how close real-wo Read more…

By John Russell

Trump Budget Targets NIH, DOE, and EPA; No Mention of NSF

March 16, 2017

President Trump’s proposed U.S. fiscal 2018 budget issued today sharply cuts science spending while bolstering military spending as he promised during the cam Read more…

By John Russell

Google Pulls Back the Covers on Its First Machine Learning Chip

April 6, 2017

This week Google released a report detailing the design and performance characteristics of the Tensor Processing Unit (TPU), its custom ASIC for the inference Read more…

By Tiffany Trader

HPC Compiler Company PathScale Seeks Life Raft

March 23, 2017

HPCwire has learned that HPC compiler company PathScale has fallen on difficult times and is asking the community for help or actively seeking a buyer for its a Read more…

By Tiffany Trader

CPU-based Visualization Positions for Exascale Supercomputing

March 16, 2017

Since our first formal product releases of OSPRay and OpenSWR libraries in 2016, CPU-based Software Defined Visualization (SDVis) has achieved wide-spread adopt Read more…

By Jim Jeffers, Principal Engineer and Engineering Leader, Intel

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Last week, Google reported that its custom ASIC Tensor Processing Unit (TPU) was 15-30x faster for inferencing workloads than Nvidia's K80 GPU (see our coverage Read more…

By Tiffany Trader

Nvidia’s Mammoth Volta GPU Aims High for AI, HPC

May 10, 2017

At Nvidia's GPU Technology Conference (GTC17) in San Jose, Calif., this morning, CEO Jensen Huang announced the company's much-anticipated Volta architecture a Read more…

By Tiffany Trader

TSUBAME3.0 Points to Future HPE Pascal-NVLink-OPA Server

February 17, 2017

Since our initial coverage of the TSUBAME3.0 supercomputer yesterday, more details have come to light on this innovative project. Of particular interest is a ne Read more…

By Tiffany Trader

Leading Solution Providers

Facebook Open Sources Caffe2; Nvidia, Intel Rush to Optimize

April 18, 2017

From its F8 developer conference in San Jose, Calif., today, Facebook announced Caffe2, a new open-source, cross-platform framework for deep learning. Caffe2 is Read more…

By Tiffany Trader

Tokyo Tech’s TSUBAME3.0 Will Be First HPE-SGI Super

February 16, 2017

In a press event Friday afternoon local time in Japan, Tokyo Institute of Technology (Tokyo Tech) announced its plans for the TSUBAME3.0 supercomputer, which w Read more…

By Tiffany Trader

Is Liquid Cooling Ready to Go Mainstream?

February 13, 2017

Lost in the frenzy of SC16 was a substantial rise in the number of vendors showing server oriented liquid cooling technologies. Three decades ago liquid cooling Read more…

By Steve Campbell

MIT Mathematician Spins Up 220,000-Core Google Compute Cluster

April 21, 2017

On Thursday, Google announced that MIT math professor and computational number theorist Andrew V. Sutherland had set a record for the largest Google Compute Eng Read more…

By Tiffany Trader

US Supercomputing Leaders Tackle the China Question

March 15, 2017

As China continues to prove its supercomputing mettle via the Top500 list and the forward march of its ambitious plans to stand up an exascale machine by 2020, Read more…

By Tiffany Trader

HPC Technique Propels Deep Learning at Scale

February 21, 2017

Researchers from Baidu's Silicon Valley AI Lab (SVAIL) have adapted a well-known HPC communication technique to boost the speed and scale of their neural networ Read more…

By Tiffany Trader

DOE Supercomputer Achieves Record 45-Qubit Quantum Simulation

April 13, 2017

In order to simulate larger and larger quantum systems and usher in an age of "quantum supremacy," researchers are stretching the limits of today's most advance Read more…

By Tiffany Trader

Knights Landing Processor with Omni-Path Makes Cloud Debut

April 18, 2017

HPC cloud specialist Rescale is partnering with Intel and HPC resource provider R Systems to offer first-ever cloud access to Xeon Phi "Knights Landing" process Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This