HPC Movers and Shakers: Thomas Sterling

By Nicole Hemsoth

October 29, 2010

Ah, New Orleans. The Big Easy. What a great selection for this year’s Supercomputing Conference. It was, in fact, in New Orleans where I first met Thomas Sterling. Thomas, or “Tron” to his friends, graciously invited me to join a small group for dinner one evening during an IEEE conference last summer. We dined at one of the city’s sumptuous restaurants in the Quarter, of course. It was over dinner that warm summer evening that I discovered that this highly respected man, the “father of Beowulf clusters,” has a sharp wit and irrepressible sense of humor that I found absolutely irresistible. There was no doubt in my mind about who my next column would feature as we head to the home of Louisiana State University for SC10.

HPCwire: Thomas, I love your nickname, “Tron.” How did you come by that handle?

Thomas: I had a feeling you were going to bring this up. My nickname Tron goes way back to my Navy days where I was a “tweet”, or aviation electronics technician, repairing F4 Phantom aircraft avionics. When something went really screwy with the electronics, the guys in the shop would blame the “tron god”. Now, I may not have been the most motivated squid in the “nav”, but when there was a really hard problem I was usually the one to tackle it. That’s where “tron” came from; some association with this notional tron god. It’s kind of a compliment, I guess. Later, when serving as an editor on my school paper I used “Tron” as a pen name, and then as my login at MIT, as well as my email address for the inchoate ARPAnet. It’s stayed with me ever since. As Herman Melville might have written, “Call me Tron”.

HPCwire: Speaking of names, you are highly regarded as “the father of Beowulf clusters” and for your research on petaflops computing architecture. I remember that Woody Allen once said you should never take a course where they make you read “Beowulf.” (Laughs) Seriously, though, why did you pick that name for your approach to commodity clusters?

Thomas: (Chuckling) The name was, I should be embarrassed to admit, a complete accident. I was sitting in my office at the Goddard Space Flight Center, and the Program Manager called saying they were sending in the paperwork for my new project and they needed a name for it. I had been putting her off for close to a month. She said she would not hang up until she had a name, or there would not be a project.

I respond well to threats. I needed inspiration and looked around my office in desperation when I noticed at the top of a stack of books my mother’s old copy of Beowulf. I remember saying to the PM, and this is a quote: “Oh hell, just call it ‘Beowulf’; nobody will ever hear of it anyway!” And seriously, that’s how it happened. Someone in the press started calling our Linux clusters “Beowulf-class systems,” so they, whoever they were, get credit for giving the actual clusters that name.

I think there is a lesson here; I’m just not sure what it is.

HPCwire: What’s your stance on shared versus distributed memory? Will we continue to build petascale computers with global shared memory, similar to the legacy products from Sun or SGI, or do you think the programming will be different?

Thomas: This is an important topic and reflects the diversity of experiences that drive perspective, and hence conflict. A major problem is our terminology; our words do not provide us with an effective lexicon to consider all possibilities. For example: “distributed memory.” Does this mean physically separate with intervening distance, blocks of memory not sharing a unified name space, both, or something else? When memory access times are dominated not by the DRAM cycle time but the latency of communication, it is distributed memory. I expect this to be the case for the largest machines of the future. I also expect that hardware support for global address space and unified name spaces are required for efficiency, programmability, and scalability. That sounds like “shared memory.” But now there is that last issue: is it cache coherent? And the answer there is: No, not in the usual sense. But the full explanation to this is too long for a brief interview!

HPCwire: Speaking of which, there are still people out there who long for the days when supercomputers were specialized custom designs and not built out of consumer-grade electronics like Beowulf clusters. What do you say to those people? Will we ever return to using technology specifically crafted for HPC?

Thomas: I am among those who feel that design driven by HPC requirements is essential to advance the field towards Exascale. However, those same changes will be useful for general-purpose and commercial computing as well.

Many ideas first realized in “specialized” HPC designs have migrated into the common general-purpose microprocessor of today. My expectation is that we will continue to use general-purpose devices, but they will change in accordance with the needs of scalability, efficiency, and parallel programmability.

HPCwire: I’ve heard you refer to new “execution models” too. What does that mean? What’s wrong with the current execution models?

Thomas: An execution model is a set of governing principles guiding the co-design and operation of the many interoperable layers of a computing system. It permits the use of the notion of the “decision chain” that recognizes a set of contributing influences. Understanding the decision chain contributes to determining why the operation was performed where and when it was.

Throughout the extraordinary evolution of supercomputing, spanning twelve orders of magnitude in a single lifetime, advancing technologies have required adjustments to the way we organize structures and methods of operation. For instance, a change of balance in bandwidth versus capacity. At least five times we have experienced a revolution in supercomputing. A “6th phase change” is due, and is best represented as a new model of computation.

HPC is in the midst of such a phase change because the technologies are already seen to require different ways of organizing systems, such as multi-core and GPU accelerators. CSP and MPI will not fulfill the needs of all applications on all system classes.

HPCwire: So, you agree with the people who think that MPI is at the end of its rope, and that we need something new, soon. Are you working on alternative programming models?

Thomas: MPI is not near the end of its rope, but we do need something new soon. MPI even in its current form will serve many applications on many systems for many years.

HPCwire: One of your Caltech friends put me up to asking you this one; what do you miss about Caltech?

Thomas: No question, Caltech is a special place, and even after five years I get homesick for it occasionally. There is a mindset there that any fundamental question in science or engineering can be investigated by bright minds to reveal some, if not all, of its secrets. It is the right to strive, to exceed, to understand, that I miss most. Oh, and the strawberry lemonades at the Athenaeum, of course.

HPCwire: So, are there things you can do at LSU that are easier than if you were still at Caltech?

Thomas: Joining the faculty at LSU was a risk, both for LSU and for me! A large state school is a very different environment than boutique intellectual environments such as Caltech, and that concerned me. I had not served as a tenured Professor before and that was a risk for LSU as well. They wanted someone who would rapidly expand their research program in the area of HPC systems with high national exposure. LSU, with support of the state of Louisiana, established the Center for Computation and Technology that complemented the capabilities of the academic departments by providing an advanced environment for interdisciplinary research to foster the goals of both LSU and Louisiana. This has turned out to be a great fit and both LSU and I have benefitted from this new relationship.

HPCwire: What can you share with us about the research you are doing at LSU with “ParalleX”?

Thomas: The research we have undertaken at LSU is risky and driven by the premise that the field of HPC is in that 6th phase change, as discussed above. The ParalleX execution model is a new synthesis of a collection of abstract constructs, relationships, and functional mechanisms to address starvation, latency, overhead, and contention in systems comprising more than a billion simultaneous executing entities with worst-case latencies on the order of a hundred thousand cycles. Recently, the LSU group has teamed with Guang Gao at the University of Delaware, an expert in many related fields, to expand and improve the product of this research under the auspices of the DARPA UHPC Program, the Sandia-led X-Caliber team, and the Intel-led Runnemede team.

HPCwire: This is my ‘live your dream question’: If you could wave a wand and change something about the way HPC is today, what would that thing be?

Thomas: (pause) It basically comes down to having cores designed to operate efficiently in the context of a billion other like cores on a single computational problem, returning us to the notion of a single computer rather than merely a large loose collection of cores using software-managed I/O.

Maybe this does sound like something out of Hogwarts.

HPCwire: I have experienced firsthand your irrepressible sense of humor. What’s the funniest thing you’ve seen in this business?

Thomas: (Laughs) I always get into trouble when I think something is funny but the humor is often lost on others. One time when giving a talk at Los Alamos, I brought up the early energy-efficient computer, “Green Destiny” which, unfortunately, did not perform well, at least initially. I commented: “I don’t get it. Why don’t they just unplug the thing? They’d save even more power and get almost the same performance!” I was never invited back.

At a panel at the Supercomputing conference one year, a member of the audience asked about multithreading and I (without thinking of the consequences) commented that “we can thank Intel for associating the word ‘hyper’ with the number ‘2’.”

I didn’t get invited to a single whisper suite session that year.

HPCwire: Can you share with me two or three interesting things about you that relatively few (or none) of your colleagues or friends know?

Thomas: Attempting to find a human side of me may be a futile endeavor. It may not exist, and I am doubtful that your readers will find anything but my contributions of any interest. However, here goes. One: I love sailing; I used to have a J-105 sloop named “No Compromise.” Two: I am fascinated with the history of Bronze Age cultures and how emerging technologies drive them to ever more complex structures of civilization. Three: I used to enjoy long-distance river kayaking in the Arctic; and I still kayak today, though not to the extent that I used to.

HPCwire: Lastly, what do you consider to be your greatest personal achievement?

Thomas: Not to be trite, but I don’t believe I’ve done it yet. I expect to contribute to the new class of systems capable of Exaflops performance and effective dynamic graph processing for symbolic computing. I believe that such contributions will take the form of the new model of computation such as ParalleX, as a guiding abstraction and its manifestation as a new system software structure and new core architecture for symbiotic operation among billions of executing elements. If I can contribute in some small way to this “6th Phase of HPC,” I will consider that my best personal achievement.

About the Author

An avid HPC watcher and established technology marketing professional; Caroline resides in the California Bay Area and recently joined the HPCwire team as a contributing editor. You can reach her at caroline.connor@longstonegroup.com.

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