Graph 500 Takes Aim at a New Kind of HPC

By Nicole Hemsoth

November 15, 2010

For years Linpack has served as a reasonably useful benchmark for measuring the capability of supercomputers. That’s because high performance computing has traditionally been geared toward solving mathematically-intensive science problems, like 3D physics simulations. Applications in this domain are mostly an exercise in maximizing floating-point performance, and that’s what Linpack is designed to measure. But data-intensive applications are quickly emerging as a significant new class of HPC workloads. For this class of applications, a new kind of supercomputer, and a different way to assess them, will be required.

That is the impetus behind the Graph 500, a set of benchmarks that aim to measure the suitability of systems for data-intensive analytics applications. The nomenclature references graph algorithms, a core component of this class of applications. A Graph 500 group has been assembled to guide the development of these benchmarks, and has come up with a set of reference implementations. Over the past few months the group has been collecting submissions from organizations interested in benchmarking their systems.

The results of these submissions will be the first Graph 500 list, which will be announced at SC10 this year at a Bird of a Feather (BoF) session November 17. The BoF will be led by Sandia National Labs’ Richard Murphy, a computer architect at the lab, who has led some of the early work in getting the Graph 500 off the ground. We got the opportunity to ask Murphy to talk about the benchmarking effort in more detail and what it means for the HPC community.

HPCwire: To begin with, who is funding and supporting this effort?

Richard Murphy: The Graph 500 is a community effort led by Sandia. It has really been a grass-roots activity that began with an exciting dinner conversation at Supercomputing 2009. A core group of us recruited other professional colleagues, and the effort grew into an international steering committee of over 30 people. Each of the organizations represented has donated the time and expertise of the members of the steering committee.

DOE/NNSA has sponsored a small amount of administrative work in putting together putting together the list, helping to generate the reference implementations, etc., but is doing it as a community service. DARPA, NSF, and other agencies are also represented in the steering committee. Indiana University (IU) is providing computing service. IU, Georgia Tech and the University of Southern California Information Sciences Institute (USC/ISI) produced the reference implementations under contract to Sandia, which has been the major expense of the effort thus far.

Several organizations have contributed to refining the benchmarks, and provided technical expertise on deployment. Several of us chipped in a few dollars after the first dinner at SC09 to register the web site

HPCwire: So what exactly does the Graph 500 measure?

Murphy: Strictly speaking, the Graph 500 benchmark provides two computational kernels: first, the construction of an interesting large graph, and second a parallel search of that graph. We measure the execution time of those two pieces, ranked first by the size of the problem solved, then by the time.

More broadly, the goal of the Graph 500 benchmark is to measure the performance of a computer solving a large-scale “informatics” problem. We tend to use the term informatics in the US, but in Europe that’s all of computer science… its more broad than a knowledge discovery problem.

HPCwire: There are quite a few of HPC-type performance metrics out there already, including some that address the data-intensive problem space. What is the motivation behind this one?

Murphy: Most HPC-oriented benchmarks measure performance characteristics that are of traditional importance to the HPC community. While there are other very good data intensive benchmarks, including the DARPA HPCS SSCA#2 benchmark which also performs a graph problem, and more community benchmarks like the Terasort Benchmark for enterprise computing environments, our Graph 500 steering committee was trying to create a benchmark with two goals.

One is a sense of competition by creating a list-based ranking similar to the Top500, which has been tremendously successful at fostering platforms for the HPC community.

The other is a meaningful representation of future informatics applications, with a tie to a broad set of business areas. The hope was that this would be very difficult for conventional architectures, and help drive the community to computers that could better solve large-scale graph problems.

We specify a particular kind of graph because search results change dramatically depending on graph input, so it may be more precise to say that the Graph 500 benchmark is a parallel search over a proscribed graph. In fact, we’ve got six scales of problem — toy, mini, small, medium, large, and huge — and I doubt anybody will be able to solve the huge problem in the first list. We actually added the toy problem based on feedback that all the other scales were significantly challenging on some platforms.

HPCwire: What problem domain is this aimed at?

Murphy: We have identified five major areas in need of this kind of computational kernel: cybersecurity, medical informatics, data enrichment, social networks, and symbolic networks. Many of us on the steering committee believe that these kinds of problems have the potential to eclipse traditional physics-based HPC over the next decade.

Cybersecurity — large enterprises may create 15 billion log entries per day, and require a full table scan with end-to-end joins

Medical Informatics — 50 million patient records, with 20 to 200 records per patient, resulting in billions of individual pieces of information all of which need entity resolution… which records belong to me, you, somebody else, etc.

Data Enrichment — often petascale data sets, a straight forward example being maritime domain awareness with hundreds of millions of individual transponders, tens of thousands of ships, and tens of millions of pieces of individual bulk cargo. These problems also have a lot of different types of input data.

Social Networks — almost unbounded; one example is Facebook.

Symbolic Networks — often petabytes in size, a good example is the human cortex with 25 billion neurons and approximately 7,000 connections each.

As we’ve begun to think about these large data problems, one thing is clear: they are very different from physics problems. Our steering committee has representation from LexisNexis, who as a data company deals with many of these types of data sets as a core part of their business. We’ve also got representation from many of the major computer companies, who see this as an emerging challenge area.

Unlike a typical computation-oriented application, this kind of analysis is often dominated by searching through a large, sparse data set with very simple computational operations. To use the human brain example, each neuron probably only has 50-degrees of freedom or so — 5 or 6 bits of information — but that information is propagated to thousands of additional neurons in a structure with 25 billion neurons overall. A typical 3D physics application, more typified by the TOP500, in the simplest sense communicates along the faces of a cube, which from a data movement standpoint is much easier.

Finally, we hope this will be useful to computer companies. The DARPA Exascale Report concludes that moving data around — not simple computations — will be the dominant energy problem on an exascale machine. Part of the goal of the Graph 500 list is to point out that in addition to the technology making data movement “more expensive”, any shift in the application base from physics to large-scale data problems is likely to further increase the application requirements for data movement. In short, we’re going to have to rethink how we build computers to solve these problems, and the Graph 500 is meant as an early stake in the ground for these application requirements.

HPCwire: Are there specific system architectural features that are especially suited to these types of applications?

Murphy: Performance for these applications is dominated by the ability of the machine to sustain a large number of small, nearly random remote data accesses across its memory system and interconnect, the parallelism available in the machine — more than the performance of a single instruction stream — and the ability for fine-grained synchronization. In some sense, very different requirements from a machine performing a Linpack calculation. In fact, there’s very little compute, other than pointer math and simple comparisons, in this class of applications in general.

HPCwire: Are there any system requirements for a submission? Along those lines, do you expect to attract non-traditional platforms — those that wouldn’t necessarily show up on a TOP500 list?

Murphy: Any system capable of solving the problem is encouraged to compete, and I expect that this ranking may at times look very different from the TOP500 list. Cloud architectures will almost certainly dominate a major chunk of part of the list, and we may find that some exotic architectures dominate the top. I’m curious to see who submits the first time around. The goal in all this is to solve the problem, not require a particular way to solve it. We have released two reference implementations of the benchmark, and hope to have a good cloud reference implementation in the near future.

The only requirements are in the specification we also released, meaning that people are encouraged to target custom environments. We will also happily redistribute custom implementation as reference codes should organizations wish to contribute them.

HPCwire: Do you intend to fold the Graph 500 into any existing benchmark suite?

Murphy: We had a goal this year of producing a very small version of the benchmark for the consideration of the SPEC committee, but missed the deadline. Several of our industry representatives are part of the SPEC committee and will help us create a submission for their consideration the next time the opportunity comes up. We’d very much like to have the benchmark prove its utility. One of the tremendous successes of Linpack in the early days was that Linpack performance corresponded to real application performance for some critical codes. We believe that the Graph 500 benchmark will evolve to demonstrate performance on key codes related to the five business areas listed above.

HPCwire: How do you see the Graph 500 evolving?

Murphy: The Graph 500 steering committee is working to make the tie between data sets in the business areas listed above and the artificial benchmark graphs we generate stronger, which is part of what LexisNexis is helping us to do.

Additionally, we believe there are three key computational kernels: search, the kernel we released this year; optimization, a single source shortest path; and edge oriented, a maximal independent set. We’ve started with one this year to gain some experience in the benchmarking process, and to generate community feedback as we revise the benchmarking process. We envision the first several years of the Graph 500 as a learning process in applications and performance measurement, and plan to release the additional kernels over time.

There are some very difficult questions with those kernels. For example, the edge-oriented kernel we identified is important but amenable to randomized algorithms, and we want to prevent “gaming the benchmark.”

We’re also eager to evolve in the face of community needs. We may have missed an important business area or kernel, and we expect the benchmark to evolve with the application base.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Researchers Scale COSMO Climate Code to 4888 GPUs on Piz Daint

October 17, 2017

Effective global climate simulation, sorely needed to anticipate and cope with global warming, has long been computationally challenging. Two of the major obstacles are the needed resolution and prolonged time to compute Read more…

By John Russell

Student Cluster Competition Coverage New Home

October 16, 2017

Hello computer sports fans! This is the first of many (many!) articles covering the world-wide phenomenon of Student Cluster Competitions. Finally, the Student Cluster Competition coverage has come to its natural home: H Read more…

By Dan Olds

UCSD Web-based Tool Tracking CA Wildfires Generates 1.5M Views

October 16, 2017

Tracking the wildfires raging in northern CA is an unpleasant but necessary part of guiding efforts to fight the fires and safely evacuate affected residents. One such tool – Firemap – is a web-based tool developed b Read more…

By John Russell

HPE Extreme Performance Solutions

Transforming Genomic Analytics with HPC-Accelerated Insights

Advancements in the field of genomics are revolutionizing our understanding of human biology, rapidly accelerating the discovery and treatment of genetic diseases, and dramatically improving human health. Read more…

Exascale Imperative: New Movie from HPE Makes a Compelling Case

October 13, 2017

Why is pursuing exascale computing so important? In a new video – Hewlett Packard Enterprise: Eighteen Zeros – four HPE executives, a prominent national lab HPC researcher, and HPCwire managing editor Tiffany Trader Read more…

By John Russell

Student Cluster Competition Coverage New Home

October 16, 2017

Hello computer sports fans! This is the first of many (many!) articles covering the world-wide phenomenon of Student Cluster Competitions. Finally, the Student Read more…

By Dan Olds

Intel Delivers 17-Qubit Quantum Chip to European Research Partner

October 10, 2017

On Tuesday, Intel delivered a 17-qubit superconducting test chip to research partner QuTech, the quantum research institute of Delft University of Technology (TU Delft) in the Netherlands. The announcement marks a major milestone in the 10-year, $50-million collaborative relationship with TU Delft and TNO, the Dutch Organization for Applied Research, to accelerate advancements in quantum computing. Read more…

By Tiffany Trader

Fujitsu Tapped to Build 37-Petaflops ABCI System for AIST

October 10, 2017

Fujitsu announced today it will build the long-planned AI Bridging Cloud Infrastructure (ABCI) which is set to become the fastest supercomputer system in Japan Read more…

By John Russell

HPC Chips – A Veritable Smorgasbord?

October 10, 2017

For the first time since AMD's ill-fated launch of Bulldozer the answer to the question, 'Which CPU will be in my next HPC system?' doesn't have to be 'Whichever variety of Intel Xeon E5 they are selling when we procure'. Read more…

By Dairsie Latimer

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Intel Debuts Programmable Acceleration Card

October 5, 2017

With a view toward supporting complex, data-intensive applications, such as AI inference, video streaming analytics, database acceleration and genomics, Intel i Read more…

By Doug Black

OLCF’s 200 Petaflops Summit Machine Still Slated for 2018 Start-up

October 3, 2017

The Department of Energy’s planned 200 petaflops Summit computer, which is currently being installed at Oak Ridge Leadership Computing Facility, is on track t Read more…

By John Russell

US Exascale Program – Some Additional Clarity

September 28, 2017

The last time we left the Department of Energy’s exascale computing program in July, things were looking very positive. Both the U.S. House and Senate had pas Read more…

By Alex R. Larzelere

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

NERSC Scales Scientific Deep Learning to 15 Petaflops

August 28, 2017

A collaborative effort between Intel, NERSC and Stanford has delivered the first 15-petaflops deep learning software running on HPC platforms and is, according Read more…

By Rob Farber

Oracle Layoffs Reportedly Hit SPARC and Solaris Hard

September 7, 2017

Oracle’s latest layoffs have many wondering if this is the end of the line for the SPARC processor and Solaris OS development. As reported by multiple sources Read more…

By John Russell

US Coalesces Plans for First Exascale Supercomputer: Aurora in 2021

September 27, 2017

At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, in Arlington, Va., yesterday (Sept. 26), it was revealed that the "Aurora" supercompute Read more…

By Tiffany Trader

Google Releases Deeplearn.js to Further Democratize Machine Learning

August 17, 2017

Spreading the use of machine learning tools is one of the goals of Google’s PAIR (People + AI Research) initiative, which was introduced in early July. Last w Read more…

By John Russell

GlobalFoundries Puts Wind in AMD’s Sails with 12nm FinFET

September 24, 2017

From its annual tech conference last week (Sept. 20), where GlobalFoundries welcomed more than 600 semiconductor professionals (reaching the Santa Clara venue Read more…

By Tiffany Trader

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in Read more…

By Tiffany Trader

Leading Solution Providers

Amazon Debuts New AMD-based GPU Instances for Graphics Acceleration

September 12, 2017

Last week Amazon Web Services (AWS) streaming service, AppStream 2.0, introduced a new GPU instance called Graphics Design intended to accelerate graphics. The Read more…

By John Russell

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

EU Funds 20 Million Euro ARM+FPGA Exascale Project

September 7, 2017

At the Barcelona Supercomputer Centre on Wednesday (Sept. 6), 16 partners gathered to launch the EuroEXA project, which invests €20 million over three-and-a-half years into exascale-focused research and development. Led by the Horizon 2020 program, EuroEXA picks up the banner of a triad of partner projects — ExaNeSt, EcoScale and ExaNoDe — building on their work... Read more…

By Tiffany Trader

Cray Moves to Acquire the Seagate ClusterStor Line

July 28, 2017

This week Cray announced that it is picking up Seagate's ClusterStor HPC storage array business for an undisclosed sum. "In short we're effectively transitioning the bulk of the ClusterStor product line to Cray," said CEO Peter Ungaro. Read more…

By Tiffany Trader

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Intel Launches Software Tools to Ease FPGA Programming

September 5, 2017

Field Programmable Gate Arrays (FPGAs) have a reputation for being difficult to program, requiring expertise in specialty languages, like Verilog or VHDL. Easin Read more…

By Tiffany Trader

IBM Advances Web-based Quantum Programming

September 5, 2017

IBM Research is pairing its Jupyter-based Data Science Experience notebook environment with its cloud-based quantum computer, IBM Q, in hopes of encouraging a new class of entrepreneurial user to solve intractable problems that even exceed the capabilities of the best AI systems. Read more…

By Alex Woodie

Intel, NERSC and University Partners Launch New Big Data Center

August 17, 2017

A collaboration between the Department of Energy’s National Energy Research Scientific Computing Center (NERSC), Intel and five Intel Parallel Computing Cente Read more…

By Linda Barney

  • arrow
  • Click Here for More Headlines
  • arrow
Share This