The Expanding Floating-Point Performance Gap Between FPGAs and Microprocessors

By Dave Strenski, Cray; Prasanna Sundararajan, Xilinx; and Ralph Wittig, Xilinx

November 22, 2010

For the past several years, Field Programmable Gate Arrays (FPGAs) have been getting large enough to compete with microprocessors in floating-point performance. Using the theoretical peak performance numbers, the FPGA’s floating-point performance is growing faster than microprocessors. This article calculates the peak performance for several FPGA devices from Xilinx and compares them to a reference microprocessor for equivalent time periods and shows that this gap in performance is growing. More realistic predicted performance numbers are also calculated for these devices and those results show equivalent trends.


Three years ago an article was published in HPCwire showing a method for comparing the peak performance of 64 bit floating-point calculations between FPGAs and a microprocessor. The article showed that the theoretical peak performance of the Virtex-4 LX200 was about 50 percent better than the then current dual-core processor. A follow-up article in HPCwire in 2008 refined these calculations, adding more detail to account for placement and routing issues in the FPGAs and using the latest release of the floating-point cores from Xilinx. These refined calculations compared three Virtex-5 FPGA devices against the then current quad-core microprocessor. That article showed that not only were the newer FPGAs faster than the quad-core processor, but that the gap in performance was getting larger. In 2009, six-core microprocessors were released and Xilinx released several new Virtex-6 FPGA devices. Recalculating the performance of all these devices shows that this gap in performance between the FPGAs and microprocessors continues to grow.

Recall that FPGAs are made up of an interconnecting fabric that are populated with Look Up Tables (LUTs), Flip-Flops (FFs), Configurable Logic Blocks (CLBs), Block RAM memory (BRAM), Digital Signal Processing (DSP) blocks, and other specialized features for performing I/O on these devices. On the Virtex-4 FPGAs, LUTs and FFs were arranged on the device with two LUTs and two FFs per logic slice and the DSPs were 18×18-bit multiply/accumulate units. The Virtex-4 BRAMs are18-bits wide. On the Virtex-5 FPGAs, LUTs and FFs are arranged in logic slices with four LUTs and four FFs per logic slice, DSPs are 25×18-bit multiply/accumulate and the BRAM is a mix of 18-bits and 36-bits wide. The Virtex-6 logic slices are now four LUTs and eight FFs making this the first time logic slices that are asymmetric with more FFs then LUTs. The DSP units remain 25×18-bit multiply/accumulate units. Finally, the BRAM is fundamentally 36-bits wide.

Beginning with the Virtex-4, Xilinx started making LX, SX, and FX versions of the FPGAs, with the LX maximizing the amount of logic slices and the SX maximizing the amount of DSP slices. This continues with the Virtex-5 and Virtex-6 devices. This article will use the Virtex-4 LX160 and LX200 [PDF], Virtex-5 LX330T, SX95T, and SX240T [PDF], and the Virtex-6 LX240T, LX550T, LX760, and SX475T [PDF] FPGA devices and a reference dual-core, quad-core, and six-core microprocessor.

As with the previous papers on this topic, theoretical peak performance will be calculated for all the devices. While peak performances can be seen as artificial, they are easy to understand and do show qualitative trends. More predicted performances will also be calculated to show a more quantitative comparison. The predicted performances actually gives an advantage to the FPGAs since the interface code size remains constant while the devices get bigger, giving proportionally more space for the user’s logic.

An interesting side bar about this project is the code used to calculate the peak performances on the FPGAs. The calculations look at all possible combination of the six function units (two types of adders and four types of multipliers) that will fit on the device. The maximum search space is then defined as the maximum number of adders of type one, times the maximum number of adders of type two, times the maximum number of multipliers of type one, times the maximum number of multipliers of type two, etc., for all six types of function units. For the Virtex-4, this search space ranged from 10^8 to 10^13 possible combinations which were reasonable for an exhaustive search. The Virtex-5 FPGAs are larger and the search space went from 10^10 to 10^17 possible combinations depending on the type of FPGA device being studied. Adding to the growing search space is the number of devices to test with two Virtex-4 devices, three Virtex-5 devices, and now four Virtex-6 devices. This required rethinking of the exhaustive search and reducing the search space by ignoring sub-domains that will not fit on the device. The Virtex-6 pushed the search space even higher, from 10^12 to 10^19 possible combinations. The code needed a complete rewrite to add a restart capability, parallelization, and a step function that allow for a near-exhaustive search.

Calculating Peak Performance
Peak 64-bits

Peak 32-bits

Peak 24-bitsThe first task is to define a reference microprocessor. Both Intel and AMD have been making microprocessors for many years — both company’s microprocessors tend to leapfrog each other every year in performance — making it difficult to make a general statement about which processor is the fastest at a given point in time. AMD’s line of Opteron microprocessors: Santa Ana, Barcelona, and Istanbul are more or less equivalent to Intel’s Xeon microprocessor line: Woodcrest, Harpertown, and Nehalem. The peak performance used for the reference microprocessors in this article will be defined by a number of floating-point results per clock, times the number of cores, times the clock frequency. For the dual-core microprocessor, we used 2 flops/clock and for the quad-core and six-core, we used 4 flops/clock. This gives a peak performance for the dual-core of (2 flops/clock * 2 cores * 2.5 GHz) 10 Gflop/s, the quad-core of (4 flops/clock * 4 cores * 2.5 GHz) 40 Gflop/s, and the six-core of (4 flops/clock * 6 cores * 2.5 GHz) 60 Gflop/s for 64-bit floating-point results. The calculations are using the same clock frequency of 2.5 GHz for the microprocessors for easier comparisons. In reality, the clock frequency has been dropping as the core count goes up due to power constraints. For 32-bit and 24-bit results, these numbers can be doubled.

For FPGAs this peak can be represented as the available logic on the device, divided by the amount of logic needed to build a function unit, times the maximum clock frequency at which those function units will run. Calculating these peaks for FPGAs is more complicated since one can implement different ratios of add and multiply function units and use different ratios of logic and DSP resources. The microprocessors also only have one peak performance representing an equal ratio of additions and multiplications every clock cycle, whereas the FPGAs can have many peak performances.

Calculating the peak performance for FPGAs gets even more complicated since not only are there multiple devices, multiple ratios of additions and multiplications, but also because Xilinx supplies a set of floating-point cores to build function units, and these cores are improving over time. “Floating-point Operators v3.0” (Xilinx document DS335) was first published in September of 2006. Version 4.0 of the same document was published in April 2008, and the latest version was published in June of 2009 [PDF]. As with compilers for microprocessors, each new floating-point core reduces its size and increases its performance. All the results shown here were performed with the latest floating-point operators, so the performance numbers of Virtex-4 and Virtex-5 may differ from results in previous articles.

The graphs above show the peak performance of the FPGAs as compared to the reference microprocessors. For the FPGA results, the peak performance was calculated for several devices of the same family and the best result plotted. The red line is the FPGA performance while forcing an even ratio of addition and multiplication function units on the device. These would give a fair comparison to the peak performance of the microprocessors since their best performance comes from having an equal number of additions to multiplications. The green line shows the peak performance of the FPGA devices by removing this restriction and finding the optimal mix of function units for the best possible peak performance. Clearly from a peak performance point of view the FPGAs are outpacing microprocessors. This can be explained by thinking about what happens inside the devices as they grow. For the microprocessor the whole computing core is replicated. While this adds another set of function units, it also adds all the overhead needed to manage those functions, whether they are used in the calculation or not. On the FPGA side, adding more space on the device allows the programmer to add more function units that are used in the calculation. This makes the percentage of the device doing useful calculations higher then on the microprocessor.

Calculating Predicted Performance
Predicted 64-bits

Predicted 32-bits

Predicted 24-bitsThe same calculations were performed to calculate a more predicted performance for both the microprocessors and the FPGAs. Looking at results from the HPL benchmark, microprocessors typically get 80 percent to 90 percent for the peak performance running this benchmark. While this benchmark is somewhat artificial compared to what an application might get, it is useful in showing the performance of a calculation actually running on the device. For the results presented here, 85 percent of the peak performance was used as the predicted performance for the microprocessors.

While an actual calculation has not yet been synthesized and implemented on the FPGAs, working with Xilinx engineers, the predicted performance has been calculated by using a reduced clock frequency of 15 percent and a reduced amount of available logic, by first removing 20,000 LUTs and 20,000 FFs for an I/O interface and an additional 15 percent reduction for placement and routing.

The graphs to the left show the same trends. The FPGAs are growing in performance faster than microprocessors. This trend gets even bigger when non-standard floating-point operations are considered. Note how the 24-bit floating-point performance continues to grow over 32-bit floating-point performance on the FPGAs. This is because an FPGA does not have a fixed word size and can reconfigure the logic into exactly what it needs for the calculation. Microprocessors on the other hand can only do 64-bit or 32-bit floating-point operations, and these graphs are simply repeating the 32-bit results for the 24-bit calculations. If you extend this to applications that work on the bit level, like compression/decompression, searches, and encryption/decryption, FPGAs have shown two orders of magnitude better performance.

While FPGA performance is growing, the ease to program them has not. Programming an FPGA still requires a highly skilled programmer/engineer to develop the code for the device. However, once developed standard C/Fortran applications can call them as specialized subroutines. This difficulty in code development is due to the programmability of the device. The programmer needs to create the function units needed for the calculation and also all the caching and memory operations. While this allows for a calculation to take full advantage of every bit of circuitry available on the device, it makes them much harder to program.

It should also be noted that these graphs are considering the devices themselves and are not taking into account the amount of time needed to export data, if needed, to a separate device. Typically an FPGA is used as an accelerator attached to a microprocessor, thus any speedup achieved by the attached accelerator needs to be reduced by the amount of time needed to move the data from the microprocessor to/from the accelerator or the calculations and communications needs to be overlapped. The graphs also do not consider the effects of using local memory during the calculations.

To better understand the raw computing performance of the FPGA, consider the latest SX475T with 74,400 logic slices and four LUTs per slice, giving it a total of 297,000 LUTs. Recall that a LUT is a “Look Up Table” with two outputs per LUT. A logic slice also has many Flip-Flops, but those are used to split a signal for routing and do not contribute to an operation. This gives the device, running at a conservative speed of 250 MHz, 2.32 trillion 64-bit op/s (297,600 LUTs * 2 bit operators per LUT * 250 MHz * 1/64). A six-core microprocessor running at 2.5 GHz would have 60 billion 64-bit op/s (6 cores * 4 ops per clock * 2500 MHz). This gives the FPGA 38.7 times more raw computing power.

Clearly, microprocessors are hitting their limit in serial processing and programmers are now forced to make their codes more parallel on multi-core microprocessors. Other options programmers have are to look at accelerators such as FPGAs, GPUs, or other specialized hardware. Any of these accelerators need a new development environment to write the code. For the FPGA, the development tools continue to improve as well as the IP cores used as the basic building blocks of these new accelerator algorithms. Most of all, FPGAs typically run at about a 10x slower clock rate which makes them use about a third to a quarter of the power as a typical microprocessor. As the number of devices needed to reach a petaflop grows, having these low power accelerators helps HPC systems fit within a reasonable power envelope.

Xilinx has now released the Virtex-7 [PDF] and new microprocessors are available, so it is time to start another set of comparison calculations.

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