Intel Charts Its Multicore and Manycore Future for HPC

By Michael Feldman

December 1, 2010

A lot of discussion at this year’s Supercomputing Conference was devoted to manycore architectures and exascale computing — two topics which seem to go hand-in-hand. But as the community hurtles toward the exaflop milestone, it has become clear that the natural evolution of multicore x86 CPUs won’t get the industry very far toward that goal. Manycore GPGPUs, on the other hand, do appear to be a viable path to exascale computing. So where does that leave GPU-less Intel?

In a nutshell, Intel’s answer to GPGPUs is its new Many Integrated Core (MIC) architecture. MIC, which was unveiled at the International Supercomputing Conference (ISC’10) this summer in Germany, is the recycled Larrabee technology that Intel originally developed for the high end graphics and visualization markets. When it became clear that effort wouldn’t yield a competitive alternative to the established GPUs from NVIDIA and AMD, Intel scrapped the project and recast the technology as an HPC accelerator.

To dig a little deeper into Intel’s HPC strategy, HPCwire spoke with Rajeeb Hazra, the general manager for the High Performance Computing group at Intel. A 15-year veteran of Intel, Hazra took over the HPC GM position from Richard Dracott in July of this year. Prior to that, Hazra was the director of the Supercomputing Architecture and Planning (SAP) group, which focuses on designing architectures for the highest end platforms, that is, petaflop and exaflop computing.

His experience in the supercomputing group was fortuitous, given that Intel’s biggest challenge in the server market is likely to be delivering products for the elite end of high performance computing. Today Intel is the dominant processor supplier for all HPC platforms, from top 10 supercomputers, to clusters, and down to high performance clients. The plan is to continue to do so. “Our objective is to bring to the high performance computing marketplace innovations that drive essentially all of HPC, from the very high end of supercomputing to volume workstations,” Hazra told HPCwire.

Intel’s MIC architecture stands to be a big part of that. Hazra says it will be the basis for its manycore processor design for the next decade and beyond. But first they have to hit a moving target. The rapid ascension of general-purpose GPUs into high performance computing over the last three years has given NVIDIA, and to a lesser extent AMD, a formidable head start.

As of October, the fastest supercomputer in the world, the Tianhe-1A, is a GPU-CPU hybrid. That machine delivers 2.5 petaflops on Linpack, with the vast majority of those FLOPS being supplied by the GPUs. There are a handful of other top 100 GPU-powered supercomputers, and more are on the way. If Intel doesn’t have a viable alternative to the GPGPU juggernaut, its chips will be relegated to the role of supporting player in a lot of future supercomputers, not to mention mainstream clusters and high performance workstations.

Although MIC is a modified x86 implementation and is a completely different architecture from GPGPUs, it is aimed to solve the same problem — namely to get a lot of floating point performance in a very energy efficient package. (For a detailed comparison between MIC and the latest generation Fermi GPU, see Michael Wolfe’s in-depth analysis.) It is also intended to be used in the same manner as a GPU, namely as a floating point accelerator connected to a conventional x86 processor. The common thread is that both architectures are using a high degree of parallelism and simple cores to extract a lot of performance per watt.

That’s a valuable attribute for any HPC platform, but it’s critical for the next generation of multi-petaflop supercomputers. Hazra notes the performance increase in the top 100 supercomputers over the last 10 years was achieved mainly via the scale-out model, that is, adding more processors and more nodes. New CPU architectures changed the slope of the performance per watt curve somewhat, but systems have generally gotten larger, thus consuming more power.

That can’t continue for more than a few more years. It’s not practical to build a 500 petaflop system that consumes 300 megawatts. The conventional wisdom suggests power is going to capped at something between 20 and 40 megawatts for a single machine. So you can’t just ride the performance curve of existing Xeons or Opterons and expect to deliver the required performance for these future systems. “As we look out over the next five to ten years, those systems have some fundamental inflection points,” concedes Hazra.

While Intel intends to deliver the performance per watt similar to that of a GPGPU, it will do so in an x86 framework. Hazra says that will allow applications to transition from single-threaded codes to highly-parallel codes without changing the underlying model. Intel will supply compiler and runtime software support for the product, and if it becomes a commercial success, other vendors, no doubt, will add their products as well. Intel will also provide a common set of development tools to be used across the Xeon and MIC products, such that differences between the two architectures are encapsulated within tools. The goal is to be able to recompile any x86 source and have it automatically spit out MIC instructions.

The idea, of course, is to maximize programmer productivity — and not just for new codes, but also for legacy codes that represent years or even decades of investment. Intel does seem to have an advantage here. Although a Xeon-MIC combo is still a heterogeneous platform, it will be a lot more homogeneous, at least from an instruction set point of view, than say a Xeon-GPGPU platform. Hazra believes that the path they are pursuing with the x86 Intel architecture on both sides will allow them to provide a more balanced heterogeneous system. If Intel can truly deliver a minimally-painful software transition from multicore Xeons to manycore MICs, they will have a compelling HPC accelerator offering. “We believe the MIC architecture will become the workhorse as more and more applications and algorithms are able to take advantage of parallelism,” said Hazra.

The first MIC product, codenamed “Knights Corner,” is to be built with the chipmaker’s 22nm process technology. Given that the 22nm fabs will most likely be used for higher volume chips to start, we probably won’t see the first MIC until sometime in 2012. Knights Corner is supposed to be a 50-core chip, but Intel has not as yet supplied any estimated performance metrics.

Meanwhile, the chipmaker will continue to develop its multicore Xeon line that spans the enterprise and “volume” HPC market. Not every HPC application is going to need manycore acceleration, and for those codes that are more aligned with coarse-grained parallelism or are especially geared toward single-threaded performance, Xeons will be the chip of choice.

The Xeon line will continue to be developed using Intel’s 12-month tick-tock cadence — a process shrink followed by a microarchitecture update — used for its mainstream x86 processors. According to Hazra, though, the MIC cadence will be slower, more like a 18-24 month cadence, although in this case each processor update could encapsulate more significant architectural changes. This schedule aligns closely with the pace NVIDIA and AMD have set with their GPGPU offerings, and is pretty much what one would expect for a relatively low-volume accelerator.

The big unknown is if Intel can deliver the goods in time to reverse the GPGPU momentum. NVIDIA and AMD have a three-year head start, which will be extended to five years by the time the first commercial MIC chips hit the streets. Intel as a company doesn’t need to rely on the success of this manycore product for its success, but its HPC aspirations seem to be tied to it. 2012 is shaping up to be an interesting year.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

GDPR’s Impact on Scientific Research Uncertain

May 24, 2018

Amid the angst over preparations—or lack thereof—for new European Union data protections entering into force at week’s end is the equally worrisome issue of the rules’ impact on scientific research. Among the Read more…

By George Leopold

Intel Pledges First Commercial Nervana Product ‘Spring Crest’ in 2019

May 24, 2018

At its AI developer conference in San Francisco yesterday, Intel embraced a holistic approach to AI and showed off a broad AI portfolio that includes Xeon processors, Movidius technologies, FPGAs and Intel’s Nervana Neural Network Processors (NNPs), based on the technology it acquired in 2016. Read more…

By Tiffany Trader

Pattern Computer – Startup Claims Breakthrough in ‘Pattern Discovery’ Technology

May 23, 2018

If it weren’t for the heavy-hitter technology team behind start-up Pattern Computer, which emerged from stealth today in a live-streamed event from San Francisco, one would be tempted to dismiss its claims of inventing Read more…

By John Russell

HPE Extreme Performance Solutions

HPC and AI Convergence is Accelerating New Levels of Intelligence

Data analytics is the most valuable tool in the digital marketplace – so much so that organizations are employing high performance computing (HPC) capabilities to rapidly collect, share, and analyze endless streams of data. Read more…

IBM Accelerated Insights

Mastering the Big Data Challenge in Cognitive Healthcare

Patrick Chain, genomics researcher at Los Alamos National Laboratory, posed a question in a recent blog: What if a nurse could swipe a patient’s saliva and run a quick genetic test to determine if the patient’s sore throat was caused by a cold virus or a bacterial infection? Read more…

Silicon Startup Raises ‘Prodigy’ for Hyperscale/AI Workloads

May 23, 2018

There's another silicon startup coming onto the HPC/hyperscale scene with some intriguing and bold claims. Silicon Valley-based Tachyum Inc., which has been emerging from stealth over the last year and a half, is unveili Read more…

By Tiffany Trader

Intel Pledges First Commercial Nervana Product ‘Spring Crest’ in 2019

May 24, 2018

At its AI developer conference in San Francisco yesterday, Intel embraced a holistic approach to AI and showed off a broad AI portfolio that includes Xeon processors, Movidius technologies, FPGAs and Intel’s Nervana Neural Network Processors (NNPs), based on the technology it acquired in 2016. Read more…

By Tiffany Trader

Pattern Computer – Startup Claims Breakthrough in ‘Pattern Discovery’ Technology

May 23, 2018

If it weren’t for the heavy-hitter technology team behind start-up Pattern Computer, which emerged from stealth today in a live-streamed event from San Franci Read more…

By John Russell

Silicon Startup Raises ‘Prodigy’ for Hyperscale/AI Workloads

May 23, 2018

There's another silicon startup coming onto the HPC/hyperscale scene with some intriguing and bold claims. Silicon Valley-based Tachyum Inc., which has been eme Read more…

By Tiffany Trader

Japan Meteorological Agency Takes Delivery of Pair of Crays

May 21, 2018

Cray has supplied two identical Cray XC50 supercomputers to the Japan Meteorological Agency (JMA) in northwestern Tokyo. Boasting more than 18 petaflops combine Read more…

By Tiffany Trader

ASC18: Final Results Revealed & Wrapped Up

May 17, 2018

It was an exciting week at ASC18 in Nanyang, China. The student teams braved extreme heat, extremely difficult applications, and extreme competition in order to cross the cluster competition finish line. The gala awards ceremony took place on Wednesday. The auditorium was packed with student teams, various dignitaries, the media, and other interested parties. So what happened? Read more…

By Dan Olds

Spring Meetings Underscore Quantum Computing’s Rise

May 17, 2018

The month of April 2018 saw four very important and interesting meetings to discuss the state of quantum computing technologies, their potential impacts, and th Read more…

By Alex R. Larzelere

Quantum Network Hub Opens in Japan

May 17, 2018

Following on the launch of its Q Commercial quantum network last December with 12 industrial and academic partners, the official Japanese hub at Keio University is now open to facilitate the exploration of quantum applications important to science and business. The news comes a week after IBM announced that North Carolina State University was the first U.S. university to join its Q Network. Read more…

By Tiffany Trader

Democratizing HPC: OSC Releases Version 1.3 of OnDemand

May 16, 2018

Making HPC resources readily available and easier to use for scientists who may have less HPC expertise is an ongoing challenge. Open OnDemand is a project by t Read more…

By John Russell

MLPerf – Will New Machine Learning Benchmark Help Propel AI Forward?

May 2, 2018

Let the AI benchmarking wars begin. Today, a diverse group from academia and industry – Google, Baidu, Intel, AMD, Harvard, and Stanford among them – releas Read more…

By John Russell

How the Cloud Is Falling Short for HPC

March 15, 2018

The last couple of years have seen cloud computing gradually build some legitimacy within the HPC world, but still the HPC industry lies far behind enterprise I Read more…

By Chris Downing

Russian Nuclear Engineers Caught Cryptomining on Lab Supercomputer

February 12, 2018

Nuclear scientists working at the All-Russian Research Institute of Experimental Physics (RFNC-VNIIEF) have been arrested for using lab supercomputing resources to mine crypto-currency, according to a report in Russia’s Interfax News Agency. Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Deep Learning at 15 PFlops Enables Training for Extreme Weather Identification at Scale

March 19, 2018

Petaflop per second deep learning training performance on the NERSC (National Energy Research Scientific Computing Center) Cori supercomputer has given climate Read more…

By Rob Farber

AI Cloud Competition Heats Up: Google’s TPUs, Amazon Building AI Chip

February 12, 2018

Competition in the white hot AI (and public cloud) market pits Google against Amazon this week, with Google offering AI hardware on its cloud platform intended Read more…

By Doug Black

US Plans $1.8 Billion Spend on DOE Exascale Supercomputing

April 11, 2018

On Monday, the United States Department of Energy announced its intention to procure up to three exascale supercomputers at a cost of up to $1.8 billion with th Read more…

By Tiffany Trader

Lenovo Unveils Warm Water Cooled ThinkSystem SD650 in Rampup to LRZ Install

February 22, 2018

This week Lenovo took the wraps off the ThinkSystem SD650 high-density server with third-generation direct water cooling technology developed in tandem with par Read more…

By Tiffany Trader

Leading Solution Providers

SC17 Booth Video Tours Playlist

Altair @ SC17


AMD @ SC17


ASRock Rack @ SC17

ASRock Rack



DDN Storage @ SC17

DDN Storage

Huawei @ SC17


IBM @ SC17


IBM Power Systems @ SC17

IBM Power Systems

Intel @ SC17


Lenovo @ SC17


Mellanox Technologies @ SC17

Mellanox Technologies

Microsoft @ SC17


Penguin Computing @ SC17

Penguin Computing

Pure Storage @ SC17

Pure Storage

Supericro @ SC17


Tyan @ SC17


Univa @ SC17


Google Chases Quantum Supremacy with 72-Qubit Processor

March 7, 2018

Google pulled ahead of the pack this week in the race toward "quantum supremacy," with the introduction of a new 72-qubit quantum processor called Bristlecone. Read more…

By Tiffany Trader

CFO Steps down in Executive Shuffle at Supermicro

January 31, 2018

Supermicro yesterday announced senior management shuffling including prominent departures, the completion of an audit linked to its delayed Nasdaq filings, and Read more…

By John Russell

HPE Wins $57 Million DoD Supercomputing Contract

February 20, 2018

Hewlett Packard Enterprise (HPE) today revealed details of its massive $57 million HPC contract with the U.S. Department of Defense (DoD). The deal calls for HP Read more…

By Tiffany Trader

Deep Learning Portends ‘Sea Change’ for Oil and Gas Sector

February 1, 2018

The billowing compute and data demands that spurred the oil and gas industry to be the largest commercial users of high-performance computing are now propelling Read more…

By Tiffany Trader

Nvidia Ups Hardware Game with 16-GPU DGX-2 Server and 18-Port NVSwitch

March 27, 2018

Nvidia unveiled a raft of new products from its annual technology conference in San Jose today, and despite not offering up a new chip architecture, there were still a few surprises in store for HPC hardware aficionados. Read more…

By Tiffany Trader

Hennessy & Patterson: A New Golden Age for Computer Architecture

April 17, 2018

On Monday June 4, 2018, 2017 A.M. Turing Award Winners John L. Hennessy and David A. Patterson will deliver the Turing Lecture at the 45th International Sympo Read more…

By Staff

HPC and AI – Two Communities Same Future

January 25, 2018

According to Al Gara (Intel Fellow, Data Center Group), high performance computing and artificial intelligence will increasingly intertwine as we transition to Read more…

By Rob Farber

Part One: Deep Dive into 2018 Trends in Life Sciences HPC

March 1, 2018

Life sciences is an interesting lens through which to see HPC. It is perhaps not an obvious choice, given life sciences’ relative newness as a heavy user of H Read more…

By John Russell

  • arrow
  • Click Here for More Headlines
  • arrow
Share This