Intel Charts Its Multicore and Manycore Future for HPC

By Michael Feldman

December 1, 2010

A lot of discussion at this year’s Supercomputing Conference was devoted to manycore architectures and exascale computing — two topics which seem to go hand-in-hand. But as the community hurtles toward the exaflop milestone, it has become clear that the natural evolution of multicore x86 CPUs won’t get the industry very far toward that goal. Manycore GPGPUs, on the other hand, do appear to be a viable path to exascale computing. So where does that leave GPU-less Intel?

In a nutshell, Intel’s answer to GPGPUs is its new Many Integrated Core (MIC) architecture. MIC, which was unveiled at the International Supercomputing Conference (ISC’10) this summer in Germany, is the recycled Larrabee technology that Intel originally developed for the high end graphics and visualization markets. When it became clear that effort wouldn’t yield a competitive alternative to the established GPUs from NVIDIA and AMD, Intel scrapped the project and recast the technology as an HPC accelerator.

To dig a little deeper into Intel’s HPC strategy, HPCwire spoke with Rajeeb Hazra, the general manager for the High Performance Computing group at Intel. A 15-year veteran of Intel, Hazra took over the HPC GM position from Richard Dracott in July of this year. Prior to that, Hazra was the director of the Supercomputing Architecture and Planning (SAP) group, which focuses on designing architectures for the highest end platforms, that is, petaflop and exaflop computing.

His experience in the supercomputing group was fortuitous, given that Intel’s biggest challenge in the server market is likely to be delivering products for the elite end of high performance computing. Today Intel is the dominant processor supplier for all HPC platforms, from top 10 supercomputers, to clusters, and down to high performance clients. The plan is to continue to do so. “Our objective is to bring to the high performance computing marketplace innovations that drive essentially all of HPC, from the very high end of supercomputing to volume workstations,” Hazra told HPCwire.

Intel’s MIC architecture stands to be a big part of that. Hazra says it will be the basis for its manycore processor design for the next decade and beyond. But first they have to hit a moving target. The rapid ascension of general-purpose GPUs into high performance computing over the last three years has given NVIDIA, and to a lesser extent AMD, a formidable head start.

As of October, the fastest supercomputer in the world, the Tianhe-1A, is a GPU-CPU hybrid. That machine delivers 2.5 petaflops on Linpack, with the vast majority of those FLOPS being supplied by the GPUs. There are a handful of other top 100 GPU-powered supercomputers, and more are on the way. If Intel doesn’t have a viable alternative to the GPGPU juggernaut, its chips will be relegated to the role of supporting player in a lot of future supercomputers, not to mention mainstream clusters and high performance workstations.

Although MIC is a modified x86 implementation and is a completely different architecture from GPGPUs, it is aimed to solve the same problem — namely to get a lot of floating point performance in a very energy efficient package. (For a detailed comparison between MIC and the latest generation Fermi GPU, see Michael Wolfe’s in-depth analysis.) It is also intended to be used in the same manner as a GPU, namely as a floating point accelerator connected to a conventional x86 processor. The common thread is that both architectures are using a high degree of parallelism and simple cores to extract a lot of performance per watt.

That’s a valuable attribute for any HPC platform, but it’s critical for the next generation of multi-petaflop supercomputers. Hazra notes the performance increase in the top 100 supercomputers over the last 10 years was achieved mainly via the scale-out model, that is, adding more processors and more nodes. New CPU architectures changed the slope of the performance per watt curve somewhat, but systems have generally gotten larger, thus consuming more power.

That can’t continue for more than a few more years. It’s not practical to build a 500 petaflop system that consumes 300 megawatts. The conventional wisdom suggests power is going to capped at something between 20 and 40 megawatts for a single machine. So you can’t just ride the performance curve of existing Xeons or Opterons and expect to deliver the required performance for these future systems. “As we look out over the next five to ten years, those systems have some fundamental inflection points,” concedes Hazra.

While Intel intends to deliver the performance per watt similar to that of a GPGPU, it will do so in an x86 framework. Hazra says that will allow applications to transition from single-threaded codes to highly-parallel codes without changing the underlying model. Intel will supply compiler and runtime software support for the product, and if it becomes a commercial success, other vendors, no doubt, will add their products as well. Intel will also provide a common set of development tools to be used across the Xeon and MIC products, such that differences between the two architectures are encapsulated within tools. The goal is to be able to recompile any x86 source and have it automatically spit out MIC instructions.

The idea, of course, is to maximize programmer productivity — and not just for new codes, but also for legacy codes that represent years or even decades of investment. Intel does seem to have an advantage here. Although a Xeon-MIC combo is still a heterogeneous platform, it will be a lot more homogeneous, at least from an instruction set point of view, than say a Xeon-GPGPU platform. Hazra believes that the path they are pursuing with the x86 Intel architecture on both sides will allow them to provide a more balanced heterogeneous system. If Intel can truly deliver a minimally-painful software transition from multicore Xeons to manycore MICs, they will have a compelling HPC accelerator offering. “We believe the MIC architecture will become the workhorse as more and more applications and algorithms are able to take advantage of parallelism,” said Hazra.

The first MIC product, codenamed “Knights Corner,” is to be built with the chipmaker’s 22nm process technology. Given that the 22nm fabs will most likely be used for higher volume chips to start, we probably won’t see the first MIC until sometime in 2012. Knights Corner is supposed to be a 50-core chip, but Intel has not as yet supplied any estimated performance metrics.

Meanwhile, the chipmaker will continue to develop its multicore Xeon line that spans the enterprise and “volume” HPC market. Not every HPC application is going to need manycore acceleration, and for those codes that are more aligned with coarse-grained parallelism or are especially geared toward single-threaded performance, Xeons will be the chip of choice.

The Xeon line will continue to be developed using Intel’s 12-month tick-tock cadence — a process shrink followed by a microarchitecture update — used for its mainstream x86 processors. According to Hazra, though, the MIC cadence will be slower, more like a 18-24 month cadence, although in this case each processor update could encapsulate more significant architectural changes. This schedule aligns closely with the pace NVIDIA and AMD have set with their GPGPU offerings, and is pretty much what one would expect for a relatively low-volume accelerator.

The big unknown is if Intel can deliver the goods in time to reverse the GPGPU momentum. NVIDIA and AMD have a three-year head start, which will be extended to five years by the time the first commercial MIC chips hit the streets. Intel as a company doesn’t need to rely on the success of this manycore product for its success, but its HPC aspirations seem to be tied to it. 2012 is shaping up to be an interesting year.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

HPC Startup Advances Auto-Parallelization’s Promise

January 23, 2017

The shift from single core to multicore hardware has made finding parallelism in codes more important than ever, but that hasn’t made the task of parallel programming any easier. Read more…

By Tiffany Trader

Answered Prayers for High Frequency Traders? Latency Cut to 20 Nanoseconds

January 23, 2017

“You can buy your way out of bandwidth problems. But latency is divine.”

This sentiment, from Intel Technical Computing Group CTO Mark Seager, seems as old as the Bible, a truth universally acknowledged. Read more…

By Doug Black

CMU’s Latest “Card Shark” – Libratus – is Beating the Poker Pros (Again)

January 20, 2017

It’s starting to look like Carnegie Mellon University has a gambling problem – can’t stay away from the poker table. Read more…

By John Russell

IDG to Be Bought by Chinese Investors; IDC to Spin Out HPC Group

January 19, 2017

US-based publishing and investment firm International Data Group, Inc. (IDG) will be acquired by a pair of Chinese investors, China Oceanwide Holdings Group Co., Ltd. Read more…

By Tiffany Trader

HPE Extreme Performance Solutions

Enhancing Patient Care with Next-Generation Sequencing

In the ever-evolving world of life sciences, speed, accuracy, and savings are more important than ever. Today’s scientists and healthcare professionals are leveraging high-performance computing (HPC) solutions to solve the world’s greatest health problems and accelerate the diagnoses and treatment of a variety of medical conditions. Read more…

Weekly Twitter Roundup (Jan. 19, 2017)

January 19, 2017

Here at HPCwire, we aim to keep the HPC community apprised of the most relevant and interesting news items that get tweeted throughout the week. Read more…

By Thomas Ayres

France’s CEA and Japan’s RIKEN to Partner on ARM and Exascale

January 19, 2017

France’s CEA and Japan’s RIKEN institute announced a multi-faceted five-year collaboration to advance HPC generally and prepare for exascale computing. Among the particulars are efforts to: build out the ARM ecosystem; work on code development and code sharing on the existing and future platforms; share expertise in specific application areas (material and seismic sciences for example); improve techniques for using numerical simulation with big data; and expand HPC workforce training. It seems to be a very full agenda. Read more…

By Nishi Katsuya and John Russell

ARM Waving: Attention, Deployments, and Development

January 18, 2017

It’s been a heady two weeks for the ARM HPC advocacy camp. At this week’s Mont-Blanc Project meeting held at the Barcelona Supercomputer Center, Cray announced plans to build an ARM-based supercomputer in the U.K. while Mont-Blanc selected Cavium’s ThunderX2 ARM chip for its third phase of development. Last week, France’s CEA and Japan’s Riken announced a deep collaboration aimed largely at fostering the ARM ecosystem. This activity follows a busy 2016 when SoftBank acquired ARM, OpenHPC announced ARM support, ARM released its SVE spec, Fujistu chose ARM for the post K machine, and ARM acquired HPC tool provider Allinea in December. Read more…

By John Russell

Women Coders from Russia, Italy, and Poland Top Study

January 17, 2017

According to a study posted on HackerRank today the best women coders as judged by performance on HackerRank challenges come from Russia, Italy, and Poland. Read more…

By John Russell

HPC Startup Advances Auto-Parallelization’s Promise

January 23, 2017

The shift from single core to multicore hardware has made finding parallelism in codes more important than ever, but that hasn’t made the task of parallel programming any easier. Read more…

By Tiffany Trader

Answered Prayers for High Frequency Traders? Latency Cut to 20 Nanoseconds

January 23, 2017

“You can buy your way out of bandwidth problems. But latency is divine.”

This sentiment, from Intel Technical Computing Group CTO Mark Seager, seems as old as the Bible, a truth universally acknowledged. Read more…

By Doug Black

IDG to Be Bought by Chinese Investors; IDC to Spin Out HPC Group

January 19, 2017

US-based publishing and investment firm International Data Group, Inc. (IDG) will be acquired by a pair of Chinese investors, China Oceanwide Holdings Group Co., Ltd. Read more…

By Tiffany Trader

France’s CEA and Japan’s RIKEN to Partner on ARM and Exascale

January 19, 2017

France’s CEA and Japan’s RIKEN institute announced a multi-faceted five-year collaboration to advance HPC generally and prepare for exascale computing. Among the particulars are efforts to: build out the ARM ecosystem; work on code development and code sharing on the existing and future platforms; share expertise in specific application areas (material and seismic sciences for example); improve techniques for using numerical simulation with big data; and expand HPC workforce training. It seems to be a very full agenda. Read more…

By Nishi Katsuya and John Russell

ARM Waving: Attention, Deployments, and Development

January 18, 2017

It’s been a heady two weeks for the ARM HPC advocacy camp. At this week’s Mont-Blanc Project meeting held at the Barcelona Supercomputer Center, Cray announced plans to build an ARM-based supercomputer in the U.K. while Mont-Blanc selected Cavium’s ThunderX2 ARM chip for its third phase of development. Last week, France’s CEA and Japan’s Riken announced a deep collaboration aimed largely at fostering the ARM ecosystem. This activity follows a busy 2016 when SoftBank acquired ARM, OpenHPC announced ARM support, ARM released its SVE spec, Fujistu chose ARM for the post K machine, and ARM acquired HPC tool provider Allinea in December. Read more…

By John Russell

Spurred by Global Ambitions, Inspur in Joint HPC Deal with DDN

January 17, 2017

Inspur, the fast-growth cloud computing and server vendor from China that has several systems on the current Top500 list, and DDN, a leader in high-end storage, have announced a joint sales and marketing agreement to produce solutions based on DDN storage platforms integrated with servers, networking, software and services from Inspur. Read more…

By Doug Black

For IBM/OpenPOWER: Success in 2017 = (Volume) Sales

January 11, 2017

To a large degree IBM and the OpenPOWER Foundation have done what they said they would – assembling a substantial and growing ecosystem and bringing Power-based products to market, all in about three years. Read more…

By John Russell

UberCloud Cites Progress in HPC Cloud Computing

January 10, 2017

200 HPC cloud experiments, 80 case studies, and a ton of hands-on experience gained, that’s the harvest of four years of UberCloud HPC Experiments. Read more…

By Wolfgang Gentzsch and Burak Yenier

AWS Beats Azure to K80 General Availability

September 30, 2016

Amazon Web Services has seeded its cloud with Nvidia Tesla K80 GPUs to meet the growing demand for accelerated computing across an increasingly-diverse range of workloads. The P2 instance family is a welcome addition for compute- and data-focused users who were growing frustrated with the performance limitations of Amazon's G2 instances, which are backed by three-year-old Nvidia GRID K520 graphics cards. Read more…

By Tiffany Trader

For IBM/OpenPOWER: Success in 2017 = (Volume) Sales

January 11, 2017

To a large degree IBM and the OpenPOWER Foundation have done what they said they would – assembling a substantial and growing ecosystem and bringing Power-based products to market, all in about three years. Read more…

By John Russell

US, China Vie for Supercomputing Supremacy

November 14, 2016

The 48th edition of the TOP500 list is fresh off the presses and while there is no new number one system, as previously teased by China, there are a number of notable entrants from the US and around the world and significant trends to report on. Read more…

By Tiffany Trader

Vectors: How the Old Became New Again in Supercomputing

September 26, 2016

Vector instructions, once a powerful performance innovation of supercomputing in the 1970s and 1980s became an obsolete technology in the 1990s. But like the mythical phoenix bird, vector instructions have arisen from the ashes. Here is the history of a technology that went from new to old then back to new. Read more…

By Lynd Stringer

Container App ‘Singularity’ Eases Scientific Computing

October 20, 2016

HPC container platform Singularity is just six months out from its 1.0 release but already is making inroads across the HPC research landscape. It's in use at Lawrence Berkeley National Laboratory (LBNL), where Singularity founder Gregory Kurtzer has worked in the High Performance Computing Services (HPCS) group for 16 years. Read more…

By Tiffany Trader

Dell EMC Engineers Strategy to Democratize HPC

September 29, 2016

The freshly minted Dell EMC division of Dell Technologies is on a mission to take HPC mainstream with a strategy that hinges on engineered solutions, beginning with a focus on three industry verticals: manufacturing, research and life sciences. "Unlike traditional HPC where everybody bought parts, assembled parts and ran the workloads and did iterative engineering, we want folks to focus on time to innovation and let us worry about the infrastructure," said Jim Ganthier, senior vice president, validated solutions organization at Dell EMC Converged Platforms Solution Division. Read more…

By Tiffany Trader

D-Wave SC16 Update: What’s Bo Ewald Saying These Days

November 18, 2016

Tucked in a back section of the SC16 exhibit hall, quantum computing pioneer D-Wave has been talking up its new 2000-qubit processor announced in September. Forget for a moment the criticism sometimes aimed at D-Wave. This small Canadian company has sold several machines including, for example, ones to Lockheed and NASA, and has worked with Google on mapping machine learning problems to quantum computing. In July Los Alamos National Laboratory took possession of a 1000-quibit D-Wave 2X system that LANL ordered a year ago around the time of SC15. Read more…

By John Russell

Lighting up Aurora: Behind the Scenes at the Creation of the DOE’s Upcoming 200 Petaflops Supercomputer

December 1, 2016

In April 2015, U.S. Department of Energy Undersecretary Franklin Orr announced that Intel would be the prime contractor for Aurora: Read more…

By Jan Rowell

Leading Solution Providers

Enlisting Deep Learning in the War on Cancer

December 7, 2016

Sometime in Q2 2017 the first ‘results’ of the Joint Design of Advanced Computing Solutions for Cancer (JDACS4C) will become publicly available according to Rick Stevens. He leads one of three JDACS4C pilot projects pressing deep learning (DL) into service in the War on Cancer. Read more…

By John Russell

CPU Benchmarking: Haswell Versus POWER8

June 2, 2015

With OpenPOWER activity ramping up and IBM’s prominent role in the upcoming DOE machines Summit and Sierra, it’s a good time to look at how the IBM POWER CPU stacks up against the x86 Xeon Haswell CPU from Intel. Read more…

By Tiffany Trader

Nvidia Sees Bright Future for AI Supercomputing

November 23, 2016

Graphics chipmaker Nvidia made a strong showing at SC16 in Salt Lake City last week. Read more…

By Tiffany Trader

Beyond von Neumann, Neuromorphic Computing Steadily Advances

March 21, 2016

Neuromorphic computing – brain inspired computing – has long been a tantalizing goal. The human brain does with around 20 watts what supercomputers do with megawatts. And power consumption isn’t the only difference. Fundamentally, brains ‘think differently’ than the von Neumann architecture-based computers. While neuromorphic computing progress has been intriguing, it has still not proven very practical. Read more…

By John Russell

BioTeam’s Berman Charts 2017 HPC Trends in Life Sciences

January 4, 2017

Twenty years ago high performance computing was nearly absent from life sciences. Today it’s used throughout life sciences and biomedical research. Genomics and the data deluge from modern lab instruments are the main drivers, but so is the longer-term desire to perform predictive simulation in support of Precision Medicine (PM). There’s even a specialized life sciences supercomputer, ‘Anton’ from D.E. Shaw Research, and the Pittsburgh Supercomputing Center is standing up its second Anton 2 and actively soliciting project proposals. There’s a lot going on. Read more…

By John Russell

The Exascale Computing Project Awards $39.8M to 22 Projects

September 7, 2016

The Department of Energy’s Exascale Computing Project (ECP) hit an important milestone today with the announcement of its first round of funding, moving the nation closer to its goal of reaching capable exascale computing by 2023. Read more…

By Tiffany Trader

Dell Knights Landing Machine Sets New STAC Records

November 2, 2016

The Securities Technology Analysis Center, commonly known as STAC, has released a new report characterizing the performance of the Knight Landing-based Dell PowerEdge C6320p server on the STAC-A2 benchmarking suite, widely used by the financial services industry to test and evaluate computing platforms. The Dell machine has set new records for both the baseline Greeks benchmark and the large Greeks benchmark. Read more…

By Tiffany Trader

What Knights Landing Is Not

June 18, 2016

As we get ready to launch the newest member of the Intel Xeon Phi family, code named Knights Landing, it is natural that there be some questions and potentially some confusion. Read more…

By James Reinders, Intel

  • arrow
  • Click Here for More Headlines
  • arrow
Share This