Intel Charts Its Multicore and Manycore Future for HPC

By Michael Feldman

December 1, 2010

A lot of discussion at this year’s Supercomputing Conference was devoted to manycore architectures and exascale computing — two topics which seem to go hand-in-hand. But as the community hurtles toward the exaflop milestone, it has become clear that the natural evolution of multicore x86 CPUs won’t get the industry very far toward that goal. Manycore GPGPUs, on the other hand, do appear to be a viable path to exascale computing. So where does that leave GPU-less Intel?

In a nutshell, Intel’s answer to GPGPUs is its new Many Integrated Core (MIC) architecture. MIC, which was unveiled at the International Supercomputing Conference (ISC’10) this summer in Germany, is the recycled Larrabee technology that Intel originally developed for the high end graphics and visualization markets. When it became clear that effort wouldn’t yield a competitive alternative to the established GPUs from NVIDIA and AMD, Intel scrapped the project and recast the technology as an HPC accelerator.

To dig a little deeper into Intel’s HPC strategy, HPCwire spoke with Rajeeb Hazra, the general manager for the High Performance Computing group at Intel. A 15-year veteran of Intel, Hazra took over the HPC GM position from Richard Dracott in July of this year. Prior to that, Hazra was the director of the Supercomputing Architecture and Planning (SAP) group, which focuses on designing architectures for the highest end platforms, that is, petaflop and exaflop computing.

His experience in the supercomputing group was fortuitous, given that Intel’s biggest challenge in the server market is likely to be delivering products for the elite end of high performance computing. Today Intel is the dominant processor supplier for all HPC platforms, from top 10 supercomputers, to clusters, and down to high performance clients. The plan is to continue to do so. “Our objective is to bring to the high performance computing marketplace innovations that drive essentially all of HPC, from the very high end of supercomputing to volume workstations,” Hazra told HPCwire.

Intel’s MIC architecture stands to be a big part of that. Hazra says it will be the basis for its manycore processor design for the next decade and beyond. But first they have to hit a moving target. The rapid ascension of general-purpose GPUs into high performance computing over the last three years has given NVIDIA, and to a lesser extent AMD, a formidable head start.

As of October, the fastest supercomputer in the world, the Tianhe-1A, is a GPU-CPU hybrid. That machine delivers 2.5 petaflops on Linpack, with the vast majority of those FLOPS being supplied by the GPUs. There are a handful of other top 100 GPU-powered supercomputers, and more are on the way. If Intel doesn’t have a viable alternative to the GPGPU juggernaut, its chips will be relegated to the role of supporting player in a lot of future supercomputers, not to mention mainstream clusters and high performance workstations.

Although MIC is a modified x86 implementation and is a completely different architecture from GPGPUs, it is aimed to solve the same problem — namely to get a lot of floating point performance in a very energy efficient package. (For a detailed comparison between MIC and the latest generation Fermi GPU, see Michael Wolfe’s in-depth analysis.) It is also intended to be used in the same manner as a GPU, namely as a floating point accelerator connected to a conventional x86 processor. The common thread is that both architectures are using a high degree of parallelism and simple cores to extract a lot of performance per watt.

That’s a valuable attribute for any HPC platform, but it’s critical for the next generation of multi-petaflop supercomputers. Hazra notes the performance increase in the top 100 supercomputers over the last 10 years was achieved mainly via the scale-out model, that is, adding more processors and more nodes. New CPU architectures changed the slope of the performance per watt curve somewhat, but systems have generally gotten larger, thus consuming more power.

That can’t continue for more than a few more years. It’s not practical to build a 500 petaflop system that consumes 300 megawatts. The conventional wisdom suggests power is going to capped at something between 20 and 40 megawatts for a single machine. So you can’t just ride the performance curve of existing Xeons or Opterons and expect to deliver the required performance for these future systems. “As we look out over the next five to ten years, those systems have some fundamental inflection points,” concedes Hazra.

While Intel intends to deliver the performance per watt similar to that of a GPGPU, it will do so in an x86 framework. Hazra says that will allow applications to transition from single-threaded codes to highly-parallel codes without changing the underlying model. Intel will supply compiler and runtime software support for the product, and if it becomes a commercial success, other vendors, no doubt, will add their products as well. Intel will also provide a common set of development tools to be used across the Xeon and MIC products, such that differences between the two architectures are encapsulated within tools. The goal is to be able to recompile any x86 source and have it automatically spit out MIC instructions.

The idea, of course, is to maximize programmer productivity — and not just for new codes, but also for legacy codes that represent years or even decades of investment. Intel does seem to have an advantage here. Although a Xeon-MIC combo is still a heterogeneous platform, it will be a lot more homogeneous, at least from an instruction set point of view, than say a Xeon-GPGPU platform. Hazra believes that the path they are pursuing with the x86 Intel architecture on both sides will allow them to provide a more balanced heterogeneous system. If Intel can truly deliver a minimally-painful software transition from multicore Xeons to manycore MICs, they will have a compelling HPC accelerator offering. “We believe the MIC architecture will become the workhorse as more and more applications and algorithms are able to take advantage of parallelism,” said Hazra.

The first MIC product, codenamed “Knights Corner,” is to be built with the chipmaker’s 22nm process technology. Given that the 22nm fabs will most likely be used for higher volume chips to start, we probably won’t see the first MIC until sometime in 2012. Knights Corner is supposed to be a 50-core chip, but Intel has not as yet supplied any estimated performance metrics.

Meanwhile, the chipmaker will continue to develop its multicore Xeon line that spans the enterprise and “volume” HPC market. Not every HPC application is going to need manycore acceleration, and for those codes that are more aligned with coarse-grained parallelism or are especially geared toward single-threaded performance, Xeons will be the chip of choice.

The Xeon line will continue to be developed using Intel’s 12-month tick-tock cadence — a process shrink followed by a microarchitecture update — used for its mainstream x86 processors. According to Hazra, though, the MIC cadence will be slower, more like a 18-24 month cadence, although in this case each processor update could encapsulate more significant architectural changes. This schedule aligns closely with the pace NVIDIA and AMD have set with their GPGPU offerings, and is pretty much what one would expect for a relatively low-volume accelerator.

The big unknown is if Intel can deliver the goods in time to reverse the GPGPU momentum. NVIDIA and AMD have a three-year head start, which will be extended to five years by the time the first commercial MIC chips hit the streets. Intel as a company doesn’t need to rely on the success of this manycore product for its success, but its HPC aspirations seem to be tied to it. 2012 is shaping up to be an interesting year.

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