We’ve been hearing about so-called 3D, stacked-chip technology for a while. By layering circuits and components on top of each other, data does not need to travel as far and consequently the chip runs much faster. The design has not yet reached the commercialization stage, but that may soon change as progress on these chips appears to be reaching critical mass. This is the subject of recent Processors Whispers column, by Andreas Stiller.
The article begins by citing a humorous exchange that took place at CeBIT. When IBM Chairman Sam Palmisano presented German Chancellor Angela Merkel with a model 3D chip stack, the Chancellor asked him, “Do you take that from Intel?” Palmisano’s reply, “No, ours are better”, was nearly drowned out by the crowd’s hearty laughter.
However blunt the Chancellor’s question, Intel was among the first to grow the processor into the vertical dimension. When designing a stacked chip, one of the primary goals is to integrate the memory either above or beneath the CPU, which Intel’s Teraflops Research Chips project accomplished.
Stiller notes that IBM’s 3D technology will first appear in its upcoming Power8 processor, planned for 2013, using 28 or 22nm process technology. He says the processor will likely employ a linked memory and “a layer of small specialized computing cores adapted for specific intended uses.” The new design may even repurpose the Synergistic Processing Units of the abandoned Cell processors, as the 3D stacks offer enough room for modularity. In the future, 100,000 connections per square millimeter may be possible.
Stiller also acknowledges the possibility that Intel’s Haswell processor, the successor to Sandy Bridge that is scheduled for 2013 release, could make use of the 3D technique in the form of a large stacked cache.
Three-dimensional integration does have its drawbacks, however. The chips’ high power densities pose a significant cooling challenge. To address this issue, IBM is working with the École Polytechnique Federale de Lausanne and the ETH Zurich on an innovative cooling system that pipes water between the chip layers through tiny tubes no more than 50 microns in diameter, or about the width of a human hair. There are still many more technical challenges to overcome, however, and fully functional prototypes might not appear for another decade.