Compilers and More: Expose, Express, Exploit

By Michael Wolfe

March 28, 2011

Part 2: Programming at Exascale

In my previous column, I introduced six levels of parallelism that we’ll have in exascale systems:

  • Node level
  • Socket level
  • Core level
  • Vector level
  • Instruction level
  • Pipeline level

As we move towards exascale, we want to take advantage of all of these. We need to expose parallelism at all the levels, either explicitly in the program, or implicitly within the compiler. We need to express this parallelism, in a language and in the generated code. And we need to exploit the parallelism, efficiently and effectively, at runtime on the target machine. Performance is important; in fact, performance is key. The only reason we are looking at parallelism is for higher performance. This is a point I have made in the past, and I’ll say it again: the only reason to program in parallel is for higher performance. (Someone at SC10 responded that another reason to use parallelism is for redundancy, for error detection. I should have replied that redundancy is good, but you do the redundant computations in parallel to get the benefits of redundant computation without performance degradation.)

Exposing Parallelism

Someone has to find or create the parallelism in the program. At tera and petascale, we’ve mostly focused on data parallelism: large datasets, where the program can operate on separate data in parallel. At exascale, we’re likely to want even more parallelism, such as running coupled models in parallel. We’ll do the structural mechanics model concurrently with the heat transfer and deformation physics models. Since these models are coupled, it’s much easier to separate the problems and iterate through them one at a time; it will be a challenge to structure the code so they can run in parallel with each other. Parallelism at this high a level has to be exposed in the application design.

Within each algorithm, there is additional parallelism. This is where we get most of the parallel execution today, from individual algorithms. Parallelism at this level has finer granularity, and often is naturally dynamic. Some parallelism we get for free, meaning the compiler can find vector and instruction-level parallelism without changing the program. To be honest, this is a misrepresentation. The compiler can only find parallelism that already exists in the program. There are always ways to write the program to defeat the compiler; this isn’t a failing of the compiler, it’s compiler abuse.

Exposing parallelism, at any level, is a creative process. You choose how to organize your data such that it can be processed in parallel, or not. You choose the algorithms, solvers, conditioners, etc., that can use more parallelism, or that use less. You make these decisions in your application design. You might make different decisions, use different algorithms, depending on the target machine (laptop vs. cluster vs. exascale); this makes your job more challenging. However, since these decisions affect not only the parallelism and performance, but the accuracy and quality of the results, they have to be made by an expert, by a human.

Expressing Parallelism

Most of the discussion about parallel programming falls into this heading: how do I write my parallel program? Will I use MPI? Do I use some programming framework which is itself built on top of MPI? Do I use OpenMP directives? Do I use Cilk language extensions, or Unified Parallel C? Should I write in a consistent sequential language and use a compiler or other tool to find the parallelism? Should I use a truly higher order language, like SISAL or Haskell? Can I design a domain-specific language to make the programming more natural? Maybe I can build a C++ class library that will support my data structures directly?

There is a big step between designing an algorithm and expressing that algorithm in some language. Writing a parallel message-passing solver for large systems (such as the High Performance Linpack benchmark) is much more work that simply calling the LAPACK DGESV routine. You have to worry about data distribution, communication, and load balancing. Your answers to these will affect what algorithms you use locally and globally, and may be affected by your tolerance for numerical accuracy.

Since performance is key, we should focus on those aspects of the program that lead to high performance, or that might degrade performance. Given a parallel program, the performance keys are high locality and little synchronization. This has different meanings at different levels of parallelism. At the lowest levels of parallelism, locality is implemented in registers; the compiler manages register allocation to minimize memory accesses. We expect synchronization at the lower levels to be handled in hardware, almost for free, but we want the compiler to find enough instruction-level parallelism to exploit the functional units efficiently.

Between cores or sockets, locality is implemented in cache memory. We want the application to be organized to take advantage of the improved performance of caches for spatially and temporally local memory references. Modern cache memory hierarchies are large (12MB is not uncommon), but large parallel datasets can be huge (6GB is often considered small). Cache memory locality is typically optimized by loop tiling, usually manually in the program, but sometimes by the compiler. Cache memory locality for parallel cores can be hard to manage since some levels of the cache are shared between cores. This implies that we want those cores to share the data at that level in the cache, to avoid the cores interfering with each other. Cores on processors in separate sockets don’t share cache, so we’d like those cores to not share data, at least not very often, so the caches don’t thrash. Synchronization between cores that share memory is typically done through the memory, using locks or semaphores. It can be challenging to get these primitives correct and inserted in a way that gives high performance. Transactional memory has been proposed as a mechanism to simplify parallel programming. It treats shared data structure updates as atomic transactions, the same way a database implementation treats database updates. An implementation allows updates to separate areas of the shared data structure to proceed speculatively in parallel without explicit locks, although under the hood, as with databases, the transaction commit does use locks and incurs additional cost to verify that the transaction will behave as if it were truly atomic.

Any Single Program-Multiple Data (SPMD) program, whether MPI, Unified Parallel C, using coarrays in Fortran, or other method, requires the user to manage data locality explicitly in the program. In an MPI program, the programmer specifies what data to allocate on each node (MPI rank), and when to send or receive data from other nodes. In UPC or coarrays in Fortran, the programmer uses an additional index (or indices), the UPC shared array dimension or coarray image codimensions, to determine on which thread or image (i.e., node) the data resides. Using MPI, the program uses explicit messages; messages can have additional costs, such as implicit data copies and buffers on the sender or receiver side. However, messages also carry synchronization information, “the data is ready, and here’s the data,” along with the data. With an implicit or global address space model, the program must include separate synchronization primitives, as with a shared memory model. Neither is perfect, and both can be prone to errors.

If accelerators become common, then programs have to explicitly or implicitly be partitioned into CPU and accelerator parts. Current accelerators, such as GPUs, use a separate address space and physical memory. I hear predictions that on-chip accelerators, such as promised by the AMD Fusion devices, will solve this problem. I doubt this. Accelerators are designed for high-bandwidth memory access to support large data structures, whereas CPUs are designed for low latency operations. The CPU is supported by a deep cache hierarchy, which won’t help the accelerator, and current accelerators use a different memory implementation than a CPU. Today’s AMD Llano and Intel’s Sandy Bridge combine a relatively low-performance GPU on the CPU chip, designed to replace the integrated graphics chip that appears on many motherboards. These GPUs share the physical memory with the CPU, as those integrated graphics chips do, though not the same virtual address space. Such a solution incurs a performance penalty for not having dedicated graphics memory. Another approach would be to integrate the virtual address space of CPU and accelerator, while still maintaining the separate latency-oriented memory structure for data accessed from the CPU and bandwidth-oriented memory for accelerator data. Such an approach is used on Convey hybrid computers, with hardware to manage coherence between the CPU and accelerator, though again with performance penalties when CPU or accelerator accesses the other memory. The ultimate goal of full performance, coherent memory access across CPU and accelerator will be difficult to achieve.

The job of expressing parallelism is much more difficult today than it should be. This is largely because we have to include locality (data distribution) and synchronization (messages or explicit synchronization), and we have to express different levels of parallelism explicitly. If we want to target a multi-node, multi-core, accelerator based system, we might need to express message passing between the nodes, shared memory parallelism across cores within a node concurrently with accelerator parallelism on that node, and still leave enough vector parallelism to get the peak performance on each core. While some of this task is creative, much of it is mechanical. Choosing whether to distribute data by rows, columns, or panels can be a creative task, much as choosing a sparse matrix layout is creative. Inserting message primitives or optimizing synchronization placement is largely mechanical, and our programming mechanism should be able to handle this.

Exploiting Parallelism

The final step is to take the parallelism we’ve exposed and expressed and to map it to the target machine. With current MPI programs, this is a simple mechanical task, since all the work was done by the programmer. We should demand more from our implementation. We should want more flexibility across many dimensions, including scalability, dynamic parallelism, composability, load balancing, as well as productivity. Let’s take each in turn.

Scalability: The usual discussion of scalability is to be able to write programs that scale up to massive amounts of parallelism. In the exascale world, we need to have the right algorithms with enough parallelism to give us that level of performance; making those choices is a creative task, and we can’t expect to automate that. However, we should demand that the same program can be scaled down to run efficiently on our (smaller) terascale systems, our clusters, our workstations, and even our laptops. Automatically scaling down should be easier than automatically scaling up; in fact, it should be mostly mechanical, choosing which levels of parallelism to scale back or scalarize entirely. If the parallelism is expressed opaquely in the program (as with an MPI library), such decisions must be made by the programmer; we should design better programming strategies.

Dynamic parallelism: Most of the current large-scale parallel programming models are static: MPI mostly requires the processes to be created at program startup, though MPI-2 does add some weak support for dynamic process creation. Coarray Fortran and UPC similarly start a static number of images or threads. High Performance Fortran suffered from the same weakness. Shared memory models are often more dynamic; OpenMP can dynamically create nested parallel regions, and dynamically create tasks within each region, though the number of actual threads for each region is fixed. Cilk allows spawning of parallel strands, though the parallelism is exploited at runtime by some number of threads or processors managed by the runtime. The more recent High Productivity Programming Languages X10, Chapel and Fortress have more support for dynamic parallelism, and some traction among small groups of users, so perhaps there’s hope.

Composability: However I express my basic operations, the implementation must be able to efficiently compose these for the target processor. For instance, if I should write in Fortran:

    r = sum( x(:) * y(:) )

the definition is that the array product x(:)*y(:) be computed and stored in a temporary array, possibly dynamically allocated, then the elements of the temporary array are summed. However, the implementation shouldn’t have to create the temporary array; if this is being executed in scalar mode, the implementation should be just as efficient as the corresponding loop:

    r = 0     do i = . . .      r = r + x(i)*y(i)     enddo

If this is executed in parallel, each thread or process should be able to accumulate its partial sum efficiently in scalar mode, then the partial sums combined appropriately, with only one temporary scalar per thread. Some approaches to HPC are weak with respect to composability, as I’ll point out in the next column.

Load Balancing: Researchers in the past have developed implementations of parallel systems that monitor the performance across the cores and nodes, and redistribute the work and even the data to balance the load and improve the performance. With low-level parallel programming, work and data distribution is opaque to the runtime system, but there’s no reason we can’t change that. This requires certain characteristics of the program to be exposed to the implementation, such as the data and work distribution, so it can be measured and managed.

There’s a great deal of work in runtime optimization, ranging from systems that vary runtime parameters such as tile sizes to tune for cache locality, all the way to managed languages that compile the hot routines to native code and even specializing the code for runtime values. At least some of these are ripe for industrialization in the HPC space.

Productivity: In the past, productivity in HPC focused on how close the application could get to the peak performance of the computer. This is still important; no one would argue that we should use these 100-million-dollar mega-computers inefficiently. However, even at that price, the cost of the 1,000+ scientists and engineers that will use the machine approaches or exceeds the cost of the hardware. So, however measured, we want to make productive use of the machine, and make productive use of our time.

Many argue that we want our scientists (astronomers, chemists, physicists, biologists) to be able to directly program these machines with the same productivity as when they use Matlab or Mathematica. I’m going out on a limb here; I don’t see these astronomers polishing their own mirrors for large, multi-million dollar telescopes. I don’t see physicists winding wires around superconducting magnets for the colliders, or biologists constructing scanning, tunneling electron microscopes. Of course, early astronomers really did grind lenses and polish mirrors, but now they specify the design and hire an expert to do that for them. Why should we not expect the same protocol for high end computing? Why should scientists not hire an HPC expert to build and tune the program? Yes, software is fundamentally different than a piece of hardware, but the goals are not just the specification and implementation of an algorithm, but the expression of that algorithm that provides enough performance to change the nature of science that we can perform. If that’s not enough motivation to invest in expert programmers, what is?

So what are the characteristics of a programming method for the coming exascale systems? How different will it be from what we have today? That is the topic of my third, and hopefully final, column on exascale programming.

About the Author

Michael Wolfe has developed compilers for over 30 years in both academia and industry, and is now a senior compiler engineer at The Portland Group, Inc. (www.pgroup.com), a wholly-owned subsidiary of STMicroelectronics, Inc. The opinions stated here are those of the author, and do not represent opinions of The Portland Group, Inc. or STMicroelectronics, Inc.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

What’s New in HPC Research: September (Part 1)

September 18, 2018

In this new bimonthly feature, HPCwire will highlight newly published research in the high-performance computing community and related domains. From exascale to quantum computing, the details are here. Check back every Read more…

By Oliver Peckham

House Passes $1.275B National Quantum Initiative

September 17, 2018

Last Thursday the U.S. House of Representatives passed the National Quantum Initiative Act (NQIA) intended to accelerate quantum computing research and development. Among other things it would establish a National Quantu Read more…

By John Russell

Nvidia Accelerates AI Inference in the Datacenter with T4 GPU

September 14, 2018

Nvidia is upping its game for AI inference in the datacenter with a new platform consisting of an inference accelerator chip--the new Turing-based Tesla T4 GPU--and a refresh of its inference server software packaged as Read more…

By George Leopold

HPE Extreme Performance Solutions

Introducing the First Integrated System Management Software for HPC Clusters from HPE

How do you manage your complex, growing cluster environments? Answer that big challenge with the new HPC cluster management solution: HPE Performance Cluster Manager. Read more…

IBM Accelerated Insights

A Crystal Ball for HPC

People are notoriously bad at predicting the future.  This very much includes experts. In the Forbes article “Why Most Predictions Are So Bad” Philip Tetlock discusses the largest and best-known test of the accuracy of expert predictions which show that any experts would do better if they make random guesses. Read more…

NSF Highlights Expanded Efforts for Broadening Participation in Computing

September 13, 2018

Today, the Directorate of Computer and Information Science and Engineering (CISE) of the NSF released a letter highlighting the expansion of its broadening participation in computing efforts. The letter was penned by Jam Read more…

By Staff

House Passes $1.275B National Quantum Initiative

September 17, 2018

Last Thursday the U.S. House of Representatives passed the National Quantum Initiative Act (NQIA) intended to accelerate quantum computing research and developm Read more…

By John Russell

Nvidia Accelerates AI Inference in the Datacenter with T4 GPU

September 14, 2018

Nvidia is upping its game for AI inference in the datacenter with a new platform consisting of an inference accelerator chip--the new Turing-based Tesla T4 GPU- Read more…

By George Leopold

DeepSense Combines HPC and AI to Bolster Canada’s Ocean Economy

September 13, 2018

We often hear scientists say that we know less than 10 percent of the life of the oceans. This week, IBM and a group of Canadian industry and government partner Read more…

By Tiffany Trader

Rigetti (and Others) Pursuit of Quantum Advantage

September 11, 2018

Remember ‘quantum supremacy’, the much-touted but little-loved idea that the age of quantum computing would be signaled when quantum computers could tackle Read more…

By John Russell

How FPGAs Accelerate Financial Services Workloads

September 11, 2018

While FSI companies are unlikely, for competitive reasons, to disclose their FPGA strategies, James Reinders offers insights into the case for FPGAs as accelerators for FSI by discussing performance, power, size, latency, jitter and inline processing. Read more…

By James Reinders

Update from Gregory Kurtzer on Singularity’s Push into FS and the Enterprise

September 11, 2018

Container technology is hardly new but it has undergone rapid evolution in the HPC space in recent years to accommodate traditional science workloads and HPC systems requirements. While Docker containers continue to dominate in the enterprise, other variants are becoming important and one alternative with distinctly HPC roots – Singularity – is making an enterprise push targeting advanced scale workload inclusive of HPC. Read more…

By John Russell

At HPC on Wall Street: AI-as-a-Service Accelerates AI Journeys

September 10, 2018

AIaaS – artificial intelligence-as-a-service – is the technology discipline that eases enterprise entry into the mysteries of the AI journey while lowering Read more…

By Doug Black

No Go for GloFo at 7nm; and the Fujitsu A64FX post-K CPU

September 5, 2018

It’s been a news worthy couple of weeks in the semiconductor and HPC industry. There were several HPC relevant disclosures at Hot Chips 2018 to whet appetites Read more…

By Dairsie Latimer

TACC Wins Next NSF-funded Major Supercomputer

July 30, 2018

The Texas Advanced Computing Center (TACC) has won the next NSF-funded big supercomputer beating out rivals including the National Center for Supercomputing Ap Read more…

By John Russell

IBM at Hot Chips: What’s Next for Power

August 23, 2018

With processor, memory and networking technologies all racing to fill in for an ailing Moore’s law, the era of the heterogeneous datacenter is well underway, Read more…

By Tiffany Trader

Requiem for a Phi: Knights Landing Discontinued

July 25, 2018

On Monday, Intel made public its end of life strategy for the Knights Landing "KNL" Phi product set. The announcement makes official what has already been wide Read more…

By Tiffany Trader

CERN Project Sees Orders-of-Magnitude Speedup with AI Approach

August 14, 2018

An award-winning effort at CERN has demonstrated potential to significantly change how the physics based modeling and simulation communities view machine learni Read more…

By Rob Farber

ORNL Summit Supercomputer Is Officially Here

June 8, 2018

Oak Ridge National Laboratory (ORNL) together with IBM and Nvidia celebrated the official unveiling of the Department of Energy (DOE) Summit supercomputer toda Read more…

By Tiffany Trader

New Deep Learning Algorithm Solves Rubik’s Cube

July 25, 2018

Solving (and attempting to solve) Rubik’s Cube has delighted millions of puzzle lovers since 1974 when the cube was invented by Hungarian sculptor and archite Read more…

By John Russell

AMD’s EPYC Road to Redemption in Six Slides

June 21, 2018

A year ago AMD returned to the server market with its EPYC processor line. The earth didn’t tremble but folks took notice. People remember the Opteron fondly Read more…

By John Russell

MLPerf – Will New Machine Learning Benchmark Help Propel AI Forward?

May 2, 2018

Let the AI benchmarking wars begin. Today, a diverse group from academia and industry – Google, Baidu, Intel, AMD, Harvard, and Stanford among them – releas Read more…

By John Russell

Leading Solution Providers

SC17 Booth Video Tours Playlist

Altair @ SC17

Altair

AMD @ SC17

AMD

ASRock Rack @ SC17

ASRock Rack

CEJN @ SC17

CEJN

DDN Storage @ SC17

DDN Storage

Huawei @ SC17

Huawei

IBM @ SC17

IBM

IBM Power Systems @ SC17

IBM Power Systems

Intel @ SC17

Intel

Lenovo @ SC17

Lenovo

Mellanox Technologies @ SC17

Mellanox Technologies

Microsoft @ SC17

Microsoft

Penguin Computing @ SC17

Penguin Computing

Pure Storage @ SC17

Pure Storage

Supericro @ SC17

Supericro

Tyan @ SC17

Tyan

Univa @ SC17

Univa

Pattern Computer – Startup Claims Breakthrough in ‘Pattern Discovery’ Technology

May 23, 2018

If it weren’t for the heavy-hitter technology team behind start-up Pattern Computer, which emerged from stealth today in a live-streamed event from San Franci Read more…

By John Russell

Sandia to Take Delivery of World’s Largest Arm System

June 18, 2018

While the enterprise remains circumspect on prospects for Arm servers in the datacenter, the leadership HPC community is taking a bolder, brighter view of the x86 server CPU alternative. Amongst current and planned Arm HPC installations – i.e., the innovative Mont-Blanc project, led by Bull/Atos, the 'Isambard’ Cray XC50 going into the University of Bristol, and commitments from both Japan and France among others -- HPE is announcing that it will be supply the United States National Nuclear Security Administration (NNSA) with a 2.3 petaflops peak Arm-based system, named Astra. Read more…

By Tiffany Trader

D-Wave Breaks New Ground in Quantum Simulation

July 16, 2018

Last Friday D-Wave scientists and colleagues published work in Science which they say represents the first fulfillment of Richard Feynman’s 1982 notion that Read more…

By John Russell

Intel Pledges First Commercial Nervana Product ‘Spring Crest’ in 2019

May 24, 2018

At its AI developer conference in San Francisco yesterday, Intel embraced a holistic approach to AI and showed off a broad AI portfolio that includes Xeon processors, Movidius technologies, FPGAs and Intel’s Nervana Neural Network Processors (NNPs), based on the technology it acquired in 2016. Read more…

By Tiffany Trader

Intel Announces Cooper Lake, Advances AI Strategy

August 9, 2018

Intel's chief datacenter exec Navin Shenoy kicked off the company's Data-Centric Innovation Summit Wednesday, the day-long program devoted to Intel's datacenter Read more…

By Tiffany Trader

TACC’s ‘Frontera’ Supercomputer Expands Horizon for Extreme-Scale Science

August 29, 2018

The National Science Foundation and the Texas Advanced Computing Center announced today that a new system, called Frontera, will overtake Stampede 2 as the fast Read more…

By Tiffany Trader

GPUs Power Five of World’s Top Seven Supercomputers

June 25, 2018

The top 10 echelon of the newly minted Top500 list boasts three powerful new systems with one common engine: the Nvidia Volta V100 general-purpose graphics proc Read more…

By Tiffany Trader

The Machine Learning Hype Cycle and HPC

June 14, 2018

Like many other HPC professionals I’m following the hype cycle around machine learning/deep learning with interest. I subscribe to the view that we’re probably approaching the ‘peak of inflated expectation’ but not quite yet starting the descent into the ‘trough of disillusionment. This still raises the probability that... Read more…

By Dairsie Latimer

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This