Compilers and More: Expose, Express, Exploit

By Michael Wolfe

March 28, 2011

Part 2: Programming at Exascale

In my previous column, I introduced six levels of parallelism that we’ll have in exascale systems:

  • Node level
  • Socket level
  • Core level
  • Vector level
  • Instruction level
  • Pipeline level

As we move towards exascale, we want to take advantage of all of these. We need to expose parallelism at all the levels, either explicitly in the program, or implicitly within the compiler. We need to express this parallelism, in a language and in the generated code. And we need to exploit the parallelism, efficiently and effectively, at runtime on the target machine. Performance is important; in fact, performance is key. The only reason we are looking at parallelism is for higher performance. This is a point I have made in the past, and I’ll say it again: the only reason to program in parallel is for higher performance. (Someone at SC10 responded that another reason to use parallelism is for redundancy, for error detection. I should have replied that redundancy is good, but you do the redundant computations in parallel to get the benefits of redundant computation without performance degradation.)

Exposing Parallelism

Someone has to find or create the parallelism in the program. At tera and petascale, we’ve mostly focused on data parallelism: large datasets, where the program can operate on separate data in parallel. At exascale, we’re likely to want even more parallelism, such as running coupled models in parallel. We’ll do the structural mechanics model concurrently with the heat transfer and deformation physics models. Since these models are coupled, it’s much easier to separate the problems and iterate through them one at a time; it will be a challenge to structure the code so they can run in parallel with each other. Parallelism at this high a level has to be exposed in the application design.

Within each algorithm, there is additional parallelism. This is where we get most of the parallel execution today, from individual algorithms. Parallelism at this level has finer granularity, and often is naturally dynamic. Some parallelism we get for free, meaning the compiler can find vector and instruction-level parallelism without changing the program. To be honest, this is a misrepresentation. The compiler can only find parallelism that already exists in the program. There are always ways to write the program to defeat the compiler; this isn’t a failing of the compiler, it’s compiler abuse.

Exposing parallelism, at any level, is a creative process. You choose how to organize your data such that it can be processed in parallel, or not. You choose the algorithms, solvers, conditioners, etc., that can use more parallelism, or that use less. You make these decisions in your application design. You might make different decisions, use different algorithms, depending on the target machine (laptop vs. cluster vs. exascale); this makes your job more challenging. However, since these decisions affect not only the parallelism and performance, but the accuracy and quality of the results, they have to be made by an expert, by a human.

Expressing Parallelism

Most of the discussion about parallel programming falls into this heading: how do I write my parallel program? Will I use MPI? Do I use some programming framework which is itself built on top of MPI? Do I use OpenMP directives? Do I use Cilk language extensions, or Unified Parallel C? Should I write in a consistent sequential language and use a compiler or other tool to find the parallelism? Should I use a truly higher order language, like SISAL or Haskell? Can I design a domain-specific language to make the programming more natural? Maybe I can build a C++ class library that will support my data structures directly?

There is a big step between designing an algorithm and expressing that algorithm in some language. Writing a parallel message-passing solver for large systems (such as the High Performance Linpack benchmark) is much more work that simply calling the LAPACK DGESV routine. You have to worry about data distribution, communication, and load balancing. Your answers to these will affect what algorithms you use locally and globally, and may be affected by your tolerance for numerical accuracy.

Since performance is key, we should focus on those aspects of the program that lead to high performance, or that might degrade performance. Given a parallel program, the performance keys are high locality and little synchronization. This has different meanings at different levels of parallelism. At the lowest levels of parallelism, locality is implemented in registers; the compiler manages register allocation to minimize memory accesses. We expect synchronization at the lower levels to be handled in hardware, almost for free, but we want the compiler to find enough instruction-level parallelism to exploit the functional units efficiently.

Between cores or sockets, locality is implemented in cache memory. We want the application to be organized to take advantage of the improved performance of caches for spatially and temporally local memory references. Modern cache memory hierarchies are large (12MB is not uncommon), but large parallel datasets can be huge (6GB is often considered small). Cache memory locality is typically optimized by loop tiling, usually manually in the program, but sometimes by the compiler. Cache memory locality for parallel cores can be hard to manage since some levels of the cache are shared between cores. This implies that we want those cores to share the data at that level in the cache, to avoid the cores interfering with each other. Cores on processors in separate sockets don’t share cache, so we’d like those cores to not share data, at least not very often, so the caches don’t thrash. Synchronization between cores that share memory is typically done through the memory, using locks or semaphores. It can be challenging to get these primitives correct and inserted in a way that gives high performance. Transactional memory has been proposed as a mechanism to simplify parallel programming. It treats shared data structure updates as atomic transactions, the same way a database implementation treats database updates. An implementation allows updates to separate areas of the shared data structure to proceed speculatively in parallel without explicit locks, although under the hood, as with databases, the transaction commit does use locks and incurs additional cost to verify that the transaction will behave as if it were truly atomic.

Any Single Program-Multiple Data (SPMD) program, whether MPI, Unified Parallel C, using coarrays in Fortran, or other method, requires the user to manage data locality explicitly in the program. In an MPI program, the programmer specifies what data to allocate on each node (MPI rank), and when to send or receive data from other nodes. In UPC or coarrays in Fortran, the programmer uses an additional index (or indices), the UPC shared array dimension or coarray image codimensions, to determine on which thread or image (i.e., node) the data resides. Using MPI, the program uses explicit messages; messages can have additional costs, such as implicit data copies and buffers on the sender or receiver side. However, messages also carry synchronization information, “the data is ready, and here’s the data,” along with the data. With an implicit or global address space model, the program must include separate synchronization primitives, as with a shared memory model. Neither is perfect, and both can be prone to errors.

If accelerators become common, then programs have to explicitly or implicitly be partitioned into CPU and accelerator parts. Current accelerators, such as GPUs, use a separate address space and physical memory. I hear predictions that on-chip accelerators, such as promised by the AMD Fusion devices, will solve this problem. I doubt this. Accelerators are designed for high-bandwidth memory access to support large data structures, whereas CPUs are designed for low latency operations. The CPU is supported by a deep cache hierarchy, which won’t help the accelerator, and current accelerators use a different memory implementation than a CPU. Today’s AMD Llano and Intel’s Sandy Bridge combine a relatively low-performance GPU on the CPU chip, designed to replace the integrated graphics chip that appears on many motherboards. These GPUs share the physical memory with the CPU, as those integrated graphics chips do, though not the same virtual address space. Such a solution incurs a performance penalty for not having dedicated graphics memory. Another approach would be to integrate the virtual address space of CPU and accelerator, while still maintaining the separate latency-oriented memory structure for data accessed from the CPU and bandwidth-oriented memory for accelerator data. Such an approach is used on Convey hybrid computers, with hardware to manage coherence between the CPU and accelerator, though again with performance penalties when CPU or accelerator accesses the other memory. The ultimate goal of full performance, coherent memory access across CPU and accelerator will be difficult to achieve.

The job of expressing parallelism is much more difficult today than it should be. This is largely because we have to include locality (data distribution) and synchronization (messages or explicit synchronization), and we have to express different levels of parallelism explicitly. If we want to target a multi-node, multi-core, accelerator based system, we might need to express message passing between the nodes, shared memory parallelism across cores within a node concurrently with accelerator parallelism on that node, and still leave enough vector parallelism to get the peak performance on each core. While some of this task is creative, much of it is mechanical. Choosing whether to distribute data by rows, columns, or panels can be a creative task, much as choosing a sparse matrix layout is creative. Inserting message primitives or optimizing synchronization placement is largely mechanical, and our programming mechanism should be able to handle this.

Exploiting Parallelism

The final step is to take the parallelism we’ve exposed and expressed and to map it to the target machine. With current MPI programs, this is a simple mechanical task, since all the work was done by the programmer. We should demand more from our implementation. We should want more flexibility across many dimensions, including scalability, dynamic parallelism, composability, load balancing, as well as productivity. Let’s take each in turn.

Scalability: The usual discussion of scalability is to be able to write programs that scale up to massive amounts of parallelism. In the exascale world, we need to have the right algorithms with enough parallelism to give us that level of performance; making those choices is a creative task, and we can’t expect to automate that. However, we should demand that the same program can be scaled down to run efficiently on our (smaller) terascale systems, our clusters, our workstations, and even our laptops. Automatically scaling down should be easier than automatically scaling up; in fact, it should be mostly mechanical, choosing which levels of parallelism to scale back or scalarize entirely. If the parallelism is expressed opaquely in the program (as with an MPI library), such decisions must be made by the programmer; we should design better programming strategies.

Dynamic parallelism: Most of the current large-scale parallel programming models are static: MPI mostly requires the processes to be created at program startup, though MPI-2 does add some weak support for dynamic process creation. Coarray Fortran and UPC similarly start a static number of images or threads. High Performance Fortran suffered from the same weakness. Shared memory models are often more dynamic; OpenMP can dynamically create nested parallel regions, and dynamically create tasks within each region, though the number of actual threads for each region is fixed. Cilk allows spawning of parallel strands, though the parallelism is exploited at runtime by some number of threads or processors managed by the runtime. The more recent High Productivity Programming Languages X10, Chapel and Fortress have more support for dynamic parallelism, and some traction among small groups of users, so perhaps there’s hope.

Composability: However I express my basic operations, the implementation must be able to efficiently compose these for the target processor. For instance, if I should write in Fortran:

    r = sum( x(:) * y(:) )

the definition is that the array product x(:)*y(:) be computed and stored in a temporary array, possibly dynamically allocated, then the elements of the temporary array are summed. However, the implementation shouldn’t have to create the temporary array; if this is being executed in scalar mode, the implementation should be just as efficient as the corresponding loop:

    r = 0     do i = . . .      r = r + x(i)*y(i)     enddo

If this is executed in parallel, each thread or process should be able to accumulate its partial sum efficiently in scalar mode, then the partial sums combined appropriately, with only one temporary scalar per thread. Some approaches to HPC are weak with respect to composability, as I’ll point out in the next column.

Load Balancing: Researchers in the past have developed implementations of parallel systems that monitor the performance across the cores and nodes, and redistribute the work and even the data to balance the load and improve the performance. With low-level parallel programming, work and data distribution is opaque to the runtime system, but there’s no reason we can’t change that. This requires certain characteristics of the program to be exposed to the implementation, such as the data and work distribution, so it can be measured and managed.

There’s a great deal of work in runtime optimization, ranging from systems that vary runtime parameters such as tile sizes to tune for cache locality, all the way to managed languages that compile the hot routines to native code and even specializing the code for runtime values. At least some of these are ripe for industrialization in the HPC space.

Productivity: In the past, productivity in HPC focused on how close the application could get to the peak performance of the computer. This is still important; no one would argue that we should use these 100-million-dollar mega-computers inefficiently. However, even at that price, the cost of the 1,000+ scientists and engineers that will use the machine approaches or exceeds the cost of the hardware. So, however measured, we want to make productive use of the machine, and make productive use of our time.

Many argue that we want our scientists (astronomers, chemists, physicists, biologists) to be able to directly program these machines with the same productivity as when they use Matlab or Mathematica. I’m going out on a limb here; I don’t see these astronomers polishing their own mirrors for large, multi-million dollar telescopes. I don’t see physicists winding wires around superconducting magnets for the colliders, or biologists constructing scanning, tunneling electron microscopes. Of course, early astronomers really did grind lenses and polish mirrors, but now they specify the design and hire an expert to do that for them. Why should we not expect the same protocol for high end computing? Why should scientists not hire an HPC expert to build and tune the program? Yes, software is fundamentally different than a piece of hardware, but the goals are not just the specification and implementation of an algorithm, but the expression of that algorithm that provides enough performance to change the nature of science that we can perform. If that’s not enough motivation to invest in expert programmers, what is?

So what are the characteristics of a programming method for the coming exascale systems? How different will it be from what we have today? That is the topic of my third, and hopefully final, column on exascale programming.

About the Author

Michael Wolfe has developed compilers for over 30 years in both academia and industry, and is now a senior compiler engineer at The Portland Group, Inc. (, a wholly-owned subsidiary of STMicroelectronics, Inc. The opinions stated here are those of the author, and do not represent opinions of The Portland Group, Inc. or STMicroelectronics, Inc.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Cray Completes ClusterStor Deal, Sunsets Sonexion Brand

September 25, 2017

Having today completed the transaction and strategic partnership with Seagate announced back in July, Cray is now home to the ClusterStor line and will be sunsetting the Sonexion brand. This is not an acquisition; the ClusterStor assets are transferring from Seagate to Cray (minus the Seagate ClusterStor IBM Spectrum Scale product) and Cray is taking over support and maintenance for the entire ClusterStor base. Read more…

By Tiffany Trader

China’s TianHe-2A will Use Proprietary Accelerator and Boast 94 Petaflops Peak

September 25, 2017

The details of China’s upgrade to TianHe-2 (MilkyWay-2) – now TianHe-2A – were revealed last week at the Third International High Performance Computing Forum (IHPCF2017) in China. The TianHe-2A will use a proprieta Read more…

By John Russell

SC17 Preview: Invited Talk Lineup Includes Gordon Bell, Paul Messina and Many Others

September 25, 2017

With the addition of esteemed supercomputing pioneer Gordon Bell to its invited talk lineup, SC17 now boasts a total of 12 invited talks on its agenda. As SC explains, "Invited Talks are a premier component of the SC Read more…

By Tiffany Trader

HPE Extreme Performance Solutions

HPE Prepares Customers for Success with the HPC Software Portfolio

High performance computing (HPC) software is key to harnessing the full power of HPC environments. Development and management tools enable IT departments to streamline installation and maintenance of their systems as well as create, optimize, and run their HPC applications. Read more…

GlobalFoundries Puts Wind in AMD’s Sails with 12nm FinFET

September 24, 2017

From its annual tech conference last week (Sept. 20), where GlobalFoundries welcomed more than 600 semiconductor professionals (reaching the Santa Clara venue’s max capacity and doubling 2016 attendee numbers), the one Read more…

By Tiffany Trader

Cray Completes ClusterStor Deal, Sunsets Sonexion Brand

September 25, 2017

Having today completed the transaction and strategic partnership with Seagate announced back in July, Cray is now home to the ClusterStor line and will be sunsetting the Sonexion brand. This is not an acquisition; the ClusterStor assets are transferring from Seagate to Cray (minus the Seagate ClusterStor IBM Spectrum Scale product) and Cray is taking over support and maintenance for the entire ClusterStor base. Read more…

By Tiffany Trader

China’s TianHe-2A will Use Proprietary Accelerator and Boast 94 Petaflops Peak

September 25, 2017

The details of China’s upgrade to TianHe-2 (MilkyWay-2) – now TianHe-2A – were revealed last week at the Third International High Performance Computing Fo Read more…

By John Russell

GlobalFoundries Puts Wind in AMD’s Sails with 12nm FinFET

September 24, 2017

From its annual tech conference last week (Sept. 20), where GlobalFoundries welcomed more than 600 semiconductor professionals (reaching the Santa Clara venue Read more…

By Tiffany Trader

Machine Learning at HPC User Forum: Drilling into Specific Use Cases

September 22, 2017

The 66th HPC User Forum held September 5-7, in Milwaukee, Wisconsin, at the elegant and historic Pfister Hotel, highlighting the 1893 Victorian décor and art o Read more…

By Arno Kolster

Stanford University and UberCloud Achieve Breakthrough in Living Heart Simulations

September 21, 2017

Cardiac arrhythmia can be an undesirable and potentially lethal side effect of drugs. During this condition, the electrical activity of the heart turns chaotic, Read more…

By Wolfgang Gentzsch, UberCloud, and Francisco Sahli, Stanford University

PNNL’s Center for Advanced Tech Evaluation Seeks Wider HPC Community Ties

September 21, 2017

Two years ago the Department of Energy established the Center for Advanced Technology Evaluation (CENATE) at Pacific Northwest National Laboratory (PNNL). CENAT Read more…

By John Russell

Exascale Computing Project Names Doug Kothe as Director

September 20, 2017

The Department of Energy’s Exascale Computing Project (ECP) has named Doug Kothe as its new director effective October 1. He replaces Paul Messina, who is stepping down after two years to return to Argonne National Laboratory. Kothe is a 32-year veteran of DOE’s National Laboratory System. Read more…

Takeaways from the Milwaukee HPC User Forum

September 19, 2017

Milwaukee’s elegant Pfister Hotel hosted approximately 100 attendees for the 66th HPC User Forum (September 5-7, 2017). In the original home city of Pabst Blu Read more…

By Merle Giles

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

NERSC Scales Scientific Deep Learning to 15 Petaflops

August 28, 2017

A collaborative effort between Intel, NERSC and Stanford has delivered the first 15-petaflops deep learning software running on HPC platforms and is, according Read more…

By Rob Farber

Oracle Layoffs Reportedly Hit SPARC and Solaris Hard

September 7, 2017

Oracle’s latest layoffs have many wondering if this is the end of the line for the SPARC processor and Solaris OS development. As reported by multiple sources Read more…

By John Russell

Six Exascale PathForward Vendors Selected; DoE Providing $258M

June 15, 2017

The much-anticipated PathForward awards for hardware R&D in support of the Exascale Computing Project were announced today with six vendors selected – AMD Read more…

By John Russell

Top500 Results: Latest List Trends and What’s in Store

June 19, 2017

Greetings from Frankfurt and the 2017 International Supercomputing Conference where the latest Top500 list has just been revealed. Although there were no major Read more…

By Tiffany Trader

IBM Clears Path to 5nm with Silicon Nanosheets

June 5, 2017

Two years since announcing the industry’s first 7nm node test chip, IBM and its research alliance partners GlobalFoundries and Samsung have developed a proces Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Leading Solution Providers

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in Read more…

By Tiffany Trader

Google Releases Deeplearn.js to Further Democratize Machine Learning

August 17, 2017

Spreading the use of machine learning tools is one of the goals of Google’s PAIR (People + AI Research) initiative, which was introduced in early July. Last w Read more…

By John Russell

EU Funds 20 Million Euro ARM+FPGA Exascale Project

September 7, 2017

At the Barcelona Supercomputer Centre on Wednesday (Sept. 6), 16 partners gathered to launch the EuroEXA project, which invests €20 million over three-and-a-half years into exascale-focused research and development. Led by the Horizon 2020 program, EuroEXA picks up the banner of a triad of partner projects — ExaNeSt, EcoScale and ExaNoDe — building on their work... Read more…

By Tiffany Trader

Amazon Debuts New AMD-based GPU Instances for Graphics Acceleration

September 12, 2017

Last week Amazon Web Services (AWS) streaming service, AppStream 2.0, introduced a new GPU instance called Graphics Design intended to accelerate graphics. The Read more…

By John Russell

Cray Moves to Acquire the Seagate ClusterStor Line

July 28, 2017

This week Cray announced that it is picking up Seagate's ClusterStor HPC storage array business for an undisclosed sum. "In short we're effectively transitioning the bulk of the ClusterStor product line to Cray," said CEO Peter Ungaro. Read more…

By Tiffany Trader

Russian Researchers Claim First Quantum-Safe Blockchain

May 25, 2017

The Russian Quantum Center today announced it has overcome the threat of quantum cryptography by creating the first quantum-safe blockchain, securing cryptocurrencies like Bitcoin, along with classified government communications and other sensitive digital transfers. Read more…

By Doug Black

IBM Advances Web-based Quantum Programming

September 5, 2017

IBM Research is pairing its Jupyter-based Data Science Experience notebook environment with its cloud-based quantum computer, IBM Q, in hopes of encouraging a new class of entrepreneurial user to solve intractable problems that even exceed the capabilities of the best AI systems. Read more…

By Alex Woodie

GlobalFoundries: 7nm Chips Coming in 2018, EUV in 2019

June 13, 2017

GlobalFoundries has formally announced that its 7nm technology is ready for customer engagement with product tape outs expected for the first half of 2018. The Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This