Compilers and More: Exascale Programming Requirements

By Michael Wolfe

April 14, 2011

Programming at Exascale, Part 3

In an earlier column, I discussed six levels of parallelism that we’ll have in exascale systems: node, socket, core, vector, instruction, and pipeline levels, and said that to reach exascale performance, we need to take advantage of all these levels, since the final performance is the product of them all. In my most recent column, I argued that to be successful at that, we need to effectively expose, express, and exploit parallelism: expose it in the application and algorithms, express it in the language and program, and exploit it in the generated code and at runtime. Exposing parallelism is mostly a creative task, and thus must be done by humans. Expressing parallelism is where we mostly get sidetracked: what language, what kind of parallelism, how will it work with legacy software? Since parallel programming is all about performance, we need to focus on those aspects that would hinder performance, specifically locality and synchronization. Finally, successfully exploiting parallelism means mapping the parallelism exposed in the application and expressed in the program to the parallelism in the hardware. I discussed five dimensions of flexibility: scalability, dynamic parallelism, composability, load balancing, and productivity. In this column, the last of a three-part series, I’ll give my views on what programming at the exascale level is likely to require, and how we can get there from where we are today. My belief is that it will take some work, but it’s not a wholesale rewrite of 50 years of high performance expertise.

Exascale Programming: What It Won’t Be

What are the characteristics of a programming strategy for the coming exascale computers? It’s easier to say what it isn’t.

It’s not a library. Encapsulation is a well-known, often used, and important technique to building large systems. By design, encapsulation hides information about the implementation of the encapsulated object (data structure, algorithm, service) from the user of that object. Encapsulation will continue to be important for many reasons. But information hiding obscures not just the algorithm and data structures, but performance aspects, such as what kinds of parallelism are used within the encapsulated object and how that interacts with parallelism of the user of that object, or low level information such as how the data is laid out and how that affects locality in an algorithm. In particular, opaque low-level libraries (e.g., MPI for data distribution and message passing) hide too much information from the system, preventing any system-level tuning. That’s not to say a useful system won’t be built using MPI as the transport layer, but MPI or POSIX threads or other low-level libraries should not be directly used in the application.

It’s not a C++ class hierarchy or template library. Here, I’m again going out on a limb; there have been and continue to be many sets of useful C++ class libraries intended to raise the level of application programming. Take the C++ standard template library for vector; the intent of such a template is to allow a user to define a data structure and get the benefit of reusing any routines in the STL or from elsewhere built on the vector template. But you don’t really understand the performance of the vector datatype; that information hiding means you don’t know if accesses to vector V; are efficient or not. Compare that to an array access in a loop, with the corresponding vector access V[i]; the array access can often be optimized down to two instructions: load, and increment the pointer to the next address. Moreover, two-dimensional objects using the vector type (vector>) become even more opaque.

Or take Thrust, an STL-like implementation providing a high-level interface to GPU programming, built on CUDA. You can define two vectors in Thrust as

   using namespace thrust;    device_vector x(1000);    device_vector y(1000); 

Multiplying two such vectors and then accumulating the result can be done as:

   transform( x.begin(), x.end(), y.begin(), z.begin(), multiplies() );    r = reduce( z.begin(), z.end(), 0, plus() );

This is certainly easier (more productive?) to write than the equivalent CUDA C (or CUDA Fortran) code, but it’s still far easier to write the Fortran:

   r = sum( x(:) * y(:) ) 

Moreover, when the constructs are part of the language, the compiler can compose and optimize them together. As mentioned in my last column, in the Fortran case, the compiler can generate code for the multiply then accumulate the result without requiring an intermediate vector result. With the C++ library, the code for the transform method doesn’t know that its result will immediately be accumulated, so the method or (as in this case) the user has to provide a result vector. The only tool the compiler has to optimize class library calls is inlining, and it’s simply not enough to recover the performance lost by the abstraction. There have been some efforts to use run-time code generation, building the expression tree from the method calls, then generating the optimized (and composed) code from the whole expression tree; this was the technology behind Rapidmind, which is now being used in Intel’s Array Building Blocks (ArBB). Such mechanisms are promising, but what we really want is a way to define new data types and describe operations to the compiler in a way that the compiler can reason about them, compose them, reorder them, and so on; currently, the definition is basically in terms of C code, which is not expressive enough. There’s a research project just waiting to happen.

It’s not a domain-specific language. I really like the idea of DSLs, of embedding domain knowledge in the language and using that knowledge when generating and optimizing the code. However, languages, real languages, are big project; DSLs are (by definition) specialized, and hence don’t have a large enough user community to support production, maintenance and continuing development of the language and all the tools needed to support a language. We can’t expect language implementors (like PGI) to take on the development and continuing support of a plethora of languages, any more than we should expect user communities to each design, implement, and then continue to update, enhance, tune and optimize the language implementation with each new processor release from Intel. A possible alternative approach would be to implement a language to support DSLs, supported by a language vendor, including interfacing to debuggers, performance tools, editors, and so on. The various user communities would then be somewhat insulated from the details of a performance-oriented solution, and the vendor would avoid falling into the many-languages trap. There’s another potential research project.

It’s not OpenCL. OpenCL may be a necessary step towards heterogeneous programming, but it’s not the final answer. It’s very low level, “close to the metal”, as even the language designers admit. As with MPI, we may be able to build on OpenCL, but it’s not sufficient.

It’s not a whole new language. New languages have a high barrier to entry; most programmers avoid adopting a new language for fear that it will die, unless the language meets some need better than anything else, or until it has survived along enough to ameliorate the fear. But I think a new language is not called for here. We may benefit from some new features in existing languages, and maybe new ways to make programs in those languages, but most new languages really don’t add semantically much beyond managed memory.

It’s not easy. I’ve argued before that parallel programming is not easy, won’t be, and can’t be made easy. The idea of making parallel programming easy is silly.

It’s not just parallelism. Parallelism is an important aspect, perhaps the dominant aspect, but the key isn’t parallelism, it’s performance. A bad parallel algorithm doesn’t run fast just because it’s parallel. A bad implementation of a good parallel algorithm will also be slow. It’s quite easy to write slow parallel programs; this was the key failure (my opinion) of High Performance Fortran. So our programming mechanism will focus on performance, where parallelism is one aspect (locality and synchronization being two more).

Exascale Programming: What It Is

So what do we want and need when programming at exascale from whatever programming environment we get? Here is my bucket list:

  • It supports all levels of parallelism, from node parallelism down to vector and pipeline parallelism, effectively. Support is a big word here; it has to allow for a programming model that an application developer can use to think about what kinds of parallelism will map well at different levels, that a programmer can use to write a program that can be mapped well at different levels, and that the implementation (compiler and runtime) can use to exploit the parallelism. We have this today, clumsily, with different mechanisms for different levels; a bit more integration would take us a long way.
  • It can map an expression of program parallelism (a parallel loop, say) to different levels of hardware parallelism (across nodes, or to a vector unit) depending on the target. This will make it scalable up and down, from exascale to laptop. There was a great deal of work on the SISAL language to efficiently scalarize an implicitly parallel language, which turned out to be largely the dual of the parallelizing compiler problem. Such work will be part of this parallelism remapping. Remapping node-level parallelism may require changing the data distribution per node; today, this is done at the application level. We should be able to specify what parameters of the program depend on which aspects of the target machine, so the system can do the remapping.
  • It supports the programmer with lots of feedback. Vectorizing compilers have been very successful for over 35 years in delivering good vector performance from sequential loops because the compilers tell the programmer when they are successful, and more importantly, when and why they fail. This is essentially performance feedback. We are in the business of developing high performance applications, and we should be notified when we are using constructs that will restrict our performance. Static feedback and useful dynamic feedback will both be critical.
  • It supports dynamic parallelism, creating parallel tasks and threads when needed. There are many successful and useful implementations of dynamic parallelism, some limited (OpenMP) and some more aggressive (Cilk). Dynamic parallelism is somewhat at odds with locality and synchronization optimization. Using a work-stealing scheduler, an idle worker will steal a work item from the queue of another worker. However, that work item may have been placed on that worker’s queue because that’s where its data is, or because that work item depends on some other work item also assigned to that worker. However, without constructs for dynamic parallelism, we end up micromanaging thread-level parallelism in the constructs we do have.
  • It efficiently composes abstract operations, as I discussed in my previous column; whether these are native to the language, or abstract operations defined by a user or in a library, the implementation must be able to combine them naturally. Perhaps, when we define abstract operations, we need a mechanism to describe how they can compose with others. Many now-standard compiler optimizations fall into composition, such as loop vectorization and loop fusion. We need more investigation about what composing abstract operations means, beyond simply inlining.
  • It is self-balancing and self-tuning. This involves runtime introspection and behavior modification, and means the parameters or data and work distribution must be exposed to the system in order to be modified. Examples include changing the tile sizes for tiled nested loops when optimized for cache locality, or changing the data distributions when the work load is not uniform across the domain. Such behavior modification has been demonstrated in many systems, though not many integrated with the programming language and its implementation.
  • It must be resilient. The big systems are, many believe, going to be in partial failure mode much of the time. This presents challenges for the system manager and programmer. Expecting the entire system to be working, taking checkpoints and restoring from a failure point will not be efficient if failures are the norm. Some of the necessary features must be supported by the hardware (getting data off a node with a failed processor; early failure detection). Other features could be supported by some of the runtime features we develop for other reasons (redistributing data to working nodes; reserving some nodes to serve as online replacements). Such a system can survive and continue beyond many failures.

Most of these points (except for the last) have been researched and implemented in some form already, and could be reproduced with current technology (and enough motivation) in Fortran, C++, or whatever language you want. We have to extend the programming model to expose performance aspects and perhaps resilience aspects, so the user can guide how the system (compiler plus runtime) implements the program. We often get focused on either abstracting away so much that we lose sight of performance (as happened with High Performance Fortran), or we get so tied up with performance that we focus too much on details of each target machine (as happens today with OpenCL and CUDA). We need to let the programmer do the creative parts, and let the system do the mechanical work.

Final Note: This series of columns is an expanded form of the material from the PGI Exhibitor Forum presentation at SC10 in New Orleans. If you were there, you can tell me whether it’s more informative (or entertaining) in written or verbal form.

About the Author

Michael Wolfe has developed compilers for over 30 years in both academia and industry, and is now a senior compiler engineer at The Portland Group, Inc. (www.pgroup.com), a wholly-owned subsidiary of STMicroelectronics, Inc. The opinions stated here are those of the author, and do not represent opinions of The Portland Group, Inc. or STMicroelectronics, Inc.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

What’s New in HPC Research: Wind Farms, Gravitational Lenses, Web Portals & More

February 19, 2019

In this bimonthly feature, HPCwire highlights newly published research in the high-performance computing community and related domains. From parallel programming to exascale to quantum computing, the details are here. Read more…

By Oliver Peckham

Insights from Optimized Codes on Cineca’s Marconi

February 15, 2019

What can you do with 381,392 CPU cores? For Cineca, it means enabling computational scientists to expand a large part of the world’s body of knowledge from the nanoscale to the astronomic, from calculating quantum effe Read more…

By Ken Strandberg

What Will IBM’s AI Debater Learn from Its Loss?

February 14, 2019

The utility of IBM’s latest man-versus-machine gambit is debatable. At the very least its Project Debater got us thinking about the potential uses of artificial intelligence as a way of helping humans sift through al Read more…

By George Leopold

HPE Extreme Performance Solutions

HPE Systems With Intel Omni-Path: Architected for Value and Accessible High-Performance Computing

Today’s high-performance computing (HPC) and artificial intelligence (AI) users value high performing clusters. And the higher the performance that their system can deliver, the better. Read more…

IBM Accelerated Insights

Medical Research Powered by Data

“We’re all the same, but we’re unique as well. In that uniqueness lies all of the answers….”

  • Mark Tykocinski, MD, Provost, Executive Vice President for Academic Affairs, Thomas Jefferson University

Getting the answers to what causes some people to develop diseases and not others is driving the groundbreaking medical research being conducted by the Computational Medicine Center at Thomas Jefferson University in Philadelphia. Read more…

ClusterVision in Bankruptcy, Fate Uncertain

February 13, 2019

ClusterVision, European HPC specialists that have built and installed over 20 Top500-ranked systems in their nearly 17-year history, appear to be in the midst of bankruptcy proceedings. According to Dutch news site Drimb Read more…

By Tiffany Trader

Insights from Optimized Codes on Cineca’s Marconi

February 15, 2019

What can you do with 381,392 CPU cores? For Cineca, it means enabling computational scientists to expand a large part of the world’s body of knowledge from th Read more…

By Ken Strandberg

ClusterVision in Bankruptcy, Fate Uncertain

February 13, 2019

ClusterVision, European HPC specialists that have built and installed over 20 Top500-ranked systems in their nearly 17-year history, appear to be in the midst o Read more…

By Tiffany Trader

UC Berkeley Paper Heralds Rise of Serverless Computing in the Cloud – Do You Agree?

February 13, 2019

Almost exactly ten years to the day from publishing of their widely-read, seminal paper on cloud computing, UC Berkeley researchers have issued another ambitious examination of cloud computing - Cloud Programming Simplified: A Berkeley View on Serverless Computing. The new work heralds the rise of ‘serverless computing’ as the next dominant phase of cloud computing. Read more…

By John Russell

Iowa ‘Grows Its Own’ to Fill the HPC Workforce Pipeline

February 13, 2019

The global workforce that supports advanced computing, scientific software and high-speed research networks is relatively small when you stop to consider the magnitude of the transformative discoveries it empowers. Technical conferences provide a forum where specialists convene to learn about the latest innovations and schedule face-time with colleagues from other institutions. Read more…

By Elizabeth Leake, STEM-Trek

Trump Signs Executive Order Launching U.S. AI Initiative

February 11, 2019

U.S. President Donald Trump issued an Executive Order (EO) today launching a U.S Artificial Intelligence Initiative. The new initiative - Maintaining American L Read more…

By John Russell

Celebrating Women in Science: Meet Four Women Leading the Way in HPC

February 11, 2019

One only needs to look around at virtually any CS/tech conference to realize that women are underrepresented, and that holds true of HPC. SC hosts over 13,000 H Read more…

By AJ Lauer

IBM Bets $2B Seeking 1000X AI Hardware Performance Boost

February 7, 2019

For now, AI systems are mostly machine learning-based and “narrow” – powerful as they are by today's standards, they're limited to performing a few, narro Read more…

By Doug Black

Assessing Government Shutdown’s Impact on HPC

February 6, 2019

After a 35-day federal government shutdown, the longest in U.S. history, government agencies are taking stock of the damage -- and girding for a potential secon Read more…

By Tiffany Trader

Quantum Computing Will Never Work

November 27, 2018

Amid the gush of money and enthusiastic predictions being thrown at quantum computing comes a proposed cold shower in the form of an essay by physicist Mikhail Read more…

By John Russell

Cray Unveils Shasta, Lands NERSC-9 Contract

October 30, 2018

Cray revealed today the details of its next-gen supercomputing architecture, Shasta, selected to be the next flagship system at NERSC. We've known of the code-name "Shasta" since the Argonne slice of the CORAL project was announced in 2015 and although the details of that plan have changed considerably, Cray didn't slow down its timeline for Shasta. Read more…

By Tiffany Trader

The Case Against ‘The Case Against Quantum Computing’

January 9, 2019

It’s not easy to be a physicist. Richard Feynman (basically the Jimi Hendrix of physicists) once said: “The first principle is that you must not fool yourse Read more…

By Ben Criger

AMD Sets Up for Epyc Epoch

November 16, 2018

It’s been a good two weeks, AMD’s Gary Silcott and Andy Parma told me on the last day of SC18 in Dallas at the restaurant where we met to discuss their show news and recent successes. Heck, it’s been a good year. Read more…

By Tiffany Trader

Intel Reportedly in $6B Bid for Mellanox

January 30, 2019

The latest rumors and reports around an acquisition of Mellanox focus on Intel, which has reportedly offered a $6 billion bid for the high performance interconn Read more…

By Doug Black

US Leads Supercomputing with #1, #2 Systems & Petascale Arm

November 12, 2018

The 31st Supercomputing Conference (SC) - commemorating 30 years since the first Supercomputing in 1988 - kicked off in Dallas yesterday, taking over the Kay Ba Read more…

By Tiffany Trader

Looking for Light Reading? NSF-backed ‘Comic Books’ Tackle Quantum Computing

January 28, 2019

Still baffled by quantum computing? How about turning to comic books (graphic novels for the well-read among you) for some clarity and a little humor on QC. The Read more…

By John Russell

ClusterVision in Bankruptcy, Fate Uncertain

February 13, 2019

ClusterVision, European HPC specialists that have built and installed over 20 Top500-ranked systems in their nearly 17-year history, appear to be in the midst o Read more…

By Tiffany Trader

Leading Solution Providers

SC 18 Virtual Booth Video Tour

Advania @ SC18 AMD @ SC18
ASRock Rack @ SC18
DDN Storage @ SC18
HPE @ SC18
IBM @ SC18
Lenovo @ SC18 Mellanox Technologies @ SC18
NVIDIA @ SC18
One Stop Systems @ SC18
Oracle @ SC18 Panasas @ SC18
Supermicro @ SC18 SUSE @ SC18 TYAN @ SC18
Verne Global @ SC18

Contract Signed for New Finnish Supercomputer

December 13, 2018

After the official contract signing yesterday, configuration details were made public for the new BullSequana system that the Finnish IT Center for Science (CSC Read more…

By Tiffany Trader

Deep500: ETH Researchers Introduce New Deep Learning Benchmark for HPC

February 5, 2019

ETH researchers have developed a new deep learning benchmarking environment – Deep500 – they say is “the first distributed and reproducible benchmarking s Read more…

By John Russell

IBM Quantum Update: Q System One Launch, New Collaborators, and QC Center Plans

January 10, 2019

IBM made three significant quantum computing announcements at CES this week. One was introduction of IBM Q System One; it’s really the integration of IBM’s Read more…

By John Russell

HPC Reflections and (Mostly Hopeful) Predictions

December 19, 2018

So much ‘spaghetti’ gets tossed on walls by the technology community (vendors and researchers) to see what sticks that it is often difficult to peer through Read more…

By John Russell

IBM Bets $2B Seeking 1000X AI Hardware Performance Boost

February 7, 2019

For now, AI systems are mostly machine learning-based and “narrow” – powerful as they are by today's standards, they're limited to performing a few, narro Read more…

By Doug Black

Nvidia’s Jensen Huang Delivers Vision for the New HPC

November 14, 2018

For nearly two hours on Monday at SC18, Jensen Huang, CEO of Nvidia, presented his expansive view of the future of HPC (and computing in general) as only he can do. Animated. Backstopped by a stream of data charts, product photos, and even a beautiful image of supernovae... Read more…

By John Russell

The Deep500 – Researchers Tackle an HPC Benchmark for Deep Learning

January 7, 2019

How do you know if an HPC system, particularly a larger-scale system, is well-suited for deep learning workloads? Today, that’s not an easy question to answer Read more…

By John Russell

Intel Confirms 48-Core Cascade Lake-AP for 2019

November 4, 2018

As part of the run-up to SC18, taking place in Dallas next week (Nov. 11-16), Intel is doling out info on its next-gen Cascade Lake family of Xeon processors, specifically the “Advanced Processor” version (Cascade Lake-AP), architected for high-performance computing, artificial intelligence and infrastructure-as-a-service workloads. Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This