Compilers and More: Exascale Programming Requirements

By Michael Wolfe

April 14, 2011

Programming at Exascale, Part 3

In an earlier column, I discussed six levels of parallelism that we’ll have in exascale systems: node, socket, core, vector, instruction, and pipeline levels, and said that to reach exascale performance, we need to take advantage of all these levels, since the final performance is the product of them all. In my most recent column, I argued that to be successful at that, we need to effectively expose, express, and exploit parallelism: expose it in the application and algorithms, express it in the language and program, and exploit it in the generated code and at runtime. Exposing parallelism is mostly a creative task, and thus must be done by humans. Expressing parallelism is where we mostly get sidetracked: what language, what kind of parallelism, how will it work with legacy software? Since parallel programming is all about performance, we need to focus on those aspects that would hinder performance, specifically locality and synchronization. Finally, successfully exploiting parallelism means mapping the parallelism exposed in the application and expressed in the program to the parallelism in the hardware. I discussed five dimensions of flexibility: scalability, dynamic parallelism, composability, load balancing, and productivity. In this column, the last of a three-part series, I’ll give my views on what programming at the exascale level is likely to require, and how we can get there from where we are today. My belief is that it will take some work, but it’s not a wholesale rewrite of 50 years of high performance expertise.

Exascale Programming: What It Won’t Be

What are the characteristics of a programming strategy for the coming exascale computers? It’s easier to say what it isn’t.

It’s not a library. Encapsulation is a well-known, often used, and important technique to building large systems. By design, encapsulation hides information about the implementation of the encapsulated object (data structure, algorithm, service) from the user of that object. Encapsulation will continue to be important for many reasons. But information hiding obscures not just the algorithm and data structures, but performance aspects, such as what kinds of parallelism are used within the encapsulated object and how that interacts with parallelism of the user of that object, or low level information such as how the data is laid out and how that affects locality in an algorithm. In particular, opaque low-level libraries (e.g., MPI for data distribution and message passing) hide too much information from the system, preventing any system-level tuning. That’s not to say a useful system won’t be built using MPI as the transport layer, but MPI or POSIX threads or other low-level libraries should not be directly used in the application.

It’s not a C++ class hierarchy or template library. Here, I’m again going out on a limb; there have been and continue to be many sets of useful C++ class libraries intended to raise the level of application programming. Take the C++ standard template library for vector; the intent of such a template is to allow a user to define a data structure and get the benefit of reusing any routines in the STL or from elsewhere built on the vector template. But you don’t really understand the performance of the vector datatype; that information hiding means you don’t know if accesses to vector V; are efficient or not. Compare that to an array access in a loop, with the corresponding vector access V[i]; the array access can often be optimized down to two instructions: load, and increment the pointer to the next address. Moreover, two-dimensional objects using the vector type (vector>) become even more opaque.

Or take Thrust, an STL-like implementation providing a high-level interface to GPU programming, built on CUDA. You can define two vectors in Thrust as

   using namespace thrust;    device_vector x(1000);    device_vector y(1000); 

Multiplying two such vectors and then accumulating the result can be done as:

   transform( x.begin(), x.end(), y.begin(), z.begin(), multiplies() );    r = reduce( z.begin(), z.end(), 0, plus() );

This is certainly easier (more productive?) to write than the equivalent CUDA C (or CUDA Fortran) code, but it’s still far easier to write the Fortran:

   r = sum( x(:) * y(:) ) 

Moreover, when the constructs are part of the language, the compiler can compose and optimize them together. As mentioned in my last column, in the Fortran case, the compiler can generate code for the multiply then accumulate the result without requiring an intermediate vector result. With the C++ library, the code for the transform method doesn’t know that its result will immediately be accumulated, so the method or (as in this case) the user has to provide a result vector. The only tool the compiler has to optimize class library calls is inlining, and it’s simply not enough to recover the performance lost by the abstraction. There have been some efforts to use run-time code generation, building the expression tree from the method calls, then generating the optimized (and composed) code from the whole expression tree; this was the technology behind Rapidmind, which is now being used in Intel’s Array Building Blocks (ArBB). Such mechanisms are promising, but what we really want is a way to define new data types and describe operations to the compiler in a way that the compiler can reason about them, compose them, reorder them, and so on; currently, the definition is basically in terms of C code, which is not expressive enough. There’s a research project just waiting to happen.

It’s not a domain-specific language. I really like the idea of DSLs, of embedding domain knowledge in the language and using that knowledge when generating and optimizing the code. However, languages, real languages, are big project; DSLs are (by definition) specialized, and hence don’t have a large enough user community to support production, maintenance and continuing development of the language and all the tools needed to support a language. We can’t expect language implementors (like PGI) to take on the development and continuing support of a plethora of languages, any more than we should expect user communities to each design, implement, and then continue to update, enhance, tune and optimize the language implementation with each new processor release from Intel. A possible alternative approach would be to implement a language to support DSLs, supported by a language vendor, including interfacing to debuggers, performance tools, editors, and so on. The various user communities would then be somewhat insulated from the details of a performance-oriented solution, and the vendor would avoid falling into the many-languages trap. There’s another potential research project.

It’s not OpenCL. OpenCL may be a necessary step towards heterogeneous programming, but it’s not the final answer. It’s very low level, “close to the metal”, as even the language designers admit. As with MPI, we may be able to build on OpenCL, but it’s not sufficient.

It’s not a whole new language. New languages have a high barrier to entry; most programmers avoid adopting a new language for fear that it will die, unless the language meets some need better than anything else, or until it has survived along enough to ameliorate the fear. But I think a new language is not called for here. We may benefit from some new features in existing languages, and maybe new ways to make programs in those languages, but most new languages really don’t add semantically much beyond managed memory.

It’s not easy. I’ve argued before that parallel programming is not easy, won’t be, and can’t be made easy. The idea of making parallel programming easy is silly.

It’s not just parallelism. Parallelism is an important aspect, perhaps the dominant aspect, but the key isn’t parallelism, it’s performance. A bad parallel algorithm doesn’t run fast just because it’s parallel. A bad implementation of a good parallel algorithm will also be slow. It’s quite easy to write slow parallel programs; this was the key failure (my opinion) of High Performance Fortran. So our programming mechanism will focus on performance, where parallelism is one aspect (locality and synchronization being two more).

Exascale Programming: What It Is

So what do we want and need when programming at exascale from whatever programming environment we get? Here is my bucket list:

  • It supports all levels of parallelism, from node parallelism down to vector and pipeline parallelism, effectively. Support is a big word here; it has to allow for a programming model that an application developer can use to think about what kinds of parallelism will map well at different levels, that a programmer can use to write a program that can be mapped well at different levels, and that the implementation (compiler and runtime) can use to exploit the parallelism. We have this today, clumsily, with different mechanisms for different levels; a bit more integration would take us a long way.
  • It can map an expression of program parallelism (a parallel loop, say) to different levels of hardware parallelism (across nodes, or to a vector unit) depending on the target. This will make it scalable up and down, from exascale to laptop. There was a great deal of work on the SISAL language to efficiently scalarize an implicitly parallel language, which turned out to be largely the dual of the parallelizing compiler problem. Such work will be part of this parallelism remapping. Remapping node-level parallelism may require changing the data distribution per node; today, this is done at the application level. We should be able to specify what parameters of the program depend on which aspects of the target machine, so the system can do the remapping.
  • It supports the programmer with lots of feedback. Vectorizing compilers have been very successful for over 35 years in delivering good vector performance from sequential loops because the compilers tell the programmer when they are successful, and more importantly, when and why they fail. This is essentially performance feedback. We are in the business of developing high performance applications, and we should be notified when we are using constructs that will restrict our performance. Static feedback and useful dynamic feedback will both be critical.
  • It supports dynamic parallelism, creating parallel tasks and threads when needed. There are many successful and useful implementations of dynamic parallelism, some limited (OpenMP) and some more aggressive (Cilk). Dynamic parallelism is somewhat at odds with locality and synchronization optimization. Using a work-stealing scheduler, an idle worker will steal a work item from the queue of another worker. However, that work item may have been placed on that worker’s queue because that’s where its data is, or because that work item depends on some other work item also assigned to that worker. However, without constructs for dynamic parallelism, we end up micromanaging thread-level parallelism in the constructs we do have.
  • It efficiently composes abstract operations, as I discussed in my previous column; whether these are native to the language, or abstract operations defined by a user or in a library, the implementation must be able to combine them naturally. Perhaps, when we define abstract operations, we need a mechanism to describe how they can compose with others. Many now-standard compiler optimizations fall into composition, such as loop vectorization and loop fusion. We need more investigation about what composing abstract operations means, beyond simply inlining.
  • It is self-balancing and self-tuning. This involves runtime introspection and behavior modification, and means the parameters or data and work distribution must be exposed to the system in order to be modified. Examples include changing the tile sizes for tiled nested loops when optimized for cache locality, or changing the data distributions when the work load is not uniform across the domain. Such behavior modification has been demonstrated in many systems, though not many integrated with the programming language and its implementation.
  • It must be resilient. The big systems are, many believe, going to be in partial failure mode much of the time. This presents challenges for the system manager and programmer. Expecting the entire system to be working, taking checkpoints and restoring from a failure point will not be efficient if failures are the norm. Some of the necessary features must be supported by the hardware (getting data off a node with a failed processor; early failure detection). Other features could be supported by some of the runtime features we develop for other reasons (redistributing data to working nodes; reserving some nodes to serve as online replacements). Such a system can survive and continue beyond many failures.

Most of these points (except for the last) have been researched and implemented in some form already, and could be reproduced with current technology (and enough motivation) in Fortran, C++, or whatever language you want. We have to extend the programming model to expose performance aspects and perhaps resilience aspects, so the user can guide how the system (compiler plus runtime) implements the program. We often get focused on either abstracting away so much that we lose sight of performance (as happened with High Performance Fortran), or we get so tied up with performance that we focus too much on details of each target machine (as happens today with OpenCL and CUDA). We need to let the programmer do the creative parts, and let the system do the mechanical work.

Final Note: This series of columns is an expanded form of the material from the PGI Exhibitor Forum presentation at SC10 in New Orleans. If you were there, you can tell me whether it’s more informative (or entertaining) in written or verbal form.

About the Author

Michael Wolfe has developed compilers for over 30 years in both academia and industry, and is now a senior compiler engineer at The Portland Group, Inc. (www.pgroup.com), a wholly-owned subsidiary of STMicroelectronics, Inc. The opinions stated here are those of the author, and do not represent opinions of The Portland Group, Inc. or STMicroelectronics, Inc.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

DARPA Continues Investment in Post-Moore’s Technologies

July 24, 2017

The U.S. military long ago ceded dominance in electronics innovation to Silicon Valley, the DoD-backed powerhouse that has driven microelectronic generation for decades. With Moore's Law clearly running out of steam, the Read more…

By George Leopold

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in 2017 with scale-up production for enterprise datacenters and Read more…

By Tiffany Trader

Fine-Tuning Severe Hail Forecasting with Machine Learning

July 20, 2017

Depending on whether you’ve been caught outside during a severe hail storm, the sight of greenish tinted clouds on the horizon may cause serious knots in the pit of your stomach, or at least give you pause. There’s g Read more…

By Sean Thielen

Trinity Supercomputer’s Haswell and KNL Partitions Are Merged

July 19, 2017

Trinity supercomputer’s two partitions – one based on Intel Xeon Haswell processors and the other on Xeon Phi Knights Landing – have been fully integrated are now available for use on classified work in the Nationa Read more…

By HPCwire Staff

HPE Extreme Performance Solutions

HPE Servers Deliver High Performance Remote Visualization

Whether generating seismic simulations, locating new productive oil reservoirs, or constructing complex models of the earth’s subsurface, energy, oil, and gas (EO&G) is a highly data-driven industry. Read more…

Fujitsu Continues HPC, AI Push

July 19, 2017

Summer is well under way, but the so-called summertime slowdown, linked with hot temperatures and longer vacations, does not seem to have impacted Fujitsu's output. The Japanese multinational has made a raft of HPC and A Read more…

By Tiffany Trader

Researchers Use DNA to Store and Retrieve Digital Movie

July 18, 2017

From abacus to pencil and paper to semiconductor chips, the technology of computing has always been an ever-changing target. The human brain is probably the computer we use most (hopefully) and understand least. This mon Read more…

By John Russell

The Exascale FY18 Budget – The Next Step

July 17, 2017

On July 12, 2017, the U.S. federal budget for its Exascale Computing Initiative (ECI) took its next step forward. On that day, the full Appropriations Committee of the House of Representatives voted to accept the recomme Read more…

By Alex R. Larzelere

Summer Reading: IEEE Spectrum’s Chip Hall of Fame

July 17, 2017

Take a trip down memory lane – the Mostek MK4096 4-kilobit DRAM, for instance. Perhaps processors are more to your liking. Remember the Sh-Boom processor (1988), created by Russell Fish and Chuck Moore, and named after Read more…

By John Russell

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in Read more…

By Tiffany Trader

Fine-Tuning Severe Hail Forecasting with Machine Learning

July 20, 2017

Depending on whether you’ve been caught outside during a severe hail storm, the sight of greenish tinted clouds on the horizon may cause serious knots in the Read more…

By Sean Thielen

Fujitsu Continues HPC, AI Push

July 19, 2017

Summer is well under way, but the so-called summertime slowdown, linked with hot temperatures and longer vacations, does not seem to have impacted Fujitsu's out Read more…

By Tiffany Trader

Researchers Use DNA to Store and Retrieve Digital Movie

July 18, 2017

From abacus to pencil and paper to semiconductor chips, the technology of computing has always been an ever-changing target. The human brain is probably the com Read more…

By John Russell

The Exascale FY18 Budget – The Next Step

July 17, 2017

On July 12, 2017, the U.S. federal budget for its Exascale Computing Initiative (ECI) took its next step forward. On that day, the full Appropriations Committee Read more…

By Alex R. Larzelere

Women in HPC Luncheon Shines Light on Female-Friendly Hiring Practices

July 13, 2017

The second annual Women in HPC luncheon was held on June 20, 2017, during the International Supercomputing Conference in Frankfurt, Germany. The luncheon provid Read more…

By Tiffany Trader

Satellite Advances, NSF Computation Power Rapid Mapping of Earth’s Surface

July 13, 2017

New satellite technologies have completely changed the game in mapping and geographical data gathering, reducing costs and placing a new emphasis on time series Read more…

By Ken Chiacchia and Tiffany Jolley

Intel Skylake: Xeon Goes from Chip to Platform

July 13, 2017

With yesterday’s New York unveiling of the new “Skylake” Xeon Scalable processors, Intel made multiple runs at multiple competitive threats and strategic Read more…

By Doug Black

Google Pulls Back the Covers on Its First Machine Learning Chip

April 6, 2017

This week Google released a report detailing the design and performance characteristics of the Tensor Processing Unit (TPU), its custom ASIC for the inference Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Quantum Bits: D-Wave and VW; Google Quantum Lab; IBM Expands Access

March 21, 2017

For a technology that’s usually characterized as far off and in a distant galaxy, quantum computing has been steadily picking up steam. Just how close real-wo Read more…

By John Russell

HPC Compiler Company PathScale Seeks Life Raft

March 23, 2017

HPCwire has learned that HPC compiler company PathScale has fallen on difficult times and is asking the community for help or actively seeking a buyer for its a Read more…

By Tiffany Trader

Trump Budget Targets NIH, DOE, and EPA; No Mention of NSF

March 16, 2017

President Trump’s proposed U.S. fiscal 2018 budget issued today sharply cuts science spending while bolstering military spending as he promised during the cam Read more…

By John Russell

CPU-based Visualization Positions for Exascale Supercomputing

March 16, 2017

In this contributed perspective piece, Intel’s Jim Jeffers makes the case that CPU-based visualization is now widely adopted and as such is no longer a contrarian view, but is rather an exascale requirement. Read more…

By Jim Jeffers, Principal Engineer and Engineering Leader, Intel

Nvidia’s Mammoth Volta GPU Aims High for AI, HPC

May 10, 2017

At Nvidia's GPU Technology Conference (GTC17) in San Jose, Calif., this morning, CEO Jensen Huang announced the company's much-anticipated Volta architecture a Read more…

By Tiffany Trader

Facebook Open Sources Caffe2; Nvidia, Intel Rush to Optimize

April 18, 2017

From its F8 developer conference in San Jose, Calif., today, Facebook announced Caffe2, a new open-source, cross-platform framework for deep learning. Caffe2 is the successor to Caffe, the deep learning framework developed by Berkeley AI Research and community contributors. Read more…

By Tiffany Trader

Leading Solution Providers

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

MIT Mathematician Spins Up 220,000-Core Google Compute Cluster

April 21, 2017

On Thursday, Google announced that MIT math professor and computational number theorist Andrew V. Sutherland had set a record for the largest Google Compute Engine (GCE) job. Sutherland ran the massive mathematics workload on 220,000 GCE cores using preemptible virtual machine instances. Read more…

By Tiffany Trader

Russian Researchers Claim First Quantum-Safe Blockchain

May 25, 2017

The Russian Quantum Center today announced it has overcome the threat of quantum cryptography by creating the first quantum-safe blockchain, securing cryptocurrencies like Bitcoin, along with classified government communications and other sensitive digital transfers. Read more…

By Doug Black

Google Debuts TPU v2 and will Add to Google Cloud

May 25, 2017

Not long after stirring attention in the deep learning/AI community by revealing the details of its Tensor Processing Unit (TPU), Google last week announced the Read more…

By John Russell

Groq This: New AI Chips to Give GPUs a Run for Deep Learning Money

April 24, 2017

CPUs and GPUs, move over. Thanks to recent revelations surrounding Google’s new Tensor Processing Unit (TPU), the computing world appears to be on the cusp of Read more…

By Alex Woodie

Six Exascale PathForward Vendors Selected; DoE Providing $258M

June 15, 2017

The much-anticipated PathForward awards for hardware R&D in support of the Exascale Computing Project were announced today with six vendors selected – AMD Read more…

By John Russell

Top500 Results: Latest List Trends and What’s in Store

June 19, 2017

Greetings from Frankfurt and the 2017 International Supercomputing Conference where the latest Top500 list has just been revealed. Although there were no major Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This