Startup Launches Manycore Floating Point Acceleration Technology

By Michael Feldman

May 3, 2011

Semiconductor startup Adapteva has demonstrated a manycore floating point processor architecture that promises ten times the performance per watt as the best chip technology on the market today. The architecture, called Epiphany, is aimed initially at embedded applications, but has general applicability across all math-intensive workloads in mobile computing, telecommunications and high performance computing.

Epiphany is the brainchild of Adapteva CEO and founder Andreas Olofsson, who spent nearly 15 years as chip designer, first at for Texas Instruments and later at Analog Devices. Olofsson has managed to bootstrap his company with less than $2 million, initially paying out of his own pocket to get the company up and running. An angel investor subsequently kicked in $275 thousand followed by a $1.5 million investment from BittWare, a maker of DSP and FPGA boards.

As a chip designer, Olofsson’s principle focus was in DSP designs, which he says is an excellent model for processors that need to optimize data movement and throughput in an extremely energy constrained environment. Unlike a DSP, however, Epiphany is a general-purpose design that can execute any ANSI C programs.

The architecture is a 2D mesh of general-purpose RISC cores hooked up via a high bandwidth, low latency on-chip network. The current implementation has 16 cores, but a 4 thousand core version is already in the works. The design is similar to Tilera‘s manycore chips, but with a singular focus on floating point execution. As Olofsson puts it: “We can run any program out of the box, but where we really shine is floating point processing.”

Specifically, the architecture is designed to run the inner loops of math codes with the utmost efficiency. Workloads like image processing, speech recognition, and any other sort of pattern matching code that relies heavily on vector math is right in Epiphany’s wheelhouse.

Imagine a future iPhone 9 with Epiphany on-board. One might be able to hold a conference call between individuals in the UK, China and India and all three people would hear the conversation in their native language thanks to real-time translation. Or the same phone could take a photo of a crowd of people and on-board image recognition software would instantly identify the faces and tell you who they are. Today, these types of applications are possible on an HPC cluster (or perhaps a really souped up GPU-accelerated workstation), but making them available on mobile devices like smartphones and tablets is still science fiction.

Besides the emphasis on floating point horsepower, the Epiphany design departs from traditional CPUs in a number of ways. To begin with, the processor doesn’t have a hardware cache. Each core has 32 KB of local memory, which is accessible by all the other cores, but access to this memory must be done explicitly in the software. That’s a very different programming model than that used in mainstream CPUs today. “Once you throw away the cache hierarchy, a lot of the inefficiencies of general-purpose architectures go away,” explains Olofsson.

Without the hardware cache, data movement becomes much more efficient. Essentially, the application can perform explicit data copying with zero overhead (no cache misses or copying of unused data). But, Olofsson concedes that this model doesn’t work for the vast majority of legacy codes that assumes there is a “magic cache engine” that brings in the data automatically.

The other big feature of Epiphany is its high performance on-chip interconnect, which allows data to be passed between cores with basically no overhead. In traditional architectures with memory hierarchies, communication costs tend to be extremely high. Here they are essentially free, says Olofsson. With Epiphany’s lightweight processing engines and fat pipes, even very small packets of data can be sent between cores without impacting performance.
 
Olofsson says the optimal software for such an architecture is message passing, but not necessarily MPI, which is designed with interprocessor communication in mind. At least initially, the intent is to adopt MCAPI (Multicore Communications API ), a message passing framework optimized for manycore architectures.

The Epiphany reference design, demonstrated this week at the Multicore Expo in San Jose, California, is a 16-core processor running at a relatively modest 1 GHz, with each core delivering 2 gigaflops. It boasts a peak efficiency of 35 gigaflops/watt, although in this current implementation, we’re talking 32-bit (single precision) FP. Despite that, it outruns the current top-of-the-line gaming GPUs on the market, which in single precision mode, can hit about 10 gigaflops/watt (the latest NVIDIA Tesla part aimed at computing achieves about half that). A conventional CPU like the Power7 delivers about 1.3 gigaflops/watt, while the latest Xeons top out at a modest 0.5 gigaflops/watt.

Although the Adapteva design scrimps on integer smarts, it still claims decent performance in this realm as well. According to Olofsson, a single Epiphany core is nearly equal to a core of the ARM11 MPCore on the CoreMark score. But the Adapteva silicon is not designed to replace ARM or, for that matter, any other general-purpose CPU. These CPUs already run the large code base of sequential codes rather well. Also, Epiphany lacks the memory hierarchy and paging support need to run system-level software like operating systems or hypervisors.

Olofsson thinks the initial big opportunity for Epiphany is in consumer mobile devices and embedded systems for the military, where power efficiency is the overwhelming consideration. But the Adapteva technology not meant to be used as a standalone co-processor, as ClearSpeed tried to do unsuccessfully with its CSX600 offering. Rather Adapteva intends to license the intellectual property (IP) to OEMs and chip vendors.

For mobile devices, in particular, the idea would be for system designers to integrate the Epiphany IP into a more general-purpose design, most likely an ARM implementation. (16 cores of Epiphany would take up just a fraction of the space and power of a high-end ARM chip.) Like AMD’s CPU-GPU Fusion design and NVIDIA’s upcoming “Project Denver” ARM-GPU chips, the Epiphany logic would take the of an on-chip FP accelerator in a heterogenous processor.

The aforementioned BittWare is already OEMing the technology. In this case, the company is using the Epiphany chip as a floating point accelerator on an FPGA-based signal processing board for military application. With the heavy-duty math offloaded to the co-processor, the FPGA is free to concentrate on the non-FP processing part of the application.

Currently, Adapteva offers a bare bones development kit for its hardware, including an GNU-based ANSI C compiler, a gdb debugger, a simulator, and an Eclipse IDE for project management. What’s missing is the runtime model and communication libraries. For that they have secured an unnamed commercial partner who is helping to fill out the software stack, and who, according to Olofsson, has built an environment suitable for programming millions of cores.

Although the 32-bit, 16-core reference design is the only one available today, Adapteva is also working on a 64-bit implementation of the architecture that it’s planning to launch in the second half of the year. At the 28nm node, Olofsson thinks they can get up to 1,000 64-bit floating point cores on the die.

For 32-bit designs, the company has already completed the layout for a 4,096-core implementation on 28nm technology. That version is projected to use just 64 watts of power and deliver more than 4 peak teraflops of compute (so between 50 and 80 gigaflops/watt). Olofsson says this 4K-core design will be ready by the end of 2011.

For the supercomputing crowd looking ahead to exascale hardware, these performance per watt numbers are rather compelling. So much so that Olofsson was invited to present his architecture at symposiums conducted by Los Alamos National Lab and the PRACE organization in Europe. These top tier users expect to build exascale machines that deliver 50 double precision gigaflops/watt in the 2018 timeframe. Since that includes memory and communication hardware, in addition to compute, the processors themselves will have to deliver in excess of 100 gigaflops/watt.

Although mainstream architectures like GPUs and other manycore technologies, like Intel’s MIC processor, may be able to evolve fast enough to serve this purpose, the Epiphany technology could offer a more straight-line path to such performance levels. If Adapteva is able to establish itself in a volume market like smartphones and tablets, the technology could very well end up in our future supercomputers.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “pre-exascale” award), parsed out additional information ab Read more…

By Tiffany Trader

Tsinghua Crowned Eight-Time Student Cluster Champions at ISC

June 22, 2017

Always a hard-fought competition, the Student Cluster Competition awards were announced Wednesday, June 21, at the ISC High Performance Conference 2017. Amid whoops and hollers from the crowd, Thomas Sterling presented t Read more…

By Kim McMahon

GPUs, Power9, Figure Prominently in IBM’s Bet on Weather Forecasting

June 22, 2017

IBM jumped into the weather forecasting business roughly a year and a half ago by purchasing The Weather Company. This week at ISC 2017, Big Blue rolled out plans to push deeper into climate science and develop more gran Read more…

By John Russell

Intersect 360 at ISC: HPC Industry at $44B by 2021

June 22, 2017

The care, feeding and sustained growth of the HPC industry increasingly is in the hands of the commercial market sector – in particular, it’s the hyperscale companies and their embrace of AI and deep learning – tha Read more…

By Doug Black

HPE Extreme Performance Solutions

Creating a Roadmap for HPC Innovation at ISC 2017

In an era where technological advancements are driving innovation to every sector, and powering major economic and scientific breakthroughs, high performance computing (HPC) is crucial to tackle the challenges of today and tomorrow. Read more…

At ISC – Goh on Go: Humans Can’t Scale, the Data-Centric Learning Machine Can

June 22, 2017

I've seen the future this week at ISC, it’s on display in prototype or Powerpoint form, and it’s going to dumbfound you. The future is an AI neural network designed to emulate and compete with the human brain. In thi Read more…

By Doug Black

Cray Brings AI and HPC Together on Flagship Supers

June 20, 2017

Cray took one more step toward the convergence of big data and high performance computing (HPC) today when it announced that it’s adding a full suite of big data and artificial intelligence software to its top-of-the-l Read more…

By Alex Woodie

AMD Charges Back into the Datacenter and HPC Workflows with EPYC Processor

June 20, 2017

AMD is charging back into the enterprise datacenter and select HPC workflows with its new EPYC 7000 processor line, code-named Naples, announced today at a “global” launch event in Austin TX. In many ways it was a fu Read more…

By John Russell

Hyperion: Deep Learning, AI Helping Drive Healthy HPC Industry Growth

June 20, 2017

To be at the ISC conference in Frankfurt this week is to experience deep immersion in deep learning. Users want to learn about it, vendors want to talk about it, analysts and journalists want to report on it. Deep learni Read more…

By Doug Black

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Tsinghua Crowned Eight-Time Student Cluster Champions at ISC

June 22, 2017

Always a hard-fought competition, the Student Cluster Competition awards were announced Wednesday, June 21, at the ISC High Performance Conference 2017. Amid wh Read more…

By Kim McMahon

GPUs, Power9, Figure Prominently in IBM’s Bet on Weather Forecasting

June 22, 2017

IBM jumped into the weather forecasting business roughly a year and a half ago by purchasing The Weather Company. This week at ISC 2017, Big Blue rolled out pla Read more…

By John Russell

Intersect 360 at ISC: HPC Industry at $44B by 2021

June 22, 2017

The care, feeding and sustained growth of the HPC industry increasingly is in the hands of the commercial market sector – in particular, it’s the hyperscale Read more…

By Doug Black

At ISC – Goh on Go: Humans Can’t Scale, the Data-Centric Learning Machine Can

June 22, 2017

I've seen the future this week at ISC, it’s on display in prototype or Powerpoint form, and it’s going to dumbfound you. The future is an AI neural network Read more…

By Doug Black

Cray Brings AI and HPC Together on Flagship Supers

June 20, 2017

Cray took one more step toward the convergence of big data and high performance computing (HPC) today when it announced that it’s adding a full suite of big d Read more…

By Alex Woodie

AMD Charges Back into the Datacenter and HPC Workflows with EPYC Processor

June 20, 2017

AMD is charging back into the enterprise datacenter and select HPC workflows with its new EPYC 7000 processor line, code-named Naples, announced today at a “g Read more…

By John Russell

Hyperion: Deep Learning, AI Helping Drive Healthy HPC Industry Growth

June 20, 2017

To be at the ISC conference in Frankfurt this week is to experience deep immersion in deep learning. Users want to learn about it, vendors want to talk about it Read more…

By Doug Black

Quantum Bits: D-Wave and VW; Google Quantum Lab; IBM Expands Access

March 21, 2017

For a technology that’s usually characterized as far off and in a distant galaxy, quantum computing has been steadily picking up steam. Just how close real-wo Read more…

By John Russell

Trump Budget Targets NIH, DOE, and EPA; No Mention of NSF

March 16, 2017

President Trump’s proposed U.S. fiscal 2018 budget issued today sharply cuts science spending while bolstering military spending as he promised during the cam Read more…

By John Russell

HPC Compiler Company PathScale Seeks Life Raft

March 23, 2017

HPCwire has learned that HPC compiler company PathScale has fallen on difficult times and is asking the community for help or actively seeking a buyer for its a Read more…

By Tiffany Trader

Google Pulls Back the Covers on Its First Machine Learning Chip

April 6, 2017

This week Google released a report detailing the design and performance characteristics of the Tensor Processing Unit (TPU), its custom ASIC for the inference Read more…

By Tiffany Trader

CPU-based Visualization Positions for Exascale Supercomputing

March 16, 2017

In this contributed perspective piece, Intel’s Jim Jeffers makes the case that CPU-based visualization is now widely adopted and as such is no longer a contrarian view, but is rather an exascale requirement. Read more…

By Jim Jeffers, Principal Engineer and Engineering Leader, Intel

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Nvidia’s Mammoth Volta GPU Aims High for AI, HPC

May 10, 2017

At Nvidia's GPU Technology Conference (GTC17) in San Jose, Calif., this morning, CEO Jensen Huang announced the company's much-anticipated Volta architecture a Read more…

By Tiffany Trader

Facebook Open Sources Caffe2; Nvidia, Intel Rush to Optimize

April 18, 2017

From its F8 developer conference in San Jose, Calif., today, Facebook announced Caffe2, a new open-source, cross-platform framework for deep learning. Caffe2 is the successor to Caffe, the deep learning framework developed by Berkeley AI Research and community contributors. Read more…

By Tiffany Trader

Leading Solution Providers

MIT Mathematician Spins Up 220,000-Core Google Compute Cluster

April 21, 2017

On Thursday, Google announced that MIT math professor and computational number theorist Andrew V. Sutherland had set a record for the largest Google Compute Engine (GCE) job. Sutherland ran the massive mathematics workload on 220,000 GCE cores using preemptible virtual machine instances. Read more…

By Tiffany Trader

Google Debuts TPU v2 and will Add to Google Cloud

May 25, 2017

Not long after stirring attention in the deep learning/AI community by revealing the details of its Tensor Processing Unit (TPU), Google last week announced the Read more…

By John Russell

US Supercomputing Leaders Tackle the China Question

March 15, 2017

Joint DOE-NSA report responds to the increased global pressures impacting the competitiveness of U.S. supercomputing. Read more…

By Tiffany Trader

Russian Researchers Claim First Quantum-Safe Blockchain

May 25, 2017

The Russian Quantum Center today announced it has overcome the threat of quantum cryptography by creating the first quantum-safe blockchain, securing cryptocurrencies like Bitcoin, along with classified government communications and other sensitive digital transfers. Read more…

By Doug Black

Groq This: New AI Chips to Give GPUs a Run for Deep Learning Money

April 24, 2017

CPUs and GPUs, move over. Thanks to recent revelations surrounding Google’s new Tensor Processing Unit (TPU), the computing world appears to be on the cusp of Read more…

By Alex Woodie

DOE Supercomputer Achieves Record 45-Qubit Quantum Simulation

April 13, 2017

In order to simulate larger and larger quantum systems and usher in an age of “quantum supremacy,” researchers are stretching the limits of today’s most advanced supercomputers. Read more…

By Tiffany Trader

Messina Update: The US Path to Exascale in 16 Slides

April 26, 2017

Paul Messina, director of the U.S. Exascale Computing Project, provided a wide-ranging review of ECP’s evolving plans last week at the HPC User Forum. Read more…

By John Russell

Knights Landing Processor with Omni-Path Makes Cloud Debut

April 18, 2017

HPC cloud specialist Rescale is partnering with Intel and HPC resource provider R Systems to offer first-ever cloud access to Xeon Phi "Knights Landing" processors. The infrastructure is based on the 68-core Intel Knights Landing processor with integrated Omni-Path fabric (the 7250F Xeon Phi). Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This