Startup Launches Manycore Floating Point Acceleration Technology

By Michael Feldman

May 3, 2011

Semiconductor startup Adapteva has demonstrated a manycore floating point processor architecture that promises ten times the performance per watt as the best chip technology on the market today. The architecture, called Epiphany, is aimed initially at embedded applications, but has general applicability across all math-intensive workloads in mobile computing, telecommunications and high performance computing.

Epiphany is the brainchild of Adapteva CEO and founder Andreas Olofsson, who spent nearly 15 years as chip designer, first at for Texas Instruments and later at Analog Devices. Olofsson has managed to bootstrap his company with less than $2 million, initially paying out of his own pocket to get the company up and running. An angel investor subsequently kicked in $275 thousand followed by a $1.5 million investment from BittWare, a maker of DSP and FPGA boards.

As a chip designer, Olofsson’s principle focus was in DSP designs, which he says is an excellent model for processors that need to optimize data movement and throughput in an extremely energy constrained environment. Unlike a DSP, however, Epiphany is a general-purpose design that can execute any ANSI C programs.

The architecture is a 2D mesh of general-purpose RISC cores hooked up via a high bandwidth, low latency on-chip network. The current implementation has 16 cores, but a 4 thousand core version is already in the works. The design is similar to Tilera‘s manycore chips, but with a singular focus on floating point execution. As Olofsson puts it: “We can run any program out of the box, but where we really shine is floating point processing.”

Specifically, the architecture is designed to run the inner loops of math codes with the utmost efficiency. Workloads like image processing, speech recognition, and any other sort of pattern matching code that relies heavily on vector math is right in Epiphany’s wheelhouse.

Imagine a future iPhone 9 with Epiphany on-board. One might be able to hold a conference call between individuals in the UK, China and India and all three people would hear the conversation in their native language thanks to real-time translation. Or the same phone could take a photo of a crowd of people and on-board image recognition software would instantly identify the faces and tell you who they are. Today, these types of applications are possible on an HPC cluster (or perhaps a really souped up GPU-accelerated workstation), but making them available on mobile devices like smartphones and tablets is still science fiction.

Besides the emphasis on floating point horsepower, the Epiphany design departs from traditional CPUs in a number of ways. To begin with, the processor doesn’t have a hardware cache. Each core has 32 KB of local memory, which is accessible by all the other cores, but access to this memory must be done explicitly in the software. That’s a very different programming model than that used in mainstream CPUs today. “Once you throw away the cache hierarchy, a lot of the inefficiencies of general-purpose architectures go away,” explains Olofsson.

Without the hardware cache, data movement becomes much more efficient. Essentially, the application can perform explicit data copying with zero overhead (no cache misses or copying of unused data). But, Olofsson concedes that this model doesn’t work for the vast majority of legacy codes that assumes there is a “magic cache engine” that brings in the data automatically.

The other big feature of Epiphany is its high performance on-chip interconnect, which allows data to be passed between cores with basically no overhead. In traditional architectures with memory hierarchies, communication costs tend to be extremely high. Here they are essentially free, says Olofsson. With Epiphany’s lightweight processing engines and fat pipes, even very small packets of data can be sent between cores without impacting performance.
 
Olofsson says the optimal software for such an architecture is message passing, but not necessarily MPI, which is designed with interprocessor communication in mind. At least initially, the intent is to adopt MCAPI (Multicore Communications API ), a message passing framework optimized for manycore architectures.

The Epiphany reference design, demonstrated this week at the Multicore Expo in San Jose, California, is a 16-core processor running at a relatively modest 1 GHz, with each core delivering 2 gigaflops. It boasts a peak efficiency of 35 gigaflops/watt, although in this current implementation, we’re talking 32-bit (single precision) FP. Despite that, it outruns the current top-of-the-line gaming GPUs on the market, which in single precision mode, can hit about 10 gigaflops/watt (the latest NVIDIA Tesla part aimed at computing achieves about half that). A conventional CPU like the Power7 delivers about 1.3 gigaflops/watt, while the latest Xeons top out at a modest 0.5 gigaflops/watt.

Although the Adapteva design scrimps on integer smarts, it still claims decent performance in this realm as well. According to Olofsson, a single Epiphany core is nearly equal to a core of the ARM11 MPCore on the CoreMark score. But the Adapteva silicon is not designed to replace ARM or, for that matter, any other general-purpose CPU. These CPUs already run the large code base of sequential codes rather well. Also, Epiphany lacks the memory hierarchy and paging support need to run system-level software like operating systems or hypervisors.

Olofsson thinks the initial big opportunity for Epiphany is in consumer mobile devices and embedded systems for the military, where power efficiency is the overwhelming consideration. But the Adapteva technology not meant to be used as a standalone co-processor, as ClearSpeed tried to do unsuccessfully with its CSX600 offering. Rather Adapteva intends to license the intellectual property (IP) to OEMs and chip vendors.

For mobile devices, in particular, the idea would be for system designers to integrate the Epiphany IP into a more general-purpose design, most likely an ARM implementation. (16 cores of Epiphany would take up just a fraction of the space and power of a high-end ARM chip.) Like AMD’s CPU-GPU Fusion design and NVIDIA’s upcoming “Project Denver” ARM-GPU chips, the Epiphany logic would take the of an on-chip FP accelerator in a heterogenous processor.

The aforementioned BittWare is already OEMing the technology. In this case, the company is using the Epiphany chip as a floating point accelerator on an FPGA-based signal processing board for military application. With the heavy-duty math offloaded to the co-processor, the FPGA is free to concentrate on the non-FP processing part of the application.

Currently, Adapteva offers a bare bones development kit for its hardware, including an GNU-based ANSI C compiler, a gdb debugger, a simulator, and an Eclipse IDE for project management. What’s missing is the runtime model and communication libraries. For that they have secured an unnamed commercial partner who is helping to fill out the software stack, and who, according to Olofsson, has built an environment suitable for programming millions of cores.

Although the 32-bit, 16-core reference design is the only one available today, Adapteva is also working on a 64-bit implementation of the architecture that it’s planning to launch in the second half of the year. At the 28nm node, Olofsson thinks they can get up to 1,000 64-bit floating point cores on the die.

For 32-bit designs, the company has already completed the layout for a 4,096-core implementation on 28nm technology. That version is projected to use just 64 watts of power and deliver more than 4 peak teraflops of compute (so between 50 and 80 gigaflops/watt). Olofsson says this 4K-core design will be ready by the end of 2011.

For the supercomputing crowd looking ahead to exascale hardware, these performance per watt numbers are rather compelling. So much so that Olofsson was invited to present his architecture at symposiums conducted by Los Alamos National Lab and the PRACE organization in Europe. These top tier users expect to build exascale machines that deliver 50 double precision gigaflops/watt in the 2018 timeframe. Since that includes memory and communication hardware, in addition to compute, the processors themselves will have to deliver in excess of 100 gigaflops/watt.

Although mainstream architectures like GPUs and other manycore technologies, like Intel’s MIC processor, may be able to evolve fast enough to serve this purpose, the Epiphany technology could offer a more straight-line path to such performance levels. If Adapteva is able to establish itself in a volume market like smartphones and tablets, the technology could very well end up in our future supercomputers.

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