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May 5, 2011

The Weekly Top Five

Tiffany Trader

The Weekly Top Five features the five biggest HPC stories of the week, condensed for your reading pleasure. This week we cover ISRO’s newest supercomputer; Tokyo Tech’s selection of EM Photonics’ CULA library; Intel’s 3-D transistor breakthrough; the latest LSF Tools from Platform Computing; and SciNet’s new NextIO GPU-based system.

Indian Supercomputing SAGA

This week the Indian Space Research Organisation (ISRO) launched that nation’s fastest computer — “SAGA-220” — which stands for “Supercomputer for Aerospace with GPU Architecture-220 teraflops.” The new system relies heavily on GPUs to achieve its eponymous theoretical peak speed of 220 teraflops, which will be put to work solving complex aerospace problems.

The Vikram Sarabhai Space Centre along with vendor partner, Wipro, Ltd., designed and built the supercomputer using commodity hardware and open source software components at a cost of about $3.1 million (Rs. 14 crores). SAGA-220 contains 400 NVIDIA Tesla 2070 GPUs and 400 Intel quad-core Xeon CPUs, linked with a high speed interconnect. Each GPU and CPU provides a performance of 500 gigaflops and 50 gigaflops respectively, adding up to the 220 teraflop mark. The GPUs also help the system achieve a stated power consumption of 150 kW, and the ISRO representatives explain that minimizing environmental impact was one of their goals. The architecture design intentially allows for future upgrades, which could eventually lead to petascale performance.

SAGA-220 will reside at Satish Dhawan Supercomputing Facility, which is part of the Vikram Sarabhai Space Centre (VSSC), in Thiruvananthapuram, India.

HPCwire presents feature coverage of the SAGA-220 debut, here.

Tokyo Tech Selects CULA Library for TSUBAME 2.0

EM Photonics announced that the Tokyo Institute of Technology’s supercomputer, TSUBAME 2.0, will be using CULA tools as part of a four-year licensing agreement, providing the system’s users with the most current version of the software. The arrangement was brokered by one of EM Photonics’ major resellers, Best Systems, which works with many Japanese academic and government institutions.

CULA was developed by a team of engineers at EM Photonics in partnership with NVIDIA. It leverages NVIDIA’s CUDA architecture to improve the performance of linear algebra fuctions.

The Tokyo Institute of Technology (Tokyo Tech), the largest science and technology university in Japan, is home to the TSUBAME 2.0 supercomputer, Japan’s first petascale system, which occupies the fourth spot on the TOP500 list of the world’s fastest sypercomputers.

TSUBAME 2.0 relies on GPU computing to achieve its powerful performance level, and as such it required a tool capable of tapping the power of the CUDA architecture. Professor Satoshi Matsuoka, TSUBAME 2.0 project lead, explained:

“The majority of the achievable FLOPS in TSUBAME 2.0 is due to the power of the GPUs, so it is essential that we provide as comprehensive a software stack to utilize them to their fullest potential as possible. CULA will be an extremely valuable part of the portfolio, allowing our scientists to conduct large scale simulations at unprecedented speeds.”

Intel Brings Transistor Into Third-Dimension

The wait for a commercial 3-D transistor is over and Intel was first to cross the finish line when it announced its intention to mass produce transistors with a three-dimensional structure, called Tri-Gate. According to Intel reps, this advancement will extend Moore’s Law for years to come. Intel first revealed its 3-D processor strategy in 2002, and is now finally entering the high-volume manufacturing stage for the 22-nanometer (nm) node in an Intel chip codenamed “Ivy Bridge.”

The company explains that the revolutionary transistor design will allow chips to function better with less power, a good profile for a variety of devices, from the smallest handhelds to massive distributed (cloud) servers.

HPCwire Editor Michael Feldman provides further coverage of this significant development in chip design, and helps explain why a third dimension was necessary.

The problem is that as semiconductor geometries shrink, it gets increasingly difficult to prevent the electrons from leaking out of the gates, especially at higher voltages. The solution was to build up them up into three-dimensional fin structures so they can be wrapped around the channel, making it more difficult for the electrons to escape. Essentially they’ve blocked the electrons on three sides instead of the one in the flat transistor.

The 3-D Tri-Gate transistor will be implemented in the company’s forthcoming manufacturing process, called the 22nm node, a reference to the size of individual transistor features. To illustrate just how small this is, the company explains that “more than 6 million 22nm Tri-Gate transistors could fit in the period at the end of this sentence.”

Platform Revs LSF Tools

On the heels of last week’s Platform Symphony upgrade, Platform Computing is now announcing new versions of two LSF product family tools designed to meet the workload management needs of HPC and IT administrators. According to the release: “Platform RTM 8 is a comprehensive operational dashboard that provides administrators with the information and tools needed to maximize cluster efficiency,” and “Platform Analytics 8 is an advanced analysis and visualization tool that provides the insight needed to quickly identify and troubleshoot bottlenecks and analyze usage trends within the HPC datacenter.”

Platform RTM offers monitoring across all workload aspects, including global clusters, hosts, licenses queues, users and log files. Features highlighted in the latest release include a single-view, intuitive dashboard; multi-cluster support; resource consumption monitoring; resource monitoring by user, group or team; and automated alerts and exception handling aimed at improving cluster availability. Platform Analytics 8 helps create actionable information from raw business data. Key features include an enhanced graphical interface; a configurable dashboard view; multi-level analysis; an open architecture that integrates HPC datacenter and job-related data with external data sources; and the ability to accommodate thousands of users and millions of jobs.

Several Platform customers provided feedback in support of the new releases, including Cadence Design Systems, Red Bull Racing, and Simulia. Here’s what Steve MacQuiddy, IT director engineering infrastructure at Cadence, reported: “The ability to monitor cluster availability and performance is imperative when we’re running millions of design simulations to test our latest software releases. Having the single Platform RTM dashboard allows us to simultaneously observe the entire cluster environment and it has not only made it easier for us to better balance our workloads, but it’s also helped us optimize throughput for our critical jobs during peak usage.”

NextIO GPU Computing Solution Doubles Memory Capability for SciNet System

The SciNet Consortium at the University of Toronto is relying on NextIO’s vCORE Express 2070 GPU systems to boost their computing power, enabling greater potential for scientific breakthroughs. The SciNet researchers required a powerful and flexible GPU system that would allow them to solve difficult computing challenges in the study of astrophysics, aerospace, cosmology simulations and computational combustion. The NextIO solution provides faster GPU memory, doubling the amount of memory available for simulations, helping researchers process the kinematic measurements of cosmic history, or make predictions related to combusting and multiphase flows involved in aerospace propulsion systems.

NextIO’s vCORE Express uses NVIDIA Tesla 20-Series GPUs and was designed specifically for parallel computing applications. Dr. Chris Loken, SciNet’s chief technical officer, explained in the announcement that the vCORE system was an “obvious choice,” as “these systems certainly give us better density and more memory per dollar in addition to a tremendous amount of flexibility that can be leveraged in variables for different high compute problems.”

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