Intel Touts Manycore Coprocessor at Supercomputing Conference

By Michael Feldman

June 20, 2011

Today at the International Supercomputing Conference (ISC) in Hamburg, Germany, Intel outlined the progress it has made over the last year toward bringing its Many Integrated Core (MIC) coprocessor platform to market. MIC is Intel’s answer to general-purpose GPU computing, and like the latter technology, Intel believes it can parlay the its manycore design into future exascale systems.

Recycling the design from the aborted Larrabee graphics processor effort, MIC was recast as an high performance coprocessor for HPC. This product redirection was unveiled in May 2010 during last year’s ISC event. Since then Intel has been passing out MIC software development platforms (SDPs) to selected users in the HPC community.

An SDP is basically a Knights Ferry coprocessor card (the MIC prototype) with up to two GB of GDDR5 memory. The card is hooked up, via PCIe, to a host system with one or more Xeon CPUs.

In a press briefing on June 14, Anthony Neal-Graves, Intel VP and General Manager of Workstations and MIC Computing, reported that at this time last year, they had 10 users running code on Knights Ferry platform. By the end of this month, they’ll have about 50 such users, with the goal of hitting 100 by the end of 2011. According to Neal-Graves, everything was on track for the launch of the first commercial MIC product, known as Knights Corner.

Knights Corner, he said, would arrive in 2012 using Intel’s newly hatched tri-gate 22nm process node. With perhaps an indirect inference to NVIDIA’s and AMD’s GPU computing prowess, Neal-Graves noted that they’ll be able to use their 22nm technology to deliver cheaper, faster and more power-efficient silicon than their competition, adding, “That’s really going to bring the performance to the table that we really need for these types of solutions.”

Performance-wise, MIC has to be able to hit a rather fast-moving target thanks to NVIDIA and AMD upping the FLOPS count for GPUs over the last few years. There are not a lot of performance metrics available for the Knights Ferry prototype, but Intel does claim a one teraflop value for the SGEMM benchmark (measuring a simple single precision matrix multiply). An equivalent value for the latest NVIDIA Tesla part, the M2090, would probably be in the neighborhood of 800 to 900 gigaflops, and perhaps twice that for the the FireStream 9370.

Since Knights Ferry is a 32-core processor (on 45nm technology), the 50-plus-core Knights Corner commercial product coming out next year should easily double the performance numbers of the prototype. But 2012 will also see the introduction of NVIDIA’s “Kepler” GPU, an architecture that aims to triple the performance of the current generation Fermi parts. Also, since Intel has not released any performance numbers for double precision floating point code, it remains to be seen how MIC will perform in this important realm.

Regardless of how the FLOPS shake out, Intel’s is claiming their biggest advantage will be on the software side, since they are promising MIC support under the chipmaker’s existing x86 developer toolset. Specifically, the company is inserting MIC support in their C and Fortran compilers, debuggers, libraries, and even their more exotic offerings, like Cilk Plus, and Threading Building Blocks. And since MIC is fundamentally an x86 manycore processor (with 512-bit wide vector units), even the low-level code structures are similar. The idea is to provide a common programming environment for the x86 developer, or as Neal-Graves put it: “If you can program a Xeon, you can program a MIC processor.”

For simple pieces of code, like the aforementioned SGEMM function, the 18 lines of code that performed the matrix math was identical for the Xeon and Knights Ferry versions. In this case, the Intel compiler and Math Kernel Library (MKL) performed the heavy lifting to execute the Xeon- or MIC-specific code as appropriate.

That shouldn’t lull developers into thinking they can recompile an entire application for MIC. In most cases, they are going to have to modify the source to parallelize their code or the coprocess. If the existing code is already instrumented with OpenMP directives, developers should have a leg up. Intel has implemented OpenMP support for MIC, along with some directive extensions to deal with the coprocessor setup. In general though, the developer can apply the same OpenMP task parallelization model they used for Xeon to MIC.

In fact, the Innovative Systems Lab (ISL) at the National Center for Supercomputing Applications (NCSA) has ported a couple of science codes to Knights Ferry — one a benchmark code, the other a full astronomy application. The benchmark code was used get familar with the software development process, while the astronomy code was a proof-of-concept test for a full application port.

According to Mike Showerman, the Technical Program Manager at ISL, the application code was already written with accelerators in mind, so the initial port was relatively straightforward. Much of effort (which is still ongoing) involves tuning the code to optimize MIC vectorization. The current Intel compiler performs some MIC auto-vectorization for MIC, but support for the coprocessor not fully baked yet. In fact, most of the components of the MIC software stack are in the “alpha” stage at this point.

Other demonstration of MIC-ported applications, and which will be on display at ISC this week, include an SMMP protein folding application by Forschungszentrum Juelich; a molecular dynamics code at KISTI (Korea Institute of Science & Technology Information); a TifaMMy matrix multiplication code at LRZ (Leibniz Supercomputing Center); and a core scaling benchmark from CERN.

Besides priming the pump for future MIC customers, Intel is also lining up system vendors. At ISC, Knights Ferry systems will be showcased by SGI, IBM, HP, Dell, Colfax, and Supermicro. That’s a quite a bit of vendor enthusiasm, considering this is just prototype hardware, and reflects Intel’s pull in the industry.

Besides confirming that the first MIC product would indeed be on 22nm technology, the press briefing last week gave no new details on Knights Corner. But it’s reasonable to speculate to the 2012 product will support PCIe 3.0 since the new PCI interface should shipping with most new servers by next year (not to mention that the Sandy Bridge Xeons are rumored to incorporate that technology on-chip). Also, no mention was made about ECC memory support, but given ECC is a requirement for serious HPC, and the NVIDIA Fermi Tesla GPUs already support it, it’s almost inconceivable that MIC would be launched without it.

As far as when the actual product would be released in 2012, that was left open. However since Intel has made its two MIC major announcements at ISC, it wouldn’t be surprising if they used next year’s conference to launch Knights Corner.

Beyond that first product, Intel has provided no roadmap. A logical next step would be an integrated Xeon-MIC processor, a la AMD’s Fusion APU and NVIDIA’s ‘Project Denver’ chips, but Intel has been tight-lipped about any such architecture, at least publicly. But given the performance and software friendliness of a unified memory space, heterogeneous processor, Intel has got to be thinking about it.

An integrated Xeon-MIC chip could certainly provide a viable platform for exascale supercomputers, and there is no doubt that Intel wants to be a play in this space. During the press briefing, Neal-Graves repeatedly talked about MIC and exascale in the same breath. The chipmaker’s interest in exascale computing is nothing new, but linking it to a particular architecture certainly is.

“We will be investing in the technology and software capabilities to really bring exascale to reality,” said Neal-Graves. “We’re extremely committed to that and we’re going to make that happen.”

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Nvidia Rolls Out Certified Server Program Targeting AI Applications

January 26, 2021

Nvidia today launched a certified systems program in which participating vendors can offer Nvidia-certified servers with up to eight A100 GPUs. Separate support contracts directly from Nvidia for the certified systems ar Read more…

By John Russell

XSEDE Supercomputers Square Off Against Ebola

January 26, 2021

COVID-19 may have dominated headlines and occupied much of the world’s scientific computing capacity over the last year, but many researchers continued their work to keep other deadly viruses at bay. One of those, Ebol Read more…

By Oliver Peckham

What’s New in HPC Research: Galaxies, Fugaku, Electron Microscopes & More

January 25, 2021

In this regular feature, HPCwire highlights newly published research in the high-performance computing community and related domains. From parallel programming to exascale to quantum computing, the details are here. Read more…

By Oliver Peckham

Red Hat’s Disruption of CentOS Unleashes Storm of Dissent

January 22, 2021

Five weeks after angering much of the CentOS Linux developer community by unveiling controversial changes to the no-cost CentOS operating system, Red Hat has unveiled alternatives for affected users that give them severa Read more…

By Todd R. Weiss

China Unveils First 7nm Chip: Big Island

January 22, 2021

Shanghai Tianshu Zhaoxin Semiconductor Co. is claiming China’s first 7-nanometer chip, described as a leading-edge, general-purpose cloud computing chip based on a proprietary GPU architecture. Dubbed “Big Island Read more…

By George Leopold

AWS Solution Channel

Fire Dynamics Simulation CFD workflow on AWS

Modeling fires is key for many industries, from the design of new buildings, defining evacuation procedures for trains, planes and ships, and even the spread of wildfires. Read more…

HiPEAC Keynote: In-Memory Computing Steps Closer to Practical Reality

January 21, 2021

Pursuit of in-memory computing has long been an active area with recent progress showing promise. Just how in-memory computing works, how close it is to practical application, and what are some of the key opportunities a Read more…

By John Russell

Nvidia Rolls Out Certified Server Program Targeting AI Applications

January 26, 2021

Nvidia today launched a certified systems program in which participating vendors can offer Nvidia-certified servers with up to eight A100 GPUs. Separate support Read more…

By John Russell

Red Hat’s Disruption of CentOS Unleashes Storm of Dissent

January 22, 2021

Five weeks after angering much of the CentOS Linux developer community by unveiling controversial changes to the no-cost CentOS operating system, Red Hat has un Read more…

By Todd R. Weiss

HiPEAC Keynote: In-Memory Computing Steps Closer to Practical Reality

January 21, 2021

Pursuit of in-memory computing has long been an active area with recent progress showing promise. Just how in-memory computing works, how close it is to practic Read more…

By John Russell

HiPEAC’s Vision for a New Cyber Era, a ‘Continuum of Computing’

January 21, 2021

Earlier this week (Jan. 19), HiPEAC — the European Network on High Performance and Embedded Architecture and Compilation — published the 8th edition of the HiPEAC Vision, detailing an increasingly interconnected computing landscape where complex tasks are carried out across multiple... Read more…

By Tiffany Trader

Saudi Aramco Unveils Dammam 7, Its New Top Ten Supercomputer

January 21, 2021

By revenue, oil and gas giant Saudi Aramco is one of the largest companies in the world, and it has historically employed commensurate amounts of supercomputing Read more…

By Oliver Peckham

President-elect Biden Taps Eric Lander and Deep Team on Science Policy

January 19, 2021

Last Friday U.S. President-elect Joe Biden named The Broad Institute founding director and president Eric Lander as his science advisor and as director of the Office of Science and Technology Policy. Lander, 63, is a mathematician by training and distinguished life sciences... Read more…

By John Russell

Pat Gelsinger Returns to Intel as CEO

January 14, 2021

The Intel board of directors has appointed a new CEO. Intel alum Pat Gelsinger is leaving his post as CEO of VMware to rejoin the company that he parted ways with 11 years ago. Gelsinger will succeed Bob Swan, who will remain CEO until Feb. 15. Gelsinger previously spent 30 years... Read more…

By Tiffany Trader

Julia Update: Adoption Keeps Climbing; Is It a Python Challenger?

January 13, 2021

The rapid adoption of Julia, the open source, high level programing language with roots at MIT, shows no sign of slowing according to data from Julialang.org. I Read more…

By John Russell

Julia Update: Adoption Keeps Climbing; Is It a Python Challenger?

January 13, 2021

The rapid adoption of Julia, the open source, high level programing language with roots at MIT, shows no sign of slowing according to data from Julialang.org. I Read more…

By John Russell

Esperanto Unveils ML Chip with Nearly 1,100 RISC-V Cores

December 8, 2020

At the RISC-V Summit today, Art Swift, CEO of Esperanto Technologies, announced a new, RISC-V based chip aimed at machine learning and containing nearly 1,100 low-power cores based on the open-source RISC-V architecture. Esperanto Technologies, headquartered in... Read more…

By Oliver Peckham

Azure Scaled to Record 86,400 Cores for Molecular Dynamics

November 20, 2020

A new record for HPC scaling on the public cloud has been achieved on Microsoft Azure. Led by Dr. Jer-Ming Chia, the cloud provider partnered with the Beckman I Read more…

By Oliver Peckham

NICS Unleashes ‘Kraken’ Supercomputer

April 4, 2008

A Cray XT4 supercomputer, dubbed Kraken, is scheduled to come online in mid-summer at the National Institute for Computational Sciences (NICS). The soon-to-be petascale system, and the resulting NICS organization, are the result of an NSF Track II award of $65 million to the University of Tennessee and its partners to provide next-generation supercomputing for the nation's science community. Read more…

Is the Nvidia A100 GPU Performance Worth a Hardware Upgrade?

October 16, 2020

Over the last decade, accelerators have seen an increasing rate of adoption in high-performance computing (HPC) platforms, and in the June 2020 Top500 list, eig Read more…

By Hartwig Anzt, Ahmad Abdelfattah and Jack Dongarra

Aurora’s Troubles Move Frontier into Pole Exascale Position

October 1, 2020

Intel’s 7nm node delay has raised questions about the status of the Aurora supercomputer that was scheduled to be stood up at Argonne National Laboratory next year. Aurora was in the running to be the United States’ first exascale supercomputer although it was on a contemporaneous timeline with... Read more…

By Tiffany Trader

10nm, 7nm, 5nm…. Should the Chip Nanometer Metric Be Replaced?

June 1, 2020

The biggest cool factor in server chips is the nanometer. AMD beating Intel to a CPU built on a 7nm process node* – with 5nm and 3nm on the way – has been i Read more…

By Doug Black

Programming the Soon-to-Be World’s Fastest Supercomputer, Frontier

January 5, 2021

What’s it like designing an app for the world’s fastest supercomputer, set to come online in the United States in 2021? The University of Delaware’s Sunita Chandrasekaran is leading an elite international team in just that task. Chandrasekaran, assistant professor of computer and information sciences, recently was named... Read more…

By Tracey Bryant

Leading Solution Providers

Contributors

Top500: Fugaku Keeps Crown, Nvidia’s Selene Climbs to #5

November 16, 2020

With the publication of the 56th Top500 list today from SC20's virtual proceedings, Japan's Fugaku supercomputer – now fully deployed – notches another win, Read more…

By Tiffany Trader

Texas A&M Announces Flagship ‘Grace’ Supercomputer

November 9, 2020

Texas A&M University has announced its next flagship system: Grace. The new supercomputer, named for legendary programming pioneer Grace Hopper, is replacing the Ada system (itself named for mathematician Ada Lovelace) as the primary workhorse for Texas A&M’s High Performance Research Computing (HPRC). Read more…

By Oliver Peckham

At Oak Ridge, ‘End of Life’ Sometimes Isn’t

October 31, 2020

Sometimes, the old dog actually does go live on a farm. HPC systems are often cursed with short lifespans, as they are continually supplanted by the latest and Read more…

By Oliver Peckham

Gordon Bell Special Prize Goes to Massive SARS-CoV-2 Simulations

November 19, 2020

2020 has proven a harrowing year – but it has produced remarkable heroes. To that end, this year, the Association for Computing Machinery (ACM) introduced the Read more…

By Oliver Peckham

Nvidia and EuroHPC Team for Four Supercomputers, Including Massive ‘Leonardo’ System

October 15, 2020

The EuroHPC Joint Undertaking (JU) serves as Europe’s concerted supercomputing play, currently comprising 32 member states and billions of euros in funding. I Read more…

By Oliver Peckham

Intel Xe-HP GPU Deployed for Aurora Exascale Development

November 17, 2020

At SC20, Intel announced that it is making its Xe-HP high performance discrete GPUs available to early access developers. Notably, the new chips have been deplo Read more…

By Tiffany Trader

Nvidia-Arm Deal a Boon for RISC-V?

October 26, 2020

The $40 billion blockbuster acquisition deal that will bring chipmaker Arm into the Nvidia corporate family could provide a boost for the competing RISC-V architecture. As regulators in the U.S., China and the European Union begin scrutinizing the impact of the blockbuster deal on semiconductor industry competition and innovation, the deal has at the very least... Read more…

By George Leopold

HPE, AMD and EuroHPC Partner for Pre-Exascale LUMI Supercomputer

October 21, 2020

Not even a week after Nvidia announced that it would be providing hardware for the first four of the eight planned EuroHPC systems, HPE and AMD are announcing a Read more…

By Oliver Peckham

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This