Intel Touts Manycore Coprocessor at Supercomputing Conference

By Michael Feldman

June 20, 2011

Today at the International Supercomputing Conference (ISC) in Hamburg, Germany, Intel outlined the progress it has made over the last year toward bringing its Many Integrated Core (MIC) coprocessor platform to market. MIC is Intel’s answer to general-purpose GPU computing, and like the latter technology, Intel believes it can parlay the its manycore design into future exascale systems.

Recycling the design from the aborted Larrabee graphics processor effort, MIC was recast as an high performance coprocessor for HPC. This product redirection was unveiled in May 2010 during last year’s ISC event. Since then Intel has been passing out MIC software development platforms (SDPs) to selected users in the HPC community.

An SDP is basically a Knights Ferry coprocessor card (the MIC prototype) with up to two GB of GDDR5 memory. The card is hooked up, via PCIe, to a host system with one or more Xeon CPUs.

In a press briefing on June 14, Anthony Neal-Graves, Intel VP and General Manager of Workstations and MIC Computing, reported that at this time last year, they had 10 users running code on Knights Ferry platform. By the end of this month, they’ll have about 50 such users, with the goal of hitting 100 by the end of 2011. According to Neal-Graves, everything was on track for the launch of the first commercial MIC product, known as Knights Corner.

Knights Corner, he said, would arrive in 2012 using Intel’s newly hatched tri-gate 22nm process node. With perhaps an indirect inference to NVIDIA’s and AMD’s GPU computing prowess, Neal-Graves noted that they’ll be able to use their 22nm technology to deliver cheaper, faster and more power-efficient silicon than their competition, adding, “That’s really going to bring the performance to the table that we really need for these types of solutions.”

Performance-wise, MIC has to be able to hit a rather fast-moving target thanks to NVIDIA and AMD upping the FLOPS count for GPUs over the last few years. There are not a lot of performance metrics available for the Knights Ferry prototype, but Intel does claim a one teraflop value for the SGEMM benchmark (measuring a simple single precision matrix multiply). An equivalent value for the latest NVIDIA Tesla part, the M2090, would probably be in the neighborhood of 800 to 900 gigaflops, and perhaps twice that for the the FireStream 9370.

Since Knights Ferry is a 32-core processor (on 45nm technology), the 50-plus-core Knights Corner commercial product coming out next year should easily double the performance numbers of the prototype. But 2012 will also see the introduction of NVIDIA’s “Kepler” GPU, an architecture that aims to triple the performance of the current generation Fermi parts. Also, since Intel has not released any performance numbers for double precision floating point code, it remains to be seen how MIC will perform in this important realm.

Regardless of how the FLOPS shake out, Intel’s is claiming their biggest advantage will be on the software side, since they are promising MIC support under the chipmaker’s existing x86 developer toolset. Specifically, the company is inserting MIC support in their C and Fortran compilers, debuggers, libraries, and even their more exotic offerings, like Cilk Plus, and Threading Building Blocks. And since MIC is fundamentally an x86 manycore processor (with 512-bit wide vector units), even the low-level code structures are similar. The idea is to provide a common programming environment for the x86 developer, or as Neal-Graves put it: “If you can program a Xeon, you can program a MIC processor.”

For simple pieces of code, like the aforementioned SGEMM function, the 18 lines of code that performed the matrix math was identical for the Xeon and Knights Ferry versions. In this case, the Intel compiler and Math Kernel Library (MKL) performed the heavy lifting to execute the Xeon- or MIC-specific code as appropriate.

That shouldn’t lull developers into thinking they can recompile an entire application for MIC. In most cases, they are going to have to modify the source to parallelize their code or the coprocess. If the existing code is already instrumented with OpenMP directives, developers should have a leg up. Intel has implemented OpenMP support for MIC, along with some directive extensions to deal with the coprocessor setup. In general though, the developer can apply the same OpenMP task parallelization model they used for Xeon to MIC.

In fact, the Innovative Systems Lab (ISL) at the National Center for Supercomputing Applications (NCSA) has ported a couple of science codes to Knights Ferry — one a benchmark code, the other a full astronomy application. The benchmark code was used get familar with the software development process, while the astronomy code was a proof-of-concept test for a full application port.

According to Mike Showerman, the Technical Program Manager at ISL, the application code was already written with accelerators in mind, so the initial port was relatively straightforward. Much of effort (which is still ongoing) involves tuning the code to optimize MIC vectorization. The current Intel compiler performs some MIC auto-vectorization for MIC, but support for the coprocessor not fully baked yet. In fact, most of the components of the MIC software stack are in the “alpha” stage at this point.

Other demonstration of MIC-ported applications, and which will be on display at ISC this week, include an SMMP protein folding application by Forschungszentrum Juelich; a molecular dynamics code at KISTI (Korea Institute of Science & Technology Information); a TifaMMy matrix multiplication code at LRZ (Leibniz Supercomputing Center); and a core scaling benchmark from CERN.

Besides priming the pump for future MIC customers, Intel is also lining up system vendors. At ISC, Knights Ferry systems will be showcased by SGI, IBM, HP, Dell, Colfax, and Supermicro. That’s a quite a bit of vendor enthusiasm, considering this is just prototype hardware, and reflects Intel’s pull in the industry.

Besides confirming that the first MIC product would indeed be on 22nm technology, the press briefing last week gave no new details on Knights Corner. But it’s reasonable to speculate to the 2012 product will support PCIe 3.0 since the new PCI interface should shipping with most new servers by next year (not to mention that the Sandy Bridge Xeons are rumored to incorporate that technology on-chip). Also, no mention was made about ECC memory support, but given ECC is a requirement for serious HPC, and the NVIDIA Fermi Tesla GPUs already support it, it’s almost inconceivable that MIC would be launched without it.

As far as when the actual product would be released in 2012, that was left open. However since Intel has made its two MIC major announcements at ISC, it wouldn’t be surprising if they used next year’s conference to launch Knights Corner.

Beyond that first product, Intel has provided no roadmap. A logical next step would be an integrated Xeon-MIC processor, a la AMD’s Fusion APU and NVIDIA’s ‘Project Denver’ chips, but Intel has been tight-lipped about any such architecture, at least publicly. But given the performance and software friendliness of a unified memory space, heterogeneous processor, Intel has got to be thinking about it.

An integrated Xeon-MIC chip could certainly provide a viable platform for exascale supercomputers, and there is no doubt that Intel wants to be a play in this space. During the press briefing, Neal-Graves repeatedly talked about MIC and exascale in the same breath. The chipmaker’s interest in exascale computing is nothing new, but linking it to a particular architecture certainly is.

“We will be investing in the technology and software capabilities to really bring exascale to reality,” said Neal-Graves. “We’re extremely committed to that and we’re going to make that happen.”

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