Intel Touts Manycore Coprocessor at Supercomputing Conference

By Michael Feldman

June 20, 2011

Today at the International Supercomputing Conference (ISC) in Hamburg, Germany, Intel outlined the progress it has made over the last year toward bringing its Many Integrated Core (MIC) coprocessor platform to market. MIC is Intel’s answer to general-purpose GPU computing, and like the latter technology, Intel believes it can parlay the its manycore design into future exascale systems.

Recycling the design from the aborted Larrabee graphics processor effort, MIC was recast as an high performance coprocessor for HPC. This product redirection was unveiled in May 2010 during last year’s ISC event. Since then Intel has been passing out MIC software development platforms (SDPs) to selected users in the HPC community.

An SDP is basically a Knights Ferry coprocessor card (the MIC prototype) with up to two GB of GDDR5 memory. The card is hooked up, via PCIe, to a host system with one or more Xeon CPUs.

In a press briefing on June 14, Anthony Neal-Graves, Intel VP and General Manager of Workstations and MIC Computing, reported that at this time last year, they had 10 users running code on Knights Ferry platform. By the end of this month, they’ll have about 50 such users, with the goal of hitting 100 by the end of 2011. According to Neal-Graves, everything was on track for the launch of the first commercial MIC product, known as Knights Corner.

Knights Corner, he said, would arrive in 2012 using Intel’s newly hatched tri-gate 22nm process node. With perhaps an indirect inference to NVIDIA’s and AMD’s GPU computing prowess, Neal-Graves noted that they’ll be able to use their 22nm technology to deliver cheaper, faster and more power-efficient silicon than their competition, adding, “That’s really going to bring the performance to the table that we really need for these types of solutions.”

Performance-wise, MIC has to be able to hit a rather fast-moving target thanks to NVIDIA and AMD upping the FLOPS count for GPUs over the last few years. There are not a lot of performance metrics available for the Knights Ferry prototype, but Intel does claim a one teraflop value for the SGEMM benchmark (measuring a simple single precision matrix multiply). An equivalent value for the latest NVIDIA Tesla part, the M2090, would probably be in the neighborhood of 800 to 900 gigaflops, and perhaps twice that for the the FireStream 9370.

Since Knights Ferry is a 32-core processor (on 45nm technology), the 50-plus-core Knights Corner commercial product coming out next year should easily double the performance numbers of the prototype. But 2012 will also see the introduction of NVIDIA’s “Kepler” GPU, an architecture that aims to triple the performance of the current generation Fermi parts. Also, since Intel has not released any performance numbers for double precision floating point code, it remains to be seen how MIC will perform in this important realm.

Regardless of how the FLOPS shake out, Intel’s is claiming their biggest advantage will be on the software side, since they are promising MIC support under the chipmaker’s existing x86 developer toolset. Specifically, the company is inserting MIC support in their C and Fortran compilers, debuggers, libraries, and even their more exotic offerings, like Cilk Plus, and Threading Building Blocks. And since MIC is fundamentally an x86 manycore processor (with 512-bit wide vector units), even the low-level code structures are similar. The idea is to provide a common programming environment for the x86 developer, or as Neal-Graves put it: “If you can program a Xeon, you can program a MIC processor.”

For simple pieces of code, like the aforementioned SGEMM function, the 18 lines of code that performed the matrix math was identical for the Xeon and Knights Ferry versions. In this case, the Intel compiler and Math Kernel Library (MKL) performed the heavy lifting to execute the Xeon- or MIC-specific code as appropriate.

That shouldn’t lull developers into thinking they can recompile an entire application for MIC. In most cases, they are going to have to modify the source to parallelize their code or the coprocess. If the existing code is already instrumented with OpenMP directives, developers should have a leg up. Intel has implemented OpenMP support for MIC, along with some directive extensions to deal with the coprocessor setup. In general though, the developer can apply the same OpenMP task parallelization model they used for Xeon to MIC.

In fact, the Innovative Systems Lab (ISL) at the National Center for Supercomputing Applications (NCSA) has ported a couple of science codes to Knights Ferry — one a benchmark code, the other a full astronomy application. The benchmark code was used get familar with the software development process, while the astronomy code was a proof-of-concept test for a full application port.

According to Mike Showerman, the Technical Program Manager at ISL, the application code was already written with accelerators in mind, so the initial port was relatively straightforward. Much of effort (which is still ongoing) involves tuning the code to optimize MIC vectorization. The current Intel compiler performs some MIC auto-vectorization for MIC, but support for the coprocessor not fully baked yet. In fact, most of the components of the MIC software stack are in the “alpha” stage at this point.

Other demonstration of MIC-ported applications, and which will be on display at ISC this week, include an SMMP protein folding application by Forschungszentrum Juelich; a molecular dynamics code at KISTI (Korea Institute of Science & Technology Information); a TifaMMy matrix multiplication code at LRZ (Leibniz Supercomputing Center); and a core scaling benchmark from CERN.

Besides priming the pump for future MIC customers, Intel is also lining up system vendors. At ISC, Knights Ferry systems will be showcased by SGI, IBM, HP, Dell, Colfax, and Supermicro. That’s a quite a bit of vendor enthusiasm, considering this is just prototype hardware, and reflects Intel’s pull in the industry.

Besides confirming that the first MIC product would indeed be on 22nm technology, the press briefing last week gave no new details on Knights Corner. But it’s reasonable to speculate to the 2012 product will support PCIe 3.0 since the new PCI interface should shipping with most new servers by next year (not to mention that the Sandy Bridge Xeons are rumored to incorporate that technology on-chip). Also, no mention was made about ECC memory support, but given ECC is a requirement for serious HPC, and the NVIDIA Fermi Tesla GPUs already support it, it’s almost inconceivable that MIC would be launched without it.

As far as when the actual product would be released in 2012, that was left open. However since Intel has made its two MIC major announcements at ISC, it wouldn’t be surprising if they used next year’s conference to launch Knights Corner.

Beyond that first product, Intel has provided no roadmap. A logical next step would be an integrated Xeon-MIC processor, a la AMD’s Fusion APU and NVIDIA’s ‘Project Denver’ chips, but Intel has been tight-lipped about any such architecture, at least publicly. But given the performance and software friendliness of a unified memory space, heterogeneous processor, Intel has got to be thinking about it.

An integrated Xeon-MIC chip could certainly provide a viable platform for exascale supercomputers, and there is no doubt that Intel wants to be a play in this space. During the press briefing, Neal-Graves repeatedly talked about MIC and exascale in the same breath. The chipmaker’s interest in exascale computing is nothing new, but linking it to a particular architecture certainly is.

“We will be investing in the technology and software capabilities to really bring exascale to reality,” said Neal-Graves. “We’re extremely committed to that and we’re going to make that happen.”

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Talk to Me: Nvidia Claims NLP Inference, Training Records

August 15, 2019

Nvidia says it’s achieved significant advances in conversation natural language processing (NLP) training and inference, enabling more complex, immediate-response interchanges between customers and chatbots. And the co Read more…

By Doug Black

Trump Administration and NIST Issue AI Standards Development Plan

August 14, 2019

Efforts to develop AI are gathering steam fast. On Monday, the White House issued a federal plan to help develop technical standards for AI following up on a mandate contained in the Administration’s AI Executive Order Read more…

By John Russell

Scientists to Tap Exascale Computing to Unlock the Mystery of our Accelerating Universe

August 14, 2019

The universe and everything in it roared to life with the Big Bang approximately 13.8 billion years ago. It has continued expanding ever since. While we have a good understanding of the early universe, its fate billions Read more…

By Rob Johnson

AWS Solution Channel

Efficiency and Cost-Optimization for HPC Workloads – AWS Batch and Amazon EC2 Spot Instances

High Performance Computing on AWS leverages the power of cloud computing and the extreme scale it offers to achieve optimal HPC price/performance. With AWS you can right size your services to meet exactly the capacity requirements you need without having to overprovision or compromise capacity. Read more…

HPE Extreme Performance Solutions

Bring the combined power of HPC and AI to your business transformation

FPGA (Field Programmable Gate Array) acceleration cards are not new, as they’ve been commercially available since 1984. Typically, the emphasis around FPGAs has centered on the fact that they’re programmable accelerators, and that they can truly offer workload specific hardware acceleration solutions without requiring custom silicon. Read more…

IBM Accelerated Insights

Cloudy with a Chance of Mainframes

[Connect with HPC users and learn new skills in the IBM Spectrum LSF User Community.]

Rapid rates of change sometimes result in unexpected bedfellows. Read more…

Argonne Supercomputer Accelerates Cancer Prediction Research

August 13, 2019

In the fight against cancer, early prediction, which drastically improves prognoses, is critical. Now, new research by a team from Northwestern University – and accelerated by supercomputing resources at Argonne Nation Read more…

By Oliver Peckham

Scientists to Tap Exascale Computing to Unlock the Mystery of our Accelerating Universe

August 14, 2019

The universe and everything in it roared to life with the Big Bang approximately 13.8 billion years ago. It has continued expanding ever since. While we have a Read more…

By Rob Johnson

AI is the Next Exascale – Rick Stevens on What that Means and Why It’s Important

August 13, 2019

Twelve years ago the Department of Energy (DOE) was just beginning to explore what an exascale computing program might look like and what it might accomplish. Today, DOE is repeating that process for AI, once again starting with science community town halls to gather input and stimulate conversation. The town hall program... Read more…

By Tiffany Trader and John Russell

Cray Wins NNSA-Livermore ‘El Capitan’ Exascale Contract

August 13, 2019

Cray has won the bid to build the first exascale supercomputer for the National Nuclear Security Administration (NNSA) and Lawrence Livermore National Laborator Read more…

By Tiffany Trader

AMD Launches Epyc Rome, First 7nm CPU

August 8, 2019

From a gala event at the Palace of Fine Arts in San Francisco yesterday (Aug. 7), AMD launched its second-generation Epyc Rome x86 chips, based on its 7nm proce Read more…

By Tiffany Trader

Lenovo Drives Single-Socket Servers with AMD Epyc Rome CPUs

August 7, 2019

No summer doldrums here. As part of the AMD Epyc Rome launch event in San Francisco today, Lenovo announced two new single-socket servers, the ThinkSystem SR635 Read more…

By Doug Black

Building Diversity and Broader Engagement in the HPC Community

August 7, 2019

Increasing diversity and inclusion in HPC is a community-building effort. Representation of both issues and individuals matters - the more people see HPC in a w Read more…

By AJ Lauer

Xilinx vs. Intel: FPGA Market Leaders Launch Server Accelerator Cards

August 6, 2019

The two FPGA market leaders, Intel and Xilinx, both announced new accelerator cards this week designed to handle specialized, compute-intensive workloads and un Read more…

By Doug Black

Upcoming NSF Cyberinfrastructure Projects to Support ‘Long-Tail’ Users, AI and Big Data

August 5, 2019

The National Science Foundation is well positioned to support national priorities, as new NSF-funded HPC systems to come online in the upcoming year promise to Read more…

By Ken Chiacchia, Pittsburgh Supercomputing Center/XSEDE

High Performance (Potato) Chips

May 5, 2006

In this article, we focus on how Procter & Gamble is using high performance computing to create some common, everyday supermarket products. Tom Lange, a 27-year veteran of the company, tells us how P&G models products, processes and production systems for the betterment of consumer package goods. Read more…

By Michael Feldman

Supercomputer-Powered AI Tackles a Key Fusion Energy Challenge

August 7, 2019

Fusion energy is the Holy Grail of the energy world: low-radioactivity, low-waste, zero-carbon, high-output nuclear power that can run on hydrogen or lithium. T Read more…

By Oliver Peckham

Cray, AMD to Extend DOE’s Exascale Frontier

May 7, 2019

Cray and AMD are coming back to Oak Ridge National Laboratory to partner on the world’s largest and most expensive supercomputer. The Department of Energy’s Read more…

By Tiffany Trader

Graphene Surprises Again, This Time for Quantum Computing

May 8, 2019

Graphene is fascinating stuff with promise for use in a seeming endless number of applications. This month researchers from the University of Vienna and Institu Read more…

By John Russell

AMD Verifies Its Largest 7nm Chip Design in Ten Hours

June 5, 2019

AMD announced last week that its engineers had successfully executed the first physical verification of its largest 7nm chip design – in just ten hours. The AMD Radeon Instinct Vega20 – which boasts 13.2 billion transistors – was tested using a TSMC-certified Calibre nmDRC software platform from Mentor. Read more…

By Oliver Peckham

TSMC and Samsung Moving to 5nm; Whither Moore’s Law?

June 12, 2019

With reports that Taiwan Semiconductor Manufacturing Co. (TMSC) and Samsung are moving quickly to 5nm manufacturing, it’s a good time to again ponder whither goes the venerable Moore’s law. Shrinking feature size has of course been the primary hallmark of achieving Moore’s law... Read more…

By John Russell

Deep Learning Competitors Stalk Nvidia

May 14, 2019

There is no shortage of processing architectures emerging to accelerate deep learning workloads, with two more options emerging this week to challenge GPU leader Nvidia. First, Intel researchers claimed a new deep learning record for image classification on the ResNet-50 convolutional neural network. Separately, Israeli AI chip startup Hailo.ai... Read more…

By George Leopold

Cray Wins NNSA-Livermore ‘El Capitan’ Exascale Contract

August 13, 2019

Cray has won the bid to build the first exascale supercomputer for the National Nuclear Security Administration (NNSA) and Lawrence Livermore National Laborator Read more…

By Tiffany Trader

Leading Solution Providers

ISC 2019 Virtual Booth Video Tour

CRAY
CRAY
DDN
DDN
DELL EMC
DELL EMC
GOOGLE
GOOGLE
ONE STOP SYSTEMS
ONE STOP SYSTEMS
PANASAS
PANASAS
VERNE GLOBAL
VERNE GLOBAL

Nvidia Embraces Arm, Declares Intent to Accelerate All CPU Architectures

June 17, 2019

As the Top500 list was being announced at ISC in Frankfurt today with an upgraded petascale Arm supercomputer in the top third of the list, Nvidia announced its Read more…

By Tiffany Trader

Top500 Purely Petaflops; US Maintains Performance Lead

June 17, 2019

With the kick-off of the International Supercomputing Conference (ISC) in Frankfurt this morning, the 53rd Top500 list made its debut, and this one's for petafl Read more…

By Tiffany Trader

A Behind-the-Scenes Look at the Hardware That Powered the Black Hole Image

June 24, 2019

Two months ago, the first-ever image of a black hole took the internet by storm. A team of scientists took years to produce and verify the striking image – an Read more…

By Oliver Peckham

Cray – and the Cray Brand – to Be Positioned at Tip of HPE’s HPC Spear

May 22, 2019

More so than with most acquisitions of this kind, HPE’s purchase of Cray for $1.3 billion, announced last week, seems to have elements of that overused, often Read more…

By Doug Black and Tiffany Trader

AMD Launches Epyc Rome, First 7nm CPU

August 8, 2019

From a gala event at the Palace of Fine Arts in San Francisco yesterday (Aug. 7), AMD launched its second-generation Epyc Rome x86 chips, based on its 7nm proce Read more…

By Tiffany Trader

Chinese Company Sugon Placed on US ‘Entity List’ After Strong Showing at International Supercomputing Conference

June 26, 2019

After more than a decade of advancing its supercomputing prowess, operating the world’s most powerful supercomputer from June 2013 to June 2018, China is keep Read more…

By Tiffany Trader

In Wake of Nvidia-Mellanox: Xilinx to Acquire Solarflare

April 25, 2019

With echoes of Nvidia’s recent acquisition of Mellanox, FPGA maker Xilinx has announced a definitive agreement to acquire Solarflare Communications, provider Read more…

By Doug Black

Qualcomm Invests in RISC-V Startup SiFive

June 7, 2019

Investors are zeroing in on the open standard RISC-V instruction set architecture and the processor intellectual property being developed by a batch of high-flying chip startups. Last fall, Esperanto Technologies announced a $58 million funding round. Read more…

By George Leopold

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This