The 3D Torus Architecture and the Eurotech Approach

By Nicole Hemsoth

June 20, 2011

The 3D Torus architecture and the Eurotech approach

The ability of supercomputers to progressively run job faster meets the computational needs of both scientific research and an increasingly higher number of industry sectors.

Processor power is centerpiece to determine the performance of an HPC system, but it is not the only factor. One of the key aspects of parallel computers is the communication network that interconnects the computing nodes. The network is the one guaranteeing fast interactions between CPUs and allowing the processors to cooperate: this is essential to solve complex computational problems in a fast and efficient way.

Together with speed, HPC systems are increasingly asked to be more available. Downtime can affect a high performance machines quite badly. It appears clear that a reliable average machine with a great uptime is better than a high performance one with a low MTBF (mean time before faults): ultimately, the former would process more jobs in a week than the latter.

One additional challenge with large systems is scalability, so the ability to add nodes to a cluster without affecting performance and reliability or affecting them as little as possible. Petascale and then exascale installations require and will require hundreds of thousands of cores to efficiently work together.

It is also paramount for future machines to consume less energy, being cost and availability of electrical power an issue that is becoming the most demanding challenge to overcome along the road to exascale computing.

3D torus connectivity

In a computer cluster, the way the nodes are connected together could provide some determinant help to solve the above mentioned issues.

Despite being available for quite a while, the torus architecture has now the potential to surge from niche application to mainstream. This is because, like never before, we face nowadays some severe challenges posed by a raising number of nodes. The problem, before being one of performance, is one of topology and scalability. The more a system grows, the more fat tree switched topologies show limits of cost, maintainability, consumption, reliability and, above all, scalability.

Connecting nodes using a 3D Torus configuration means than each node in a cluster is connected to the adjacent ones via short cabling. The signal is routed directly from one node to the other with no need of switches. 3D means that the communication takes places in 6 different “directions”: X+, X-, Y+, Y-, Z+, Z-. In practical terms, each node can be connected to 6 other nodes: in this way, the graph of the connections resembles a tri-dimensional matrix.

Such configuration allows the addition of nodes to a system without degrading performance. Each new node is joint as an addition of a grid, linked to it with no extensive cabling or switching. While scaling linearly, with little or no performance loss, is strictly true for those problems that heavily rely on next neighbor communication, it is also true that, avoiding switches, hundreds of nodes can be added without causing problems of clogged links or busy fat tree switch leafs. This comes without considering that the addition of a node in a large system happens with much less working and potential troubles on a 3D torus network than on switched fat tree one. 

The pairwise connectivity between nearest neighbor nodes of a 3D Torus configuration helps to reduce latency and the typical bottlenecks of switched networks. Being the connections between nodes short and direct, the latency of the links is very low: this affects positively the machine performance, especially for solving local patters problems, which can be effectively mapped onto the matrix mentioned above. The switchless nature of the 3D Torus facilitates fast communication between nodes.

Switches are also potential points of failure. Decreasing their number should improve the operational functioning of a system. In other words, the 3D Torus makes a system more agile, so more prompt to react to failures: if a connection or a node fails, the affected communication can be routed in many different directions. The inherent nature of the 3D Torus is the connectivity of each node to its nearest neighbors to form a tridimensional lattice that guarantees multiple ways for a node to reach another one.

Eliminating costly and power-hungry external spine and leaf switches, as well as their accompanying rack chassis and cooling systems, torus architectures also contribute to reduce installation costs and energy consumption.

Applications

When it comes to applications that can fully benefit from the 3D Torus configuration we could touch one of the caveats of this intelligent connection schema.

The maximization of the performance of the 3D Torus takes place with a subset of problems which is rather large but specific. These are local pattern problems, which typically deal with modeling systems whose functioning/reaction depends on adjacent systems. Typical examples are computer simulations of Lattice QCD and fluid-dynamics. More in general, many Monte Carlo simulations and embarrassingly parallel problems can exploit the full performance advantage of the 3D Torus architecture, making the range of possible applications quite vast, especially within the field of scientific research.

Problems that require all to all dialogue between nodes are less prone to exploit the full performance of the 3D torus interconnection. However, independently from the type of application and problem, the 3D torus still bears the massive advantage of scalability and serviceability, contributing also to increase the availability of the systems and reduce power consumption. In case of large systems, it may be so advantageous to resort to the 3D Torus architecture that the perfect match with the problem that better maximize the computational performance may well become secondary.

The Eurotech approach

It is rather interesting to analyze what Eurotech, a leading European computer manufacturer, has done with the 3D Torus network of their supercomputer line Aurora.

Eurotech wanted to leverage the 3D Torus benefits for their high end products, but at the same time leave to the users the flexibility and the freedom to run all the applications they need.

Taking in account these diverging characteristics, Eurotech and its scientific partners took and approach called Unified Network Architecture in designing the Aurora datacenter clusters. This fundamentally means that the Aurora systems have 3 different networks working in concomitance on the same machine: 2 fast independent networks (Infiniband, 3D Torus) and a multi-level synchronization network.

The coexistence of Infiniband and 3D Torus facilitates flexibility of use: depending on the application, one or the other network can be utilized. The synchronization networks act at different levels, synchronizing the CPUs and de facto reducing or eliminating the OS jitter and hence making the system more scalable.

Torus topologies have traditionally been implemented with proprietary, costly application-specific integrated circuit (ASIC) technology. Eurotech chose to drive the torus with FPGAs, injecting more flexibility in the hardware, and to rely both on a GPL and on a commercial distribution for the 3D torus software. The 3D torus network is managed by a network processor implemented in the FPGAs, which interfaces the system hub through two x8 PCI Express Gen 3 connections, for a total internal bandwidth of 120Gbs.

Each link in the torus architecture is physically implemented by two lines (main and redundant) that can be selected (in software) to configure the machine partitioning (full 3D Torus or one of the many 3D sub-tori available). In this way, redundant channels allow system repartitioning on-the-fly. The possibility of partitioning the system into sub-domains permits to create system partitions that communicate on independent tori, effectively creating different execution domains. In addition, each subdomain can benefit from a dedicated synchronization network.

As an example of partitioning, if a backplane with 16 boards is considered, the available topologies for the partitioning of the machine in smaller sub-machines with periodic boundaries (sub-tori) are:

Half Unit: 2 x [1:2*NC] x [1:2*NR]

Unit: 4 x [1:2*NC] x [1:2*NR]

Double Unit:8 x [1:2*NC] x [1:2*NR], Rack: 8 x 2*NC x 2, Machine: 8 x 2*NC x 2*NR

Chassis: 16 x [1:NC] x [1, 2,  2*NR], Rack: 16 x NC x 2, Machine: 16 x NC x 2*NR

Where

–         NC : Number of chassis in a rack (8).
–         NR : Number of racks in a machine (from 1 to many hundreds)

Partitioning, FPGAs, redundant channels, synchronization networks are some of the unique characteristics that Eurotech wanted in the torus architecture to create Intel based clusters with the flavor of a special machines.

Eurotech

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

SC Bids Farewell to Denver, Heads to Dallas for 30th

November 17, 2017

After a jam-packed four-day expo and intensive six-day technical program, SC17 has wrapped up another successful event that brought together nearly 13,000 visitors to the Colorado Convention Center in Denver for the larg Read more…

By Tiffany Trader

SC17 Keynote – HPC Powers SKA Efforts to Peer Deep into the Cosmos

November 17, 2017

This week’s SC17 keynote – Life, the Universe and Computing: The Story of the SKA Telescope – was a powerful pitch for the potential of Big Science projects that also showcased the foundational role of high performance computing in modern science. It was also visually stunning. Read more…

By John Russell

How Cities Use HPC at the Edge to Get Smarter

November 17, 2017

Cities are sensoring up, collecting vast troves of data that they’re running through predictive models and using the insights to solve problems that, in some cases, city managers didn’t even know existed. Speaking Read more…

By Doug Black

HPE Extreme Performance Solutions

Harness Scalable Petabyte Storage with HPE Apollo 4510 and HPE StoreEver

As a growing number of connected devices challenges IT departments to rapidly collect, manage, and store troves of data, organizations must adopt a new generation of IT to help them operate quickly and intelligently. Read more…

SC17 Student Cluster Competition Configurations: Fewer Nodes, Way More Accelerators

November 16, 2017

The final configurations for each of the SC17 “Donnybrook in Denver” Student Cluster Competition have been released. Fortunately, each team received their equipment shipments on time and undamaged, so the teams are r Read more…

By Dan Olds

SC Bids Farewell to Denver, Heads to Dallas for 30th

November 17, 2017

After a jam-packed four-day expo and intensive six-day technical program, SC17 has wrapped up another successful event that brought together nearly 13,000 visit Read more…

By Tiffany Trader

SC17 Keynote – HPC Powers SKA Efforts to Peer Deep into the Cosmos

November 17, 2017

This week’s SC17 keynote – Life, the Universe and Computing: The Story of the SKA Telescope – was a powerful pitch for the potential of Big Science projects that also showcased the foundational role of high performance computing in modern science. It was also visually stunning. Read more…

By John Russell

How Cities Use HPC at the Edge to Get Smarter

November 17, 2017

Cities are sensoring up, collecting vast troves of data that they’re running through predictive models and using the insights to solve problems that, in some Read more…

By Doug Black

Student Cluster LINPACK Record Shattered! More LINs Packed Than Ever before!

November 16, 2017

Nanyang Technological University, the pride of Singapore, utterly destroyed the Student Cluster Competition LINPACK record by posting a score of 51.77 TFlop/s a Read more…

By Dan Olds

Hyperion Market Update: ‘Decent’ Growth Led by HPE; AI Transparency a Risk Issue

November 15, 2017

The HPC market update from Hyperion Research (formerly IDC) at the annual SC conference is a business and social “must,” and this year’s presentation at S Read more…

By Doug Black

Nvidia Focuses Its Cloud Containers on HPC Applications

November 14, 2017

Having migrated its top-of-the-line datacenter GPU to the largest cloud vendors, Nvidia is touting its Volta architecture for a range of scientific computing ta Read more…

By George Leopold

HPE Launches ARM-based Apollo System for HPC, AI

November 14, 2017

HPE doubled down on its memory-driven computing vision while expanding its processor portfolio with the announcement yesterday of the company’s first ARM-base Read more…

By Doug Black

OpenACC Shines in Global Climate/Weather Codes

November 14, 2017

OpenACC, the directive-based parallel programming model used mostly for porting codes to GPUs for use on heterogeneous systems, came to SC17 touting impressive Read more…

By John Russell

US Coalesces Plans for First Exascale Supercomputer: Aurora in 2021

September 27, 2017

At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, in Arlington, Va., yesterday (Sept. 26), it was revealed that the "Aurora" supercompute Read more…

By Tiffany Trader

NERSC Scales Scientific Deep Learning to 15 Petaflops

August 28, 2017

A collaborative effort between Intel, NERSC and Stanford has delivered the first 15-petaflops deep learning software running on HPC platforms and is, according Read more…

By Rob Farber

Oracle Layoffs Reportedly Hit SPARC and Solaris Hard

September 7, 2017

Oracle’s latest layoffs have many wondering if this is the end of the line for the SPARC processor and Solaris OS development. As reported by multiple sources Read more…

By John Russell

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Google Releases Deeplearn.js to Further Democratize Machine Learning

August 17, 2017

Spreading the use of machine learning tools is one of the goals of Google’s PAIR (People + AI Research) initiative, which was introduced in early July. Last w Read more…

By John Russell

GlobalFoundries Puts Wind in AMD’s Sails with 12nm FinFET

September 24, 2017

From its annual tech conference last week (Sept. 20), where GlobalFoundries welcomed more than 600 semiconductor professionals (reaching the Santa Clara venue Read more…

By Tiffany Trader

Amazon Debuts New AMD-based GPU Instances for Graphics Acceleration

September 12, 2017

Last week Amazon Web Services (AWS) streaming service, AppStream 2.0, introduced a new GPU instance called Graphics Design intended to accelerate graphics. The Read more…

By John Russell

EU Funds 20 Million Euro ARM+FPGA Exascale Project

September 7, 2017

At the Barcelona Supercomputer Centre on Wednesday (Sept. 6), 16 partners gathered to launch the EuroEXA project, which invests €20 million over three-and-a-half years into exascale-focused research and development. Led by the Horizon 2020 program, EuroEXA picks up the banner of a triad of partner projects — ExaNeSt, EcoScale and ExaNoDe — building on their work... Read more…

By Tiffany Trader

Leading Solution Providers

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Cray Moves to Acquire the Seagate ClusterStor Line

July 28, 2017

This week Cray announced that it is picking up Seagate's ClusterStor HPC storage array business for an undisclosed sum. "In short we're effectively transitioning the bulk of the ClusterStor product line to Cray," said CEO Peter Ungaro. Read more…

By Tiffany Trader

Intel Launches Software Tools to Ease FPGA Programming

September 5, 2017

Field Programmable Gate Arrays (FPGAs) have a reputation for being difficult to program, requiring expertise in specialty languages, like Verilog or VHDL. Easin Read more…

By Tiffany Trader

HPC Chips – A Veritable Smorgasbord?

October 10, 2017

For the first time since AMD's ill-fated launch of Bulldozer the answer to the question, 'Which CPU will be in my next HPC system?' doesn't have to be 'Whichever variety of Intel Xeon E5 they are selling when we procure'. Read more…

By Dairsie Latimer

IBM Advances Web-based Quantum Programming

September 5, 2017

IBM Research is pairing its Jupyter-based Data Science Experience notebook environment with its cloud-based quantum computer, IBM Q, in hopes of encouraging a new class of entrepreneurial user to solve intractable problems that even exceed the capabilities of the best AI systems. Read more…

By Alex Woodie

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This