GPU Challenges: A Q&A with NVIDIA’s David Kirk

By Nicole Hemsoth

June 22, 2011

At ISC this year, there are plenty of sessions devoted to manycore processors, especially in the role of HPC accelerators. Not surprisingly, a lot of these are centered on the current sweetheart of manycore: GPUs. One of the most well-attended sessions here at ISC’11 was “The GPU Debate” between NVIDIA Fellow David Kirk and LSU professor Thomas Sterling, where the two bantered about the architecture, its evolution as a general-purpose HPC processor, and its roadmap to exascale.

HPCwire caught up with Kirk and asked him about some of the specific challenges of GPU computing today and how he views the role of integrated CPU-GPU architectures as they come into play.

HPCwire: Is there any thought at NVIDIA to proposing CUDA as an open standard for the GPU/manycore computing community?

David Kirk: There are no plans to turn CUDA into an open standard at this point. Right now, the only processors we see being deployed widely in servers are x86 CPUs and NVIDIA GPUs and these are all supported by CUDA toolkits today. NVIDIA offers developers choice – choice to use CUDA C, CUDA C++, CUDA Fortran, OpenCL, or DirectCompute to program CPU-GPU systems. We chair the OpenCL working group, we have collaborated closely with Microsoft on DirectCompute and continue to do so as they evolve these platforms. But CUDA is our platform for innovation. We recently released CUDA 4.0, which is a huge leap forward in programmer productivity with features like unified virtual addressing and the new Thrust C++ template library. We continue to move CUDA forward at a rapid pace.

HPCwire: There has been plenty of talk about the problems involved in hanging a GPU processor off of a PCI bus for use as an external accelerator – I/O overhead and the software messiness of having to do explicit data transfers. What do you think are the biggest limitations of the current GPU processors from a hardware point of view, in regard to high performance computing?

Kirk: The PCIe bottleneck concern is hotly debated and we hear about it a lot. We are aware of very few applications that are bottlenecked by transfer speeds. Incidentally, the PCIe bus is often not the slowest bus in the system. Network and disk interfaces are slower, and in many systems the CPU memory path is slower!

That being said, there are two things that have changed since this concern first surfaced. First, we now have 6 GB of on-board memory and second, our new NVIDIA GPUDirect technology is eliminating the CPU and GPU memory bottlenecks from the path.

These enhancements reduce the PCIe bottleneck. Data can directly stream from storage to the GPU memory via GPUDirect and the larger GPU memory enables more data to reside on the GPU without communicating to the CPU. Our future GPU architectures will continue to reduce dependence on and communication with the CPU, thus eventually very significantly limiting the PCIe bottleneck. By the way, Vincent Natoli summarized it nicely in his recent HPCwire article.

I personally believe though, that the biggest limitation of GPU computing is the misconception that it’s too hard. Put this into whichever bucket you wish — ease of use of the software, the programmability of the hardware, the performance, per watt, per dollar. However you slice it, there have been many reasons cited as to why not to adopt GPU computing.

We’ll be the first to say that parallel computing is challenging. I personally co-teach the parallel computing course, along with Dr. Wen-mei Hwu, at the University of Illinois at Urbana-Champaign, so I know first-hand what it is like to switch the mindset from a purely serial based model to thinking about problems in a multi-threaded parallel environment.

But the rewards are significant. Change two percent of your code and in many cases you can see up to a 10X increase in performance. That’s a pretty big bang for your software development buck. And, we live in a parallel computing world now, so serial programming is no longer a viable option.

HPCwire: Same question for software side. What are the biggest limitations of the current GPU computing software frameworks?

Kirk: One of the most common concerns I hear from the community is the portability aspect of CUDA and the fact that it only runs on NVIDIA GPUs. As I said before, we remain agnostic on language. Fortran, Python, C, C++, Java, OpenCL, DirectCompute – we support all these languages, either internally or through 3rd parties. If you choose to use NVIDIA GPUs, then we will ensure that have you the widest choice of languages.

With regards to the portability of the hardware platform, PGI has just announced the first version of CUDA x86, that enables CUDA code to be compiled down to x86 CPUs. This facilitates easier-than-ever deployment of CUDA-enabled applications across hybrid GPU/CPU systems and is an important milestone in the increased portability of CUDA. There are also several tools created by universities and 3rd-parties to convert CUDA source code to OpenCL source code, which can be compiled for any platform that supports OpenCL. So, portability is no longer a realistic objection but more of an excuse.

Training the millions of software developers who are already in the industry to program in parallel – that is the biggest challenge facing HPC and parallel computing in general. This is where the elegance of the CUDA parallel programming model really helps and the reason why it has caught on so quickly and so widely. CUDA C/C++ is an incredibly powerful language of authorship, and we have found that it is quite easy to learn.

HPCwire: Do you think the appearance of heterogeneous CPU-GPU processors portends the demise of discrete GPUs – for GPU computing or otherwise? Do you think it will spell the end of “pure” CPUs?

Kirk: A lot of folks believe that integrating CPUs and GPUs together is a panacea. As you well know, this is easy for NVIDIA to do. We have the highest volume integrated CPU-GPU SoC shipping today: our Tegra mobile SoC. But if you scale this to HPC, the challenge is that you have to compromise either on the performance of the CPU or that of the GPU. The silicon area is fixed, so you have to put a medium performance CPU with a medium performance GPU. Not exactly HPC! We find that none of our customers ever ask us for less performance.

For the foreseeable future, there will be a market for a discrete CPU and a discrete GPU – the performance users, whether in HPC or in gaming or CAD workstations, need the best of both. But a swing we already see happening is that applications are leaning more on the GPU for performance than on the CPU — both gaming and HPC. This is because performance scaling on CPUs seems to have reached an end. Laptops are not going beyond dual-core x86 CPUs. Even on HPC, application performance is not scaling beyond 4 cores. They end up choking on memory bandwidth.

Clearly, the personal computer experience is going to be dominated by SoCs with integrated ARM cores and GPUs. This is happening today and will be solidified by support for ARM in Windows Next. But as I said above, we expect that there will be a CPU + GPU market for a very long time to come.

HPCwire: How will users be able to port codes developed today with CUDA, OpenCL and accelerator-directives to the future shared-memory architectures of CPU-GPU integrated processors envisioned by “Project Denver” AMD Fusion, etc.?

Kirk: The beauty about the CUDA programming model is that it was designed for CPU-GPU based heterogeneous architectures. Whether the CPU and GPU are integrated does not change the programming model. Integration is simply a cost consideration. After all, we have been working on Tegra — ARM + GPU SoCs — for just as long as we have been working on CUDA. Other driver-level APIs like OpenCL treat the GPU as a device that is separate from the CPU (host) and this means that OpenCL as defined today has to be extended to support an integrated CPU-GPU device. This means that applications written with the CUDA toolkits will just work on our integrated CPU-GPU devices.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Researchers Scale COSMO Climate Code to 4888 GPUs on Piz Daint

October 17, 2017

Effective global climate simulation, sorely needed to anticipate and cope with global warming, has long been computationally challenging. Two of the major obstacles are the needed resolution and prolonged time to compute Read more…

By John Russell

Student Cluster Competition Coverage New Home

October 16, 2017

Hello computer sports fans! This is the first of many (many!) articles covering the world-wide phenomenon of Student Cluster Competitions. Finally, the Student Cluster Competition coverage has come to its natural home: H Read more…

By Dan Olds

UCSD Web-based Tool Tracking CA Wildfires Generates 1.5M Views

October 16, 2017

Tracking the wildfires raging in northern CA is an unpleasant but necessary part of guiding efforts to fight the fires and safely evacuate affected residents. One such tool – Firemap – is a web-based tool developed b Read more…

By John Russell

HPE Extreme Performance Solutions

Transforming Genomic Analytics with HPC-Accelerated Insights

Advancements in the field of genomics are revolutionizing our understanding of human biology, rapidly accelerating the discovery and treatment of genetic diseases, and dramatically improving human health. Read more…

Exascale Imperative: New Movie from HPE Makes a Compelling Case

October 13, 2017

Why is pursuing exascale computing so important? In a new video – Hewlett Packard Enterprise: Eighteen Zeros – four HPE executives, a prominent national lab HPC researcher, and HPCwire managing editor Tiffany Trader Read more…

By John Russell

Student Cluster Competition Coverage New Home

October 16, 2017

Hello computer sports fans! This is the first of many (many!) articles covering the world-wide phenomenon of Student Cluster Competitions. Finally, the Student Read more…

By Dan Olds

Intel Delivers 17-Qubit Quantum Chip to European Research Partner

October 10, 2017

On Tuesday, Intel delivered a 17-qubit superconducting test chip to research partner QuTech, the quantum research institute of Delft University of Technology (TU Delft) in the Netherlands. The announcement marks a major milestone in the 10-year, $50-million collaborative relationship with TU Delft and TNO, the Dutch Organization for Applied Research, to accelerate advancements in quantum computing. Read more…

By Tiffany Trader

Fujitsu Tapped to Build 37-Petaflops ABCI System for AIST

October 10, 2017

Fujitsu announced today it will build the long-planned AI Bridging Cloud Infrastructure (ABCI) which is set to become the fastest supercomputer system in Japan Read more…

By John Russell

HPC Chips – A Veritable Smorgasbord?

October 10, 2017

For the first time since AMD's ill-fated launch of Bulldozer the answer to the question, 'Which CPU will be in my next HPC system?' doesn't have to be 'Whichever variety of Intel Xeon E5 they are selling when we procure'. Read more…

By Dairsie Latimer

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Intel Debuts Programmable Acceleration Card

October 5, 2017

With a view toward supporting complex, data-intensive applications, such as AI inference, video streaming analytics, database acceleration and genomics, Intel i Read more…

By Doug Black

OLCF’s 200 Petaflops Summit Machine Still Slated for 2018 Start-up

October 3, 2017

The Department of Energy’s planned 200 petaflops Summit computer, which is currently being installed at Oak Ridge Leadership Computing Facility, is on track t Read more…

By John Russell

US Exascale Program – Some Additional Clarity

September 28, 2017

The last time we left the Department of Energy’s exascale computing program in July, things were looking very positive. Both the U.S. House and Senate had pas Read more…

By Alex R. Larzelere

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

NERSC Scales Scientific Deep Learning to 15 Petaflops

August 28, 2017

A collaborative effort between Intel, NERSC and Stanford has delivered the first 15-petaflops deep learning software running on HPC platforms and is, according Read more…

By Rob Farber

Oracle Layoffs Reportedly Hit SPARC and Solaris Hard

September 7, 2017

Oracle’s latest layoffs have many wondering if this is the end of the line for the SPARC processor and Solaris OS development. As reported by multiple sources Read more…

By John Russell

US Coalesces Plans for First Exascale Supercomputer: Aurora in 2021

September 27, 2017

At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, in Arlington, Va., yesterday (Sept. 26), it was revealed that the "Aurora" supercompute Read more…

By Tiffany Trader

Google Releases Deeplearn.js to Further Democratize Machine Learning

August 17, 2017

Spreading the use of machine learning tools is one of the goals of Google’s PAIR (People + AI Research) initiative, which was introduced in early July. Last w Read more…

By John Russell

GlobalFoundries Puts Wind in AMD’s Sails with 12nm FinFET

September 24, 2017

From its annual tech conference last week (Sept. 20), where GlobalFoundries welcomed more than 600 semiconductor professionals (reaching the Santa Clara venue Read more…

By Tiffany Trader

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in Read more…

By Tiffany Trader

Leading Solution Providers

Amazon Debuts New AMD-based GPU Instances for Graphics Acceleration

September 12, 2017

Last week Amazon Web Services (AWS) streaming service, AppStream 2.0, introduced a new GPU instance called Graphics Design intended to accelerate graphics. The Read more…

By John Russell

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

EU Funds 20 Million Euro ARM+FPGA Exascale Project

September 7, 2017

At the Barcelona Supercomputer Centre on Wednesday (Sept. 6), 16 partners gathered to launch the EuroEXA project, which invests €20 million over three-and-a-half years into exascale-focused research and development. Led by the Horizon 2020 program, EuroEXA picks up the banner of a triad of partner projects — ExaNeSt, EcoScale and ExaNoDe — building on their work... Read more…

By Tiffany Trader

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Cray Moves to Acquire the Seagate ClusterStor Line

July 28, 2017

This week Cray announced that it is picking up Seagate's ClusterStor HPC storage array business for an undisclosed sum. "In short we're effectively transitioning the bulk of the ClusterStor product line to Cray," said CEO Peter Ungaro. Read more…

By Tiffany Trader

Intel Launches Software Tools to Ease FPGA Programming

September 5, 2017

Field Programmable Gate Arrays (FPGAs) have a reputation for being difficult to program, requiring expertise in specialty languages, like Verilog or VHDL. Easin Read more…

By Tiffany Trader

IBM Advances Web-based Quantum Programming

September 5, 2017

IBM Research is pairing its Jupyter-based Data Science Experience notebook environment with its cloud-based quantum computer, IBM Q, in hopes of encouraging a new class of entrepreneurial user to solve intractable problems that even exceed the capabilities of the best AI systems. Read more…

By Alex Woodie

Intel, NERSC and University Partners Launch New Big Data Center

August 17, 2017

A collaboration between the Department of Energy’s National Energy Research Scientific Computing Center (NERSC), Intel and five Intel Parallel Computing Cente Read more…

By Linda Barney

  • arrow
  • Click Here for More Headlines
  • arrow
Share This