Practicalities and Challenges in the Petaflops Era

By Thomas Sterling and Chirag Dekate

June 22, 2011

Every year at ISC we stop and look back at the field of HPC, which has consistently exhibited the greatest rate of change of any technology in the history of mankind. This year is particularly important as the conventional methods that have served well over the last two decades are in direct contention with the technology trends pushing us towards a new future. This is best highlighted in the context of petaflops-capable supercomputers that have become the new standard at the top end of HPC and the reemergence of Asia as a dominant player in that ethereal regime.

But what has defined this year and distinguished it from the recent past is that although the issues are clear, the future conclusions are not. Perhaps, that is the lesson: that we are in a rare state of transition the outcome of which is yet to be determined. And the debate is anything but over. Let’s consider the highlights.

Petaflop computing is now the norm worldwide with the US, Europe, and Asia all driving computation beyond 10^15 flops. Most notable was China with its deployment of Tianhe-1A exceeding 2.5 petaflops (Linpack), assuming the position of the “fastest computer in the world” in 2010. That system is now surpassed with the 8 petaflops K Computer from Japan, giving that country the top spot for the first time since the illustrious Earth-Simulator.

Asia also has significant deployment of more traditional HPC systems, providing the means for strong programs in computational science with potential long-term impact on future science and engineering disciplines. Finally, an increasing share of the integrated components in Asia is homegrown, indicating a likely future with fully native HPC systems.

This year the big debate is the future of HPC system architecture: homogeneous multicore/manycore or heterogeneous GPU-based structures. And in both cases, the issue of programming dominates. GPUs are perceived by many as the fast track to superior computing. And for some applications this has been demonstrated. Indeed, of the top four machines, three incorporate GPUs. That would suggest a clear trend. But not so fast. Of the top 500 systems, only 17 integrate GPUs as a seminal element in achieving their performance goals. That would also suggest a clear trend, but in the opposite direction.

GPUs bring an enormous combined floating-point capability in a relatively small package and at a superior power/performance envelope. The numbers are staggering, but at a cost. Sitting at the wrong end of a PCI bus, the long latencies and relatively low bandwidth demands very high data reuse and highly regular control flow to extract anything near their peak potential. And with program control residing with the general-purpose processors, the programming methods for such hybrid systems is not for the faint of heart or consistent with the mass of legacy codes upon which industry, science, and governments all rely upon and have invested in.

Thus, it is possible that such architectures as TSUBAME 2.0 are transitional in that they represent the beginnings of an empirical search that in a few years will resolve in a distinctly different system architecture, exploiting the best of both manycore and GPUs but in a balanced and well-integrated structure managed by a unified programming methodology. While many practitioners experiment, sometimes to good effect, with CUDA and the emerging OpenCL framework, many more codes and programmers remain wedded to more day-to-day productive means.

These are very exciting times but those who think they know the final answer are probably fooling themselves, if not the rest of us. After all, the new number one K supercomputer is not based on GPUs but is 3 times faster than the number two Tianhe-1A machine, which is.

The steady increase in delivered performance is also pushing the power envelope. One advantage of GPUs, when employed effectively, is a somewhat improved energy efficiency (joules/operations). But while clock rates remain relatively stable (although differing across a range of approximately 3X) the scale of the largest systems continues to grow as HPC approaches another milestone: a million cores. The tradeoff is complex, but grave concerns are warranted as the biggest machines top 10 megawatts.

This is the driving and principal constraint for ambitious projects to deliver sustained exaflops performance before the end of this decade. The International Exascale Software Project has a worldwide representation coordinating the development of a new software platform that will support exascale systems in their management and application in the next decade. Recognizing the long lead times for software and their corresponding almost prohibitive costs, the opportunity to combine investment of resources in mutually aligned directions would appear to be an essential strategy to achieve billion-way parallelism.

In the US, the DARPA sponsored UHPC program, while not expressly targeting exascale systems has initiated this year to develop suitable technologies for a petaflop in a rack at under 60 kilowatts. The European Exascale Software Initiative is to develop a roadmap to exaflops, and also in Europe, both Intel and separately, Cray, are engaged in collaborations with European researchers to drive towards exaflops. In Asia, both Japan and China have programs intended to move aggressively towards sustained exaflops for real world applications, perhaps as early as 2018. But with predictions of hundreds of megawatts required through extensions of conventional methods, what such systems will look like is far from certain, let alone how they will be programmed.

Driving the field of HPC towards new capabilities is the underlying technologies and the processor designs from which they are constructed. Intel, IBM, and AMD are all advancing their processor designs. 45 and 32 nanometer technologies are taking hold even as the number of cores per die and socket is increasing to deliver continuing increase in performance.

Intel’s Xeon E7-8870 Processor integrates 10 cores, operating at 2.7 GHz, with 30MB cache size and supporting 2 terabytes of DDR3 memory. Using Hafnium-based high-k metal gate silicon technology, the Intel chip burns 130 Watts.

Cooler is the 12-core 2.5 GHz AMD Opteron 6100 component at 45 nanometers. It draws 105 Watts and is based on their full-field EUV lithography technology. AMD plans on going to 16 cores by Q3 of this year based on 32 nanometers, while Intel is preparing their 22 nanometer Ivy-bridge processors based on 3-D TriGate transistors.

IBM’s heavy hitter continues to be the Power family with the 45 nanometer Power7 out last year, supporting a number of chip configurations between 4 and 8 cores. This will serve as the central component to the 10 petaflops Blue Waters machine to be deployed next year. Its successor, IBM Power8, is currently under development.

GPU designs continue to push the edge of the envelope in peak performance while enhancing their generality for greater utility. The NVIDIA Tesla 20-series family based on the Fermi architecture can integrate up to 512 CUDA cores with clock rates of between 1.15 and 1.4 GHz and deliver more than a half a teraflop of double precision performance. With comparable performance is the AMD FireStream 9370 series GPU based on the Cypress architecture. Both vendors are moving towards tighter system integration with AMD’s pushing its Fusion system architecture. In the software domain, it’s a head-to-head fight between CUDA and OpenCL, with strong advocates for each.

The underlying technologies are certainly not standing still. Recent graphene technology breakthroughs include UCLA reporting 300 GHz switching rates and UC Berkeley announcing new optical modulators, while IBM has implemented the first integrated circuit based on graphene transistors. 3-D stacking of dies by IBM, Xilinx, and other manufacturers is preparing HPC for higher density packaging with higher internal bandwidths and shorter latencies, while combining disparate functional components (e.g., cores, DRAM) into single integrated units.

Every year an attempt is made to capture a more meaningful representation of supercomputing based on the TOP500. The list provides extensive data but usually only discussed in terms of the highest rated machine, the lowest rated machine, and the sum of all 500 machines. But what about supercomputing for the common man; the mainstream form and capability. This year, although the top machines exhibit unique properties, the canonical system is the standard Linux commodity cluster with a peak performance of 72.4 Teraflops and a Linpack rating of 38.3 teraflops. Such a system incorporates Intel Xeon Nehalem-EP processors, integrated by IBM (HP is a close second), and interconnected with Gigabit Ethernet (InfiniBand has almost caught up). The system comprises 1,134 sockets of 6 cores each and burns 200 Kilowatts. The closest machine to this profile is number 288 on the TOP500 list.

Even though we still rate systems in teraflops, the Graph 500 list is emerging to represent a very different class of computing: data intensive processing, a domain in which the manipulation of the metadata dominates in lieu of floating point operations. Although yet to dominate, this emerging class of computing is important for many sparse problems as well as knowledge management and understanding problems that are expected to have increasing impact on the field of HPC.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

IBM Launches Commercial Quantum Network with Samsung, ORNL

December 14, 2017

In the race to commercialize quantum computing, IBM is one of several companies leading the pack. Today, IBM announced it had signed JPMorgan Chase, Daimler AG, Samsung and a number of other corporations to its IBM Q Net Read more…

By Tiffany Trader

TACC Researchers Test AI Traffic Monitoring Tool in Austin

December 13, 2017

Traffic jams and mishaps are often painful and sometimes dangerous facts of life. At this week’s IEEE International Conference on Big Data being held in Boston, researchers from TACC and colleagues will present a new Read more…

By HPCwire Staff

AMD Wins Another: Baidu to Deploy EPYC on Single Socket Servers

December 13, 2017

When AMD introduced its EPYC chip line in June, the company said a portion of the line was specifically designed to re-invigorate a single socket segment in what has become an overwhelmingly two-socket landscape in the d Read more…

By John Russell

HPE Extreme Performance Solutions

Explore the Origins of Space with COSMOS and Memory-Driven Computing

From the formation of black holes to the origins of space, data is the key to unlocking the secrets of the early universe. Read more…

Microsoft Wants to Speed Quantum Development

December 12, 2017

Quantum computing continues to make headlines in what remains of 2017 as tech giants jockey to establish a pole position in the race toward commercialization of quantum. This week, Microsoft took the next step in advanci Read more…

By Tiffany Trader

IBM Launches Commercial Quantum Network with Samsung, ORNL

December 14, 2017

In the race to commercialize quantum computing, IBM is one of several companies leading the pack. Today, IBM announced it had signed JPMorgan Chase, Daimler AG, Read more…

By Tiffany Trader

AMD Wins Another: Baidu to Deploy EPYC on Single Socket Servers

December 13, 2017

When AMD introduced its EPYC chip line in June, the company said a portion of the line was specifically designed to re-invigorate a single socket segment in wha Read more…

By John Russell

Microsoft Wants to Speed Quantum Development

December 12, 2017

Quantum computing continues to make headlines in what remains of 2017 as tech giants jockey to establish a pole position in the race toward commercialization of Read more…

By Tiffany Trader

HPC Iron, Soft, Data, People – It Takes an Ecosystem!

December 11, 2017

Cutting edge advanced computing hardware (aka big iron) does not stand by itself. These computers are the pinnacle of a myriad of technologies that must be care Read more…

By Alex R. Larzelere

IBM Begins Power9 Rollout with Backing from DOE, Google

December 6, 2017

After over a year of buildup, IBM is unveiling its first Power9 system based on the same architecture as the Department of Energy CORAL supercomputers, Summit a Read more…

By Tiffany Trader

Microsoft Spins Cycle Computing into Core Azure Product

December 5, 2017

Last August, cloud giant Microsoft acquired HPC cloud orchestration pioneer Cycle Computing. Since then the focus has been on integrating Cycle’s organization Read more…

By John Russell

GlobalFoundries, Ayar Labs Team Up to Commercialize Optical I/O

December 4, 2017

GlobalFoundries (GF) and Ayar Labs, a startup focused on using light, instead of electricity, to transfer data between chips, today announced they've entered in Read more…

By Tiffany Trader

HPE In-Memory Platform Comes to COSMOS

November 30, 2017

Hewlett Packard Enterprise is on a mission to accelerate space research. In August, it sent the first commercial-off-the-shelf HPC system into space for testing Read more…

By Tiffany Trader

US Coalesces Plans for First Exascale Supercomputer: Aurora in 2021

September 27, 2017

At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, in Arlington, Va., yesterday (Sept. 26), it was revealed that the "Aurora" supercompute Read more…

By Tiffany Trader

NERSC Scales Scientific Deep Learning to 15 Petaflops

August 28, 2017

A collaborative effort between Intel, NERSC and Stanford has delivered the first 15-petaflops deep learning software running on HPC platforms and is, according Read more…

By Rob Farber

Oracle Layoffs Reportedly Hit SPARC and Solaris Hard

September 7, 2017

Oracle’s latest layoffs have many wondering if this is the end of the line for the SPARC processor and Solaris OS development. As reported by multiple sources Read more…

By John Russell

AMD Showcases Growing Portfolio of EPYC and Radeon-based Systems at SC17

November 13, 2017

AMD’s charge back into HPC and the datacenter is on full display at SC17. Having launched the EPYC processor line in June along with its MI25 GPU the focus he Read more…

By John Russell

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Japan Unveils Quantum Neural Network

November 22, 2017

The U.S. and China are leading the race toward productive quantum computing, but it's early enough that ultimate leadership is still something of an open questi Read more…

By Tiffany Trader

GlobalFoundries Puts Wind in AMD’s Sails with 12nm FinFET

September 24, 2017

From its annual tech conference last week (Sept. 20), where GlobalFoundries welcomed more than 600 semiconductor professionals (reaching the Santa Clara venue Read more…

By Tiffany Trader

Google Releases Deeplearn.js to Further Democratize Machine Learning

August 17, 2017

Spreading the use of machine learning tools is one of the goals of Google’s PAIR (People + AI Research) initiative, which was introduced in early July. Last w Read more…

By John Russell

Leading Solution Providers

Amazon Debuts New AMD-based GPU Instances for Graphics Acceleration

September 12, 2017

Last week Amazon Web Services (AWS) streaming service, AppStream 2.0, introduced a new GPU instance called Graphics Design intended to accelerate graphics. The Read more…

By John Russell

Perspective: What Really Happened at SC17?

November 22, 2017

SC is over. Now comes the myriad of follow-ups. Inboxes are filled with templated emails from vendors and other exhibitors hoping to win a place in the post-SC thinking of booth visitors. Attendees of tutorials, workshops and other technical sessions will be inundated with requests for feedback. Read more…

By Andrew Jones

IBM Begins Power9 Rollout with Backing from DOE, Google

December 6, 2017

After over a year of buildup, IBM is unveiling its first Power9 system based on the same architecture as the Department of Energy CORAL supercomputers, Summit a Read more…

By Tiffany Trader

EU Funds 20 Million Euro ARM+FPGA Exascale Project

September 7, 2017

At the Barcelona Supercomputer Centre on Wednesday (Sept. 6), 16 partners gathered to launch the EuroEXA project, which invests €20 million over three-and-a-half years into exascale-focused research and development. Led by the Horizon 2020 program, EuroEXA picks up the banner of a triad of partner projects — ExaNeSt, EcoScale and ExaNoDe — building on their work... Read more…

By Tiffany Trader

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Tensors Come of Age: Why the AI Revolution Will Help HPC

November 13, 2017

Thirty years ago, parallel computing was coming of age. A bitter battle began between stalwart vector computing supporters and advocates of various approaches to parallel computing. IBM skeptic Alan Karp, reacting to announcements of nCUBE’s 1024-microprocessor system and Thinking Machines’ 65,536-element array, made a public $100 wager that no one could get a parallel speedup of over 200 on real HPC workloads. Read more…

By John Gustafson & Lenore Mullin

Flipping the Flops and Reading the Top500 Tea Leaves

November 13, 2017

The 50th edition of the Top500 list, the biannual publication of the world’s fastest supercomputers based on public Linpack benchmarking results, was released Read more…

By Tiffany Trader

Intel Launches Software Tools to Ease FPGA Programming

September 5, 2017

Field Programmable Gate Arrays (FPGAs) have a reputation for being difficult to program, requiring expertise in specialty languages, like Verilog or VHDL. Easin Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This