JP Morgan Buys Into FPGA Supercomputing

By Michael Feldman

July 13, 2011

One of the largest financial institutions in the world is using FPGA-based supercomputing for analyzing some of its largest and most complex credit derivative portfolios. JP Morgan, along with Maxeler Technologies, has built and deployed a state-of-the art HPC system capable of number-crunching the company’s collateralized debt obligation (CDO) portfolio in near real-time.

CDOs are instruments in which the credit assets are divided into different bundles or tranches, according to their relative risk of default. During the credit crisis of 2007-2008, CDO valuation tanked as the value of the underlying assets, mostly mortgages, fell off a cliff. Part of the problem was that many of the computer models didn’t assess the risk parameters of the various mortgages correctly. The less obvious aspect was that these instruments were so complex that it was difficult for the models using traditional computer technology to analyze these portfolios effectively.

With the credit crisis in full swing in 2008, Stephen Weston joined JP Morgan’s London office, heading up a team devoted to making the company’s financial algorithms and models run more effectively. In what started out as a blue-sky technology project almost three years ago, Weston’s group has implemented a production-ready solution that speeds up the company’s CDO risk models by a factor of more than 130. “This, to us, is a step change,” said Weston, talking about the project during a presentation at Stanford University in May.

Execution time was the critical factor. Prior to the FPGA solution, JP Morgan’s main risk model for analyzing their CDO portfolio took 8 to 12 hours to complete — an overnight run requiring a cluster of thousands of x86 cores. If the model failed to execute correctly, there was no time to resubmit the application for that day. Worse yet, the credit risks and valuation are in constant flux. That snapshot of the previous day may no longer be useful. “It was a bit like driving your car on the freeway at 90 miles per hour by looking in the rear view mirror,” said Weston. “It could be fun, but there’s a high probability it could be a destructive activity.”

With the speedup, the same risk model took four minutes, with the FPGA processing eating up just 12 seconds of that. It’s not just that they could run the models faster though. The better performance allowed them to run multiple trading/risk scenarios throughout the day. So traders can evaluate more scenarios using different combinations of default criteria. In a nutshell, the time compression allowed JP Morgan to get a better handle on the risk profile of their CDO assets.

In general, porting legacy applications like these financial risk models to FPGAs is no small task. Programming them with low-level VHDL, the traditional programming language of FPGAs, is time-consuming, tedious, and generally unsuited for application developers. Weston knew that it would be a tough sell to convince the quants and management types at the company that this could be a viable solution for a production environment.

In fact, initially JP Morgan looked at GPUs for acceleration. They ported one of their models to the graphics architecture and were able to get a 14- to 15-fold performance boost. But they thought they could do even better with FPGAs. The problem was that it was going to take about 6 months for an initial port. That’s when they went to Maxeler and initiated a proof-of-concept engagement with them.

Maxeler is a London-based technology vendor specializing in FPGA acceleration for high performance computing applications. Unlike most FPGA vendors though, Maxeler offers a vertically integrated solution: hardware, high-level compilers (Java), runtime support, development tools, and FPGA porting expertise. As such, the company is able to meet application programmers on their own turf and help them navigate the eccentricities of FPGA software development. At least, that’s Maxeler’s pitch.

With JP Morgan, it all seemed to work. With Maxeler’s help, Weston’s group was able to port the time-critical, compute-intensive pieces of their C++ risk model (the Copula and Convoluter kernels, in particular) to the FPGA platform in about 3 months. The end result was something Weston felt was sustainable for their production environment.

Part of the effort to port to risk model involved redesigning the original C++ code, which was chock full of templates and objects. Those languages structures are great for application abstraction, said Weston, but they effectively kill parallelism, and thus performance. So the first phase of the code migrations was to remove all uses of classes, templates, and other C++ abstractions that got in the way of parallelization.

With the lower level code exposed, it became much simpler to tease out the parallelism that could be exploited by the FPGAs.  In this case, the flattened C++ source was ported to Java, which the Maxeler compiler is able to convert to VHDL.

Hardware-wise, the final target system is a 40-node hybrid HPC cluster from Maxeler. Each node houses eight Xeon cores hooked up to two Xilinx Virtex-5 (SX240T) FPGAs via PCIe links. Memory is split between the CPU (24GB) and the two FPGAs (12 GB each). Two terabytes of hard disk storage are hung off an Ethernet connection.

The advantage of the FPGA is that it is built for parallelism and allow the application to be intimately mapped onto the hardware. The devices are especially suited to applications that can exploit fine-grained parallelism and very deep pipelines. Unlike linear computations on fast CPUs (~2.6 GHz), parallel computation on slower FPGAs (~200 MHz) can yield many more calculations per watt. As Weston put it, “We went from computing in time to computing in space.”

Right now the company is in the final stages of the project to integrate it with the rest of their production infrastructure. They are also looking to move the technology into other areas of their business like FX trading and high frequency trading, and in some cases are seeing even better performance improvements. Their Monte Carlo model, for example, was able to realize a 260- to 280-fold speedup using FPGA acceleration.

Apparently JP Morgan feels bullish enough about the technology to warrant a direct investment. In March, they acquired a 20 percent stake in Maxeler for an undisclosed amount. Although the investment is probably just a rounding error for the financial giant, it signals company’s interest in making sure Maxeler’s intellectual assets are intact.

There is certainly plenty of room to expand the Maxeler footprint at JP Morgan. To run all aspects of their financial business, the company currently has 14 thousand applications running on 50 thousand servers spread across more than 42 datacenters worldwide. Only a fraction of those applications will be amenable to acceleration, but each one has the potential to raise the company’s bottom line.

“If we can compress the space, the time and the energy required to do these calculations, then it has hard business value for us,” noted Weston. “It gives us, ultimately, a competitive edge.”

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

HPC Career Notes (March 2017)

March 1, 2017

In this monthly feature, we’ll keep you up-to-date on the latest career developments for individuals in the high performance computing community. Read more…

By Thomas Ayres

Intel Sets High Bar with Workforce Diversity Program Results

February 28, 2017

Intel’s impressive efforts to achieve workforce diversity and compensation equality edged up yet another notch last year according to the company’s 2016 Diversity and Inclusion Report released today. Read more…

By John Russell

Battle Brews over Trump Intentions for Funding Science

February 27, 2017

The battle over science funding – how much and for what kinds of science – Read more…

By John Russell

Google Gets First Dibs on New Skylake Chips

February 27, 2017

As part of an ongoing effort to differentiate its public cloud services, Google made good this week on its intention to bring custom Xeon Skylake chips from Intel Corp. Read more…

By George Leopold

HPE Extreme Performance Solutions

Manufacturers Reaping the Benefits of Remote Visualization

Today’s manufacturers are operating in an ever-changing atmosphere, and finding new ways to boost productivity has never been more vital.

This is why manufacturers are ramping up their investments in high performance computing (HPC), a trend which has helped give rise to the “connected factory” and Industrial Internet of Things (IIoT) concepts that are proliferating throughout the industry today. Read more…

Thomas Sterling on CREST and Academia’s Role in HPC Research

February 27, 2017

The US advances in high performance computing over many decades have been a product of the combined engagement of research centers in industry, government labs, and academia. Read more…

By Thomas Sterling, Indiana University

Advancing Modular Supercomputing with DEEP and DEEP-ER Architectures

February 24, 2017

Knowing that the jump to exascale will require novel architectural approaches capable of delivering dramatic efficiency and performance gains, researchers around the world are hard at work on next-generation HPC systems. Read more…

By Sean Thielen

Weekly Twitter Roundup (Feb. 23, 2017)

February 23, 2017

Here at HPCwire, we aim to keep the HPC community apprised of the most relevant and interesting news items that get tweeted throughout the week. Read more…

By Thomas Ayres

HPE Server Shows Low Latency on STAC-N1 Test

February 22, 2017

The performance of trade and match servers can be a critical differentiator for financial trading houses. Read more…

By John Russell

Thomas Sterling on CREST and Academia’s Role in HPC Research

February 27, 2017

The US advances in high performance computing over many decades have been a product of the combined engagement of research centers in industry, government labs, and academia. Read more…

By Thomas Sterling, Indiana University

Advancing Modular Supercomputing with DEEP and DEEP-ER Architectures

February 24, 2017

Knowing that the jump to exascale will require novel architectural approaches capable of delivering dramatic efficiency and performance gains, researchers around the world are hard at work on next-generation HPC systems. Read more…

By Sean Thielen

HPC Technique Propels Deep Learning at Scale

February 21, 2017

Researchers from Baidu’s Silicon Valley AI Lab (SVAIL) have adapted a well-known HPC communication technique to boost the speed and scale of their neural network training and now they are sharing their implementation with the larger deep learning community. Read more…

By Tiffany Trader

IDC: Will the Real Exascale Race Please Stand Up?

February 21, 2017

So the exascale race is on. And lots of organizations are in the pack. Government announcements from the US, China, India, Japan, and the EU indicate that they are working hard to make it happen – some sooner, some later. Read more…

By Bob Sorensen, IDC

TSUBAME3.0 Points to Future HPE Pascal-NVLink-OPA Server

February 17, 2017

Since our initial coverage of the TSUBAME3.0 supercomputer yesterday, more details have come to light on this innovative project. Of particular interest is a new board design for NVLink-equipped Pascal P100 GPUs that will create another entrant to the space currently occupied by Nvidia's DGX-1 system, IBM's "Minsky" platform and the Supermicro SuperServer (1028GQ-TXR). Read more…

By Tiffany Trader

Tokyo Tech’s TSUBAME3.0 Will Be First HPE-SGI Super

February 16, 2017

In a press event Friday afternoon local time in Japan, Tokyo Institute of Technology (Tokyo Tech) announced its plans for the TSUBAME3.0 supercomputer, which will be Japan’s “fastest AI supercomputer,” Read more…

By Tiffany Trader

Drug Developers Use Google Cloud HPC in the Fight Against ALS

February 16, 2017

Within the haystack of a lethal disease such as ALS (amyotrophic lateral sclerosis / Lou Gehrig’s Disease) there exists, somewhere, the needle that will pierce this therapy-resistant affliction. Read more…

By Doug Black

Azure Edges AWS in Linpack Benchmark Study

February 15, 2017

The “when will clouds be ready for HPC” question has ebbed and flowed for years. Read more…

By John Russell

For IBM/OpenPOWER: Success in 2017 = (Volume) Sales

January 11, 2017

To a large degree IBM and the OpenPOWER Foundation have done what they said they would – assembling a substantial and growing ecosystem and bringing Power-based products to market, all in about three years. Read more…

By John Russell

US, China Vie for Supercomputing Supremacy

November 14, 2016

The 48th edition of the TOP500 list is fresh off the presses and while there is no new number one system, as previously teased by China, there are a number of notable entrants from the US and around the world and significant trends to report on. Read more…

By Tiffany Trader

Lighting up Aurora: Behind the Scenes at the Creation of the DOE’s Upcoming 200 Petaflops Supercomputer

December 1, 2016

In April 2015, U.S. Department of Energy Undersecretary Franklin Orr announced that Intel would be the prime contractor for Aurora: Read more…

By Jan Rowell

IBM Wants to be “Red Hat” of Deep Learning

January 26, 2017

IBM today announced the addition of TensorFlow and Chainer deep learning frameworks to its PowerAI suite of deep learning tools, which already includes popular offerings such as Caffe, Theano, and Torch. Read more…

By John Russell

D-Wave SC16 Update: What’s Bo Ewald Saying These Days

November 18, 2016

Tucked in a back section of the SC16 exhibit hall, quantum computing pioneer D-Wave has been talking up its new 2000-qubit processor announced in September. Forget for a moment the criticism sometimes aimed at D-Wave. This small Canadian company has sold several machines including, for example, ones to Lockheed and NASA, and has worked with Google on mapping machine learning problems to quantum computing. In July Los Alamos National Laboratory took possession of a 1000-quibit D-Wave 2X system that LANL ordered a year ago around the time of SC15. Read more…

By John Russell

Enlisting Deep Learning in the War on Cancer

December 7, 2016

Sometime in Q2 2017 the first ‘results’ of the Joint Design of Advanced Computing Solutions for Cancer (JDACS4C) will become publicly available according to Rick Stevens. He leads one of three JDACS4C pilot projects pressing deep learning (DL) into service in the War on Cancer. Read more…

By John Russell

Tokyo Tech’s TSUBAME3.0 Will Be First HPE-SGI Super

February 16, 2017

In a press event Friday afternoon local time in Japan, Tokyo Institute of Technology (Tokyo Tech) announced its plans for the TSUBAME3.0 supercomputer, which will be Japan’s “fastest AI supercomputer,” Read more…

By Tiffany Trader

HPC Startup Advances Auto-Parallelization’s Promise

January 23, 2017

The shift from single core to multicore hardware has made finding parallelism in codes more important than ever, but that hasn’t made the task of parallel programming any easier. Read more…

By Tiffany Trader

Leading Solution Providers

CPU Benchmarking: Haswell Versus POWER8

June 2, 2015

With OpenPOWER activity ramping up and IBM’s prominent role in the upcoming DOE machines Summit and Sierra, it’s a good time to look at how the IBM POWER CPU stacks up against the x86 Xeon Haswell CPU from Intel. Read more…

By Tiffany Trader

BioTeam’s Berman Charts 2017 HPC Trends in Life Sciences

January 4, 2017

Twenty years ago high performance computing was nearly absent from life sciences. Today it’s used throughout life sciences and biomedical research. Genomics and the data deluge from modern lab instruments are the main drivers, but so is the longer-term desire to perform predictive simulation in support of Precision Medicine (PM). There’s even a specialized life sciences supercomputer, ‘Anton’ from D.E. Shaw Research, and the Pittsburgh Supercomputing Center is standing up its second Anton 2 and actively soliciting project proposals. There’s a lot going on. Read more…

By John Russell

Nvidia Sees Bright Future for AI Supercomputing

November 23, 2016

Graphics chipmaker Nvidia made a strong showing at SC16 in Salt Lake City last week. Read more…

By Tiffany Trader

TSUBAME3.0 Points to Future HPE Pascal-NVLink-OPA Server

February 17, 2017

Since our initial coverage of the TSUBAME3.0 supercomputer yesterday, more details have come to light on this innovative project. Of particular interest is a new board design for NVLink-equipped Pascal P100 GPUs that will create another entrant to the space currently occupied by Nvidia's DGX-1 system, IBM's "Minsky" platform and the Supermicro SuperServer (1028GQ-TXR). Read more…

By Tiffany Trader

Is Liquid Cooling Ready to Go Mainstream?

February 13, 2017

Lost in the frenzy of SC16 was a substantial rise in the number of vendors showing server oriented liquid cooling technologies. Three decades ago liquid cooling was pretty much the exclusive realm of the Cray-2 and IBM mainframe class products. That’s changing. We are now seeing an emergence of x86 class server products with exotic plumbing technology ranging from Direct-to-Chip to servers and storage completely immersed in a dielectric fluid. Read more…

By Steve Campbell

IDG to Be Bought by Chinese Investors; IDC to Spin Out HPC Group

January 19, 2017

US-based publishing and investment firm International Data Group, Inc. (IDG) will be acquired by a pair of Chinese investors, China Oceanwide Holdings Group Co., Ltd. Read more…

By Tiffany Trader

Dell Knights Landing Machine Sets New STAC Records

November 2, 2016

The Securities Technology Analysis Center, commonly known as STAC, has released a new report characterizing the performance of the Knight Landing-based Dell PowerEdge C6320p server on the STAC-A2 benchmarking suite, widely used by the financial services industry to test and evaluate computing platforms. The Dell machine has set new records for both the baseline Greeks benchmark and the large Greeks benchmark. Read more…

By Tiffany Trader

What Knights Landing Is Not

June 18, 2016

As we get ready to launch the newest member of the Intel Xeon Phi family, code named Knights Landing, it is natural that there be some questions and potentially some confusion. Read more…

By James Reinders, Intel

  • arrow
  • Click Here for More Headlines
  • arrow
Share This