Dell to Build 10-Petaflop Supercomputer For Science

By Michael Feldman

September 22, 2011

The Texas Advanced Computing Center (TACC) has revealed plans to deploy a cutting-edge petascale supercomputer courtesy of a $27.5 million dollar NSF award. Built by Dell, the system will consist of 2 petaflops of Sandy Bridge-EP processors with an 8 petaflop boost from Intel’s Many Integrated Core (MIC) coprocessors. The machine is scheduled to boot up in late 2012 and be ready for production in January 2013.

Not only is this Dell’s first petascale system — at least the first one announced publicly — it will likely be the first deployment of Intel’s commercial MIC technology. In this case, the chips in question are pre-production versions of Knights Corner, the first commercial part in that product line. These early chips will be identical to the future production parts.

Stampede, as the system will be called, is meant to serve both traditional number crunching HPC applications and data-driven analytics applications within NSF’s eXtreme Digital (XD) user community. XD includes the Extreme Science and Engineering Discovery Environment (XSEDE) project, the sucessor to TeraGrid that encompasses more than a dozen universities and two research labs. At 10 teraflops, Stampede will be the most powerful resource for XD users.

According to Jay Boisseau, TACC Director and PI of the Stampede project, the system is expected to have several hundred projects running on it from day one. “We want to bring in users with big data sets that are doing large-scale analyses, as well as the simulations types of users,” he told HPCwire.

Data-intensive science applications include traditional ones like bioinformatics, but also codes from geosciences and astronomy — application domains that are already accumulating large amounts of digital data. Boisseau thinks as much as half of Stampede’s resources will be devoted to these types of applications.

The data-intensive support will bring in a new set of users, many of which are not as HPC savvy as the traditional simulations folks. For that, Boisseau is planning to develop a much richer software environment for this group, including new application portals and gateways, as was begun under the TeraGrid project. In addition, they will also look to bring in experts in statistics, data mining, data management, and so on, in order to support the data-driven application domain.

Some of the expertise and software resources are already built into the project via university collaborations. Besides The University of Texas at Austin, partner schools include Clemson University, University of Colorado at Boulder, Cornell University, Indiana University, Ohio State University, and The University of Texas at El Paso.

Hardware-wise, the foundation of Stampede is a 2 petaflop cluster with 6,400 x86 compute nodes, lashed together with FDR (56 Gbps) InfiniBand from Mellanox. Each node will house two of Intel’s 8-core Xeon E5 (aka Sandy Bridge-EP) and 32 GB of DRAM.

Stampede will also include 16 big memory nodes, each sporting 1 terabyte of DRAM and 2 NVIDIA GPUs. Memory-wise, that’s not exactly in SGI Altix UV territory, but it’s a respectable capacity for extra-large SMP applications. Boisseau says they’re also considering ScaleMP’s virtual SMP solution to construct a shared memory environment across all 16 TB. The shared memory sub-cluster is slated to be used for some of the big data analytics applications that Stampede will host.

The cluster will also be hooked up to to Lustre storage nodes, also suppled by Dell. It will consist of 14 PB of disk, and deliver an aggregated bandwidth of 150 GB/second. “Over the lifetime of the project we’re expecting that to grow substantially both in capacity and bandwidth over the lifetime of the system,” said Boisseau.

The Dell system was developed by its Data Center Solutions division, under the code-name Zeus. Although the technology will debut in Stampede, the company is expecting to make the Zeus product generally available for “hyperscale” supercomputing in 2012.

Stampede’s base cluster and storage nodes represent the lion’s share of the NSF funding at $25 million. The remaining $2.5 million will go toward 8 petaflops worth of MIC coprocessors, which will be hooked into the x86 nodes via PCIe 3.0 links. MIC is Intel’s x86-based manycore HPC architecture aimed at highly parallel codes, and competes head on with NVIDIA’s Tesla and AMD’s Firestream GPUS.

GPGPU enthusiasts were not completely slighted though. Besides the GPUs in the shared memory nodes, 128 of the 6,400 regular nodes will be outfitted with NVIDIA’s next-generation Kepler GPUs to support remote visualization. Kepler is the successor to Fermi, NVIDIA’s current GPU architecture. Tesla implementations of Kepler aimed at HPC servers should begin shipping sometime in 2012.

Intel has not announced an official launch date for the Knights Corner MIC product, but it should be generally available sometime in 2013, or perhaps late 2012 if Intel’s 22nm process technology ramps up more quickly. The actual number of MICs in Stampede is not public, but Intel has promised them enough to deliver 8 peak petaflops.

Using a little quick math, each MIC chip will probably need to deliver at least 1.3 to 1.5 double precision teraflops to hit the 8 petaflop performance target. Coincidentally, the NVIDIA’s Kepler GPU is also expected to deliver about 1.3 to 1.5 double precision teraflops. Note that the first MIC parts will be implemented with Intel’s Tri-Gate 22nm technology, while the Kepler GPUs will be manufactured on standard 28nm technology.

At this point, Boisseau is expecting to receive all the Intel MIC coprocessors sometime this fall, possibly in time for a Linpack run at the November’s TOP500. By that time, all the Sandy Bridge compute nodes should be fully deployed. If all goes according to plan, early access users should be able to start running codes on the machine by December 2012.

Although MIC will support a number of parallel computing models, the most straightforward one is OpenMP. This will be especially advantageous for users with hybrid MPI-OpenMP codes. The idea would be to just offload the OpenMP chunks to the coprocessors in order to parallelize those loops. Users with straight MPI codes will need to do more work to tap into MIC acceleration.

There is already an upgraded version of Stampede on the drawing board. About two years into the project, TACC is planning to deploy the second generation MIC coprocessors, with another (smaller) batch of chips. The goal is to add 5 more petaflops to the system, bringing its grand total to 15 peak petaflops sometime around the middle of the decade.

The NSF is will be funding Stampede for at least four years. Besides the inital $27.5 million outlay to build and install the system, an additional $24 million or so for system operation and support is expected to be on the table soon, bringing the total Stampede investment to more than $50 million. The project also includes an option for renewal in 2017, which would result in the deployment of an even larger and more powerful machine toward the end of the decade.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Tribute: Dr. Bob Borchers, 1936-2018

June 21, 2018

Dr. Bob Borchers, a leader in the high performance computing community for decades, passed away peacefully in Maui, Hawaii, on June 7th. His memorial service will be held on June 22nd in Reston, Virginia. Dr. Borchers Read more…

By Ann Redelfs

ISC 2018 Preview from @hpcnotes

June 21, 2018

Prepare for your social media feed to be saturated with #HPC, #ISC18, #Top500, etc. Prepare for your mainstream media to talk about supercomputers (in between the hourly commentary on Brexit, the FIFA World Cup, or US pr Read more…

By Andrew Jones

AMD’s EPYC Road to Redemption in Six Slides

June 21, 2018

A year ago AMD returned to the server market with its EPYC processor line. The earth didn’t tremble but folks took notice. People remember the Opteron fondly but later versions of the Bulldozer line not so much. Fast f Read more…

By John Russell

HPE Extreme Performance Solutions

HPC and AI Convergence is Accelerating New Levels of Intelligence

Data analytics is the most valuable tool in the digital marketplace – so much so that organizations are employing high performance computing (HPC) capabilities to rapidly collect, share, and analyze endless streams of data. Read more…

IBM Accelerated Insights

Preview the World’s Smartest Supercomputer at ISC 2018

Introducing an accelerated IT infrastructure for HPC & AI workloads Read more…

Why Student Cluster Competitions are Better than World Cup

June 21, 2018

My last article about the ISC18 Student Cluster Competition, titled “World Cup is Lame Compared to This Competition”, may have implied that I believe Student Cluster Competitions are better than World Cup soccer in s Read more…

By Dan Olds

ISC 2018 Preview from @hpcnotes

June 21, 2018

Prepare for your social media feed to be saturated with #HPC, #ISC18, #Top500, etc. Prepare for your mainstream media to talk about supercomputers (in between t Read more…

By Andrew Jones

AMD’s EPYC Road to Redemption in Six Slides

June 21, 2018

A year ago AMD returned to the server market with its EPYC processor line. The earth didn’t tremble but folks took notice. People remember the Opteron fondly Read more…

By John Russell

European HPC Summit Week and PRACEdays 2018: Slaying Dragons and SHAPEing Futures One SME at a Time

June 20, 2018

The University of Ljubljana in Slovenia hosted the third annual EHPCSW18 and fifth annual PRACEdays18 events which opened May 29, 2018. The conference was chair Read more…

By Elizabeth Leake (STEM-Trek for HPCwire)

Cray Introduces All Flash Lustre Storage Solution Targeting HPC

June 19, 2018

Citing the rise of IOPS-intensive workflows and more affordable flash technology, Cray today introduced the L300F, a scalable all-flash storage solution whose p Read more…

By John Russell

Sandia to Take Delivery of World’s Largest Arm System

June 18, 2018

While the enterprise remains circumspect on prospects for Arm servers in the datacenter, the leadership HPC community is taking a bolder, brighter view of the x86 server CPU alternative. Amongst current and planned Arm HPC installations – i.e., the innovative Mont-Blanc project, led by Bull/Atos, the 'Isambard’ Cray XC50 going into the University of Bristol, and commitments from both Japan and France among others -- HPE is announcing that it will be supply the United States National Nuclear Security Administration (NNSA) with a 2.3 petaflops peak Arm-based system, named Astra. Read more…

By Tiffany Trader

The Machine Learning Hype Cycle and HPC

June 14, 2018

Like many other HPC professionals I’m following the hype cycle around machine learning/deep learning with interest. I subscribe to the view that we’re probably approaching the ‘peak of inflated expectation’ but not quite yet starting the descent into the ‘trough of disillusionment. This still raises the probability that... Read more…

By Dairsie Latimer

Xiaoxiang Zhu Receives the 2018 PRACE Ada Lovelace Award for HPC

June 13, 2018

Xiaoxiang Zhu, who works for the German Aerospace Center (DLR) and Technical University of Munich (TUM), was awarded the 2018 PRACE Ada Lovelace Award for HPC for her outstanding contributions in the field of high performance computing (HPC) in Europe. Read more…

By Elizabeth Leake

U.S Considering Launch of National Quantum Initiative

June 11, 2018

Sometime this month the U.S. House Science Committee will introduce legislation to launch a 10-year National Quantum Initiative, according to a recent report by Read more…

By John Russell

MLPerf – Will New Machine Learning Benchmark Help Propel AI Forward?

May 2, 2018

Let the AI benchmarking wars begin. Today, a diverse group from academia and industry – Google, Baidu, Intel, AMD, Harvard, and Stanford among them – releas Read more…

By John Russell

How the Cloud Is Falling Short for HPC

March 15, 2018

The last couple of years have seen cloud computing gradually build some legitimacy within the HPC world, but still the HPC industry lies far behind enterprise I Read more…

By Chris Downing

US Plans $1.8 Billion Spend on DOE Exascale Supercomputing

April 11, 2018

On Monday, the United States Department of Energy announced its intention to procure up to three exascale supercomputers at a cost of up to $1.8 billion with th Read more…

By Tiffany Trader

Deep Learning at 15 PFlops Enables Training for Extreme Weather Identification at Scale

March 19, 2018

Petaflop per second deep learning training performance on the NERSC (National Energy Research Scientific Computing Center) Cori supercomputer has given climate Read more…

By Rob Farber

Lenovo Unveils Warm Water Cooled ThinkSystem SD650 in Rampup to LRZ Install

February 22, 2018

This week Lenovo took the wraps off the ThinkSystem SD650 high-density server with third-generation direct water cooling technology developed in tandem with par Read more…

By Tiffany Trader

ORNL Summit Supercomputer Is Officially Here

June 8, 2018

Oak Ridge National Laboratory (ORNL) together with IBM and Nvidia celebrated the official unveiling of the Department of Energy (DOE) Summit supercomputer toda Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Hennessy & Patterson: A New Golden Age for Computer Architecture

April 17, 2018

On Monday June 4, 2018, 2017 A.M. Turing Award Winners John L. Hennessy and David A. Patterson will deliver the Turing Lecture at the 45th International Sympo Read more…

By Staff

Leading Solution Providers

SC17 Booth Video Tours Playlist

Altair @ SC17

Altair

AMD @ SC17

AMD

ASRock Rack @ SC17

ASRock Rack

CEJN @ SC17

CEJN

DDN Storage @ SC17

DDN Storage

Huawei @ SC17

Huawei

IBM @ SC17

IBM

IBM Power Systems @ SC17

IBM Power Systems

Intel @ SC17

Intel

Lenovo @ SC17

Lenovo

Mellanox Technologies @ SC17

Mellanox Technologies

Microsoft @ SC17

Microsoft

Penguin Computing @ SC17

Penguin Computing

Pure Storage @ SC17

Pure Storage

Supericro @ SC17

Supericro

Tyan @ SC17

Tyan

Univa @ SC17

Univa

Google Chases Quantum Supremacy with 72-Qubit Processor

March 7, 2018

Google pulled ahead of the pack this week in the race toward "quantum supremacy," with the introduction of a new 72-qubit quantum processor called Bristlecone. Read more…

By Tiffany Trader

Google I/O 2018: AI Everywhere; TPU 3.0 Delivers 100+ Petaflops but Requires Liquid Cooling

May 9, 2018

All things AI dominated discussion at yesterday’s opening of Google’s I/O 2018 developers meeting covering much of Google's near-term product roadmap. The e Read more…

By John Russell

Nvidia Ups Hardware Game with 16-GPU DGX-2 Server and 18-Port NVSwitch

March 27, 2018

Nvidia unveiled a raft of new products from its annual technology conference in San Jose today, and despite not offering up a new chip architecture, there were still a few surprises in store for HPC hardware aficionados. Read more…

By Tiffany Trader

Pattern Computer – Startup Claims Breakthrough in ‘Pattern Discovery’ Technology

May 23, 2018

If it weren’t for the heavy-hitter technology team behind start-up Pattern Computer, which emerged from stealth today in a live-streamed event from San Franci Read more…

By John Russell

Part One: Deep Dive into 2018 Trends in Life Sciences HPC

March 1, 2018

Life sciences is an interesting lens through which to see HPC. It is perhaps not an obvious choice, given life sciences’ relative newness as a heavy user of H Read more…

By John Russell

Intel Pledges First Commercial Nervana Product ‘Spring Crest’ in 2019

May 24, 2018

At its AI developer conference in San Francisco yesterday, Intel embraced a holistic approach to AI and showed off a broad AI portfolio that includes Xeon processors, Movidius technologies, FPGAs and Intel’s Nervana Neural Network Processors (NNPs), based on the technology it acquired in 2016. Read more…

By Tiffany Trader

Google Charts Two-Dimensional Quantum Course

April 26, 2018

Quantum error correction, essential for achieving universal fault-tolerant quantum computation, is one of the main challenges of the quantum computing field and it’s top of mind for Google’s John Martinis. At a presentation last week at the HPC User Forum in Tucson, Martinis, one of the world's foremost experts in quantum computing, emphasized... Read more…

By Tiffany Trader

Cray Rolls Out AMD-Based CS500; More to Follow?

April 18, 2018

Cray was the latest OEM to bring AMD back into the fold with introduction today of a CS500 option based on AMD’s Epyc processor line. The move follows Cray’ Read more…

By John Russell

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This