A funny thing happened on the way to 4G telecommunications. When Texas Instruments (TI) added floating point smarts to its new digital signal processor (DSP) to support the fourth-generation wireless standard, it found itself with a commercial chip that had some of the most impressive flops/watt performance on the planet. And that got some of the folks at TI wondering if they could parlay that into the ethereal world of high performance computing.
Arnon Friedmann, TI’s Business Manager for Multicore DSP, and who now directs a budding HPC group at the company, says the effort to create a high performance computing presence with its latest DSP architecture is now underway, and there don’t appear to be any showstoppers. “There aren’t any doubts whether the device is capable of scaling to [HPC] products,” Friedmann told HPCwire. “It’s really just a matter of how well the applications can run on the device.”
According to Friedmann a “handful” of universities and commercial HPC customers have already expressed interest in the DSP technology and have been collaborating with engineers at TI to port their applications to the new DSP. “We’re also talking with a number of people who build HPC systems,” he says. “I wouldn’t say that you’re going to see anything immediately, but we’re getting quite a bit of interest.”
The DSP product line at the center of this effort is TI’s new TMS320C66x (aka C66x) series, a multicore chip they designed for 4G cellular base stations and radio network controllers. Launched in November 2010, the C66x is a 40nm chip that comes in single-core, dual-core, quad-core and eight-core variations. Its most distinguishing feature is the addition of floating point instructions, which were incorporated to support the more complex processing required for 4G wireless communications. The previous generation C64x series DSPs supported only fixed point math.
The C66x is implemented with TI’s new KeyStone architecture, which incorporates an eight-way VLIW architecture, a high-speed switch fabric called TeraNet, and a multicore navigator and DMA system that manages packet sending to other cores and peripherals. All the C66x products come with 512 KB of dedicated L2 cache per core, along with 32 KB of L1 cache for both instructions and data.
In its eight-core 1.25 GHz implementation, the C66x delivers 160 single precision (SP) gigaflops, while sucking up just 10 watts of power. That works out to an impressive 16 SP gigaflops/watt. Energy efficiency is a hallmark of DSPs, in general, since they typically populate systems (like the aforementioned cellular base station towers and radio network controllers), where power and cooling is in short supply.
The first HPC-friendly C66x-based device is a PCIe card, which sports four of the eight-core DSPs running at 1.0 GHz. Built by Advantech, a TI parter, the half-length PCIe card delivers 512 SP gigaflops at a modest 50 watts. On-board memory consists of 4 GB of 1333 MHz DDR3 RAM, with full ECC support. They’re also working on a full-length card, with eight DSPs, twice as much memory, and twice the performance.
Compared to the latest Tesla 20-series cards from NVIDIA, which delivers 1331 SP gigaflops at 225 watts, the Advantech hardware is the more impressive product, at least from a peak performance-per-watt perspective. The DSP-equipped card delivers 10 gigaflops/watt while the NVIDIA Tesla module puts out 6 gigaflops/watt. Those are for single precision flops. For double precision, the TI DSP delivers 3/8 of single precision performance, while the Tesla GPU delivers 1/2. In either case though, the TI DSP is the more energy efficient choice.
By the time the Kepler GPUs come out in 2012, and Intel’s first Many Integrated Core (MIC) coprocessor appears in 2013, those performance per watt numbers should be more competitive, but presumably TI can move its DSP performance up the ladder as well.
Like NVIDIA and Intel, Texas Instruments can leverage its volume position in a market much larger than HPC. In TI’s case, they expect to sell their C66x DSPs by the millions each year (as they did with the previous generation C64x line) in order to power the growing 4G wireless infrastructure. The company’s dominant position in that end of the market speaks well for the resources they could throw at this architecture.
The open question is how to do HPC-style software development on DSPs. The good news is that digital signal processors act more or less like a CPU. Unlike GPUs or FPGAs, the TI DSP doesn’t require a special programming language and doesn’t need a host processor to drive it. So the entire application can be run on the DSP, with nothing fancier than traditional C language tools, parallelized with OpenMP and/or MPI. TI offers all of this in its software development kit, including a C compiler, runtime, as well as the appropriate floating point math and parallel programming support. “We have a pretty good history of running complex systems on these DSPs,” says Friedmann.
The HPC group at TI they realize they will need to beef up their software tools to compete with the more mature parallel programming environments offered by Intel and NVIDIA. They’re even considering porting OpenCL to their DSP, but according to Friedmann, would like to see greater uptake in the community before they begin that effort. But their DSP compiler technology is mature, being based on a ten year-old VLIW architecture that has been refined over that period of time. The addition of floating point instructions entailed a relatively straightforward update to the base compiler, says Friedmann.
The new C66x DSPs are already being used in HPC-like workloads in a few specialized applications like semiconductor and LCD flat panel inspection systems. In the past, these set-ups employed hundreds of fixed-point DSPs, but with FP-capable parts now available, they can use fewer parts, and the applications are being updated accordingly. They are also seeing adoption in radar systems and medical imaging, which, again, can take advantage of the DSP’s new floating point prowess. In all of these cases, performance is a key element, since these applications rely on real time, compute-intensive processing.
Currently the company is in the process of running benchmarks against it new floating point processor to demonstrate the extent of its HPC potential. There may be certain types of algorithms that the DSP is particularly adept at. For example, running fast Fourier transforms (FFTs) on the C66x is about 8 to 10 times more efficient than using latest GPUs, according to Friedmann. Specific benchmark results will be forthcoming shortly.
The high performance computing effort at TI is still in its infancy as they learn how to navigate the HPC market and maneuver around established HPC players Intel, NVIDIA, and AMD. In the meantime, a team of 8 to 10 TI engineers has been keeping itself busy collecting applications from interested customers and helping to port and benchmark the codes. At SC11 next month, Friedmann will be demonstrating the DSP card and talking up the potential of the technology. “I do expect it’s going to get interesting in 2012,” says Friedmann.