Intel Sets High Water Mark of One Teraflop with ‘Knights Corner’

By Michael Feldman

November 16, 2011

At SC11 in Seattle, Intel showed off an early silicon version of Intel’s Many Integrated Core (MIC) “Knight Corner,” the codename for its first commercial product based on their MIC architecture. The demonstration was performed for the benefit of reporters and analysts, who got to see the new chip in action at a press briefing here on Tuesday afternoon. The jury-rigged test setup had the chip running DGEMM (the double precision floating point version of the general matrix multiply algorithm) at a rather amazing one teraflop/second.

Rajeeb Hazra, GM of Intel’s Technical Computing, Datacenter and Connected Systems Group, waved one of the pre-production chip in front of audience, saying that they had produced “a few tens of chips” for early testing. According to Hazra, they were manufactured at one of their fabs using their 22nm process technology.

He was less forthcoming about other details on the chip however, dodging questions about core counts (once again reiterating that it will be more than 50), processor clock speed, and power consumption. On that last point, it’s likely that TDP is likely to be in the GPU-like 200 to 275 watt range, inasmuch as the coprocessors are destined for servers and workstations, which only have so much leeway with regard to power envelopes.

I did manage to find out the Knight Corner does indeed support ECC memory, although it wasn’t turned on for the DGEMM demo. According to the attending engineer, it doesn’t effect the flops on that code, but will lower performance somewhat on more general applications.

As Hazra pointed out in the briefing, this is the first general-purpose chip in history that is able to hit the one teraflop mark. And while that is true, it should be noted that NVIDIA’s “Kepler” GPU, which is likely to be in production prior to Knights Corner, will probably deliver somewhere between 1.2 to 1.4 double precision teraflops, or about twice that of the current Fermi-class Tesla GPUs.

Nonetheless, the early edition Knight Corner is a remarkable achievement by Intel, and something of a watershed moment for x86 chip making. In 1997, ASCI Red, an Pentium II Xeon-based supercomputer, needed 9,298 processor to hit this same one teraflop mark. And that machine, which was spread out over 72 cabinets, sucked up 800 KW of power.

The production Knights Corner chips delivered in a year or so may actually end up delivering something north of one teraflop, so it’s not a given that NVIDIA will win the flops battle in 2012. In any case, Intel is probably not overly concerned about absolute performance. It’s made a good case that the programming model for MIC will be the real differentiator here.

For some time Intel has been touting that its own x86 parallel compiler and development tools will offer complete support for MIC coprocessors, making the application porting effort much more productive than CUDA. When the code in question incorporates MIC-friendly parallel frameworks like OpenMP, initial porting may amount to no more than a recompile and a re-link. If that pans out as advertised, the ease-of-programming feature will ultimately be the deciding factor in MIC’s favor.

During the press briefing, R. Glenn Brook, a computational scientist at the National Institute for Computational Sciences, University of Tennessee, reported that his team had ported tens of million of lines of legacy science codes to MIC (on prototype “Knights Ferry” coprocessor-powered clusters) in under three months. According to Brook, some of these applications will probably never be ported to GPUs because the complexity of these codes would make the endeavor too onerous.

Clearly, Intel sees their manycore architecture as a path to exascale. In this realm power efficiency is the whole ball game, and MIC is inherently superior to more traditional x86 CPUs in this regard. If we assume Knights Corner is a 250 watt part, it will be able to deliver 4 gigaflops/watt today. That still a far cry from the 50 gigaflops/watt target for an exaflop system (which also has to include memory, interconnects, power supplies, etc.), but the performance/watt trajectory is much more in line with exascale efficiency compared Intel’s mainstream Xeon line.

Speaking of which, Hazra offered up some interesting performance stats on their new Xeon E5 (Sandy Bridge EP) processors. According to Intel testing, the Xeon E5-2680 chip delivers 172 gigaflops of peak performance. And while that bests any of the AMD Opteron 6200 series processors, it’s still well under 2 gigaflops/watt (hard to tell exactly since Intel hasn’t provided TDPs on these pre-launched parts). From that perspective, a traditional Xeon, at least without an on-chip MIC coprocessor, has a rather uncertain future in the exascale era.

But at least for the early petascale era, the Xeon processor is doing just fine. The previous generation Xeon 5600 line is in 223 of the top 500 supercomputers in the world. And the aforementioned Xeon E5 is already in 10 systems, despite the fact that the product won’t be officially launched until the first half of 2012 (which, to my mind, makes the term launch kind of meaningless).

In addition, the E5 will also be making an appearance in future top 10 systems, like GENCI’s 2-petaflop “Curie” super. It is also the CPU of choice for TACC’s 10-petaflop “Stampede” supercomputer, which is scheduled for deployment in early 2013. In this case though, the E5 will be eclipsed by the Knights Corner coprocessors, which will provide 8 of those 10 petaflops. If that trend holds, then MIC will indeed be Intel’s dominant supercomputing architecture for the second half the decade.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

At Long Last, Supercomputing Helps to Map the Poles

August 22, 2019

“For years,” Paul Morin wrote, “those of us that made maps of the Poles apologized. We apologized for the blank spaces on maps, we apologized for mountains being in the wrong place and out-of-date information.” Read more…

By Oliver Peckham

Xilinx Says Its New FPGA is World’s Largest

August 21, 2019

In this age of exploding “technology disaggregation” – in which the Big Bang emanating from the Intel x86 CPU has produced significant advances in CPU chips and a raft of alternative, accelerated architectures... Read more…

By Doug Black

Supercomputers Generate Universes to Illuminate Galactic Formation

August 20, 2019

With advanced imaging and satellite technologies, it’s easier than ever to see a galaxy – but understanding how they form (a process that can take billions of years) is a different story. Now, a team of researchers f Read more…

By Oliver Peckham

AWS Solution Channel

Efficiency and Cost-Optimization for HPC Workloads – AWS Batch and Amazon EC2 Spot Instances

High Performance Computing on AWS leverages the power of cloud computing and the extreme scale it offers to achieve optimal HPC price/performance. With AWS you can right size your services to meet exactly the capacity requirements you need without having to overprovision or compromise capacity. Read more…

HPE Extreme Performance Solutions

Bring the combined power of HPC and AI to your business transformation

FPGA (Field Programmable Gate Array) acceleration cards are not new, as they’ve been commercially available since 1984. Typically, the emphasis around FPGAs has centered on the fact that they’re programmable accelerators, and that they can truly offer workload specific hardware acceleration solutions without requiring custom silicon. Read more…

IBM Accelerated Insights

Keys to Attracting the Newest HPC Talent – Post-Millennials

[Connect with HPC users and learn new skills in the IBM Spectrum LSF User Community.]

For engineers and scientists growing up in the 80s, the current state of HPC makes perfect sense. Read more…

Singularity Moves Up the Container Value Chain

August 20, 2019

The enterprise version of the Singularity HPC container platform released this week by Sylabs is designed to allow users to create, secure and share the high-end containers in self-hosted production deployments. The e Read more…

By George Leopold

At Long Last, Supercomputing Helps to Map the Poles

August 22, 2019

“For years,” Paul Morin wrote, “those of us that made maps of the Poles apologized. We apologized for the blank spaces on maps, we apologized for mountains being in the wrong place and out-of-date information.” Read more…

By Oliver Peckham

IBM Deepens Plunge into Open Source; OpenPOWER to Join Linux Foundation

August 20, 2019

IBM today announced it was contributing the instruction set (ISA) for its Power microprocessor and the designs for the Open Coherent Accelerator Processor Inter Read more…

By John Russell

Ayar Labs to Demo Photonics Chiplet in FPGA Package at Hot Chips

August 19, 2019

Silicon startup Ayar Labs continues to gain momentum with its DARPA-backed optical chiplet technology that puts advanced electronics and optics on the same chip Read more…

By Tiffany Trader

Scientists to Tap Exascale Computing to Unlock the Mystery of our Accelerating Universe

August 14, 2019

The universe and everything in it roared to life with the Big Bang approximately 13.8 billion years ago. It has continued expanding ever since. While we have a Read more…

By Rob Johnson

AI is the Next Exascale – Rick Stevens on What that Means and Why It’s Important

August 13, 2019

Twelve years ago the Department of Energy (DOE) was just beginning to explore what an exascale computing program might look like and what it might accomplish. Today, DOE is repeating that process for AI, once again starting with science community town halls to gather input and stimulate conversation. The town hall program... Read more…

By Tiffany Trader and John Russell

Cray Wins NNSA-Livermore ‘El Capitan’ Exascale Contract

August 13, 2019

Cray has won the bid to build the first exascale supercomputer for the National Nuclear Security Administration (NNSA) and Lawrence Livermore National Laborator Read more…

By Tiffany Trader

AMD Launches Epyc Rome, First 7nm CPU

August 8, 2019

From a gala event at the Palace of Fine Arts in San Francisco yesterday (Aug. 7), AMD launched its second-generation Epyc Rome x86 chips, based on its 7nm proce Read more…

By Tiffany Trader

Lenovo Drives Single-Socket Servers with AMD Epyc Rome CPUs

August 7, 2019

No summer doldrums here. As part of the AMD Epyc Rome launch event in San Francisco today, Lenovo announced two new single-socket servers, the ThinkSystem SR635 Read more…

By Doug Black

High Performance (Potato) Chips

May 5, 2006

In this article, we focus on how Procter & Gamble is using high performance computing to create some common, everyday supermarket products. Tom Lange, a 27-year veteran of the company, tells us how P&G models products, processes and production systems for the betterment of consumer package goods. Read more…

By Michael Feldman

Supercomputer-Powered AI Tackles a Key Fusion Energy Challenge

August 7, 2019

Fusion energy is the Holy Grail of the energy world: low-radioactivity, low-waste, zero-carbon, high-output nuclear power that can run on hydrogen or lithium. T Read more…

By Oliver Peckham

Cray, AMD to Extend DOE’s Exascale Frontier

May 7, 2019

Cray and AMD are coming back to Oak Ridge National Laboratory to partner on the world’s largest and most expensive supercomputer. The Department of Energy’s Read more…

By Tiffany Trader

Graphene Surprises Again, This Time for Quantum Computing

May 8, 2019

Graphene is fascinating stuff with promise for use in a seeming endless number of applications. This month researchers from the University of Vienna and Institu Read more…

By John Russell

AMD Verifies Its Largest 7nm Chip Design in Ten Hours

June 5, 2019

AMD announced last week that its engineers had successfully executed the first physical verification of its largest 7nm chip design – in just ten hours. The AMD Radeon Instinct Vega20 – which boasts 13.2 billion transistors – was tested using a TSMC-certified Calibre nmDRC software platform from Mentor. Read more…

By Oliver Peckham

TSMC and Samsung Moving to 5nm; Whither Moore’s Law?

June 12, 2019

With reports that Taiwan Semiconductor Manufacturing Co. (TMSC) and Samsung are moving quickly to 5nm manufacturing, it’s a good time to again ponder whither goes the venerable Moore’s law. Shrinking feature size has of course been the primary hallmark of achieving Moore’s law... Read more…

By John Russell

Cray Wins NNSA-Livermore ‘El Capitan’ Exascale Contract

August 13, 2019

Cray has won the bid to build the first exascale supercomputer for the National Nuclear Security Administration (NNSA) and Lawrence Livermore National Laborator Read more…

By Tiffany Trader

Deep Learning Competitors Stalk Nvidia

May 14, 2019

There is no shortage of processing architectures emerging to accelerate deep learning workloads, with two more options emerging this week to challenge GPU leader Nvidia. First, Intel researchers claimed a new deep learning record for image classification on the ResNet-50 convolutional neural network. Separately, Israeli AI chip startup Hailo.ai... Read more…

By George Leopold

Leading Solution Providers

ISC 2019 Virtual Booth Video Tour

CRAY
CRAY
DDN
DDN
DELL EMC
DELL EMC
GOOGLE
GOOGLE
ONE STOP SYSTEMS
ONE STOP SYSTEMS
PANASAS
PANASAS
VERNE GLOBAL
VERNE GLOBAL

Nvidia Embraces Arm, Declares Intent to Accelerate All CPU Architectures

June 17, 2019

As the Top500 list was being announced at ISC in Frankfurt today with an upgraded petascale Arm supercomputer in the top third of the list, Nvidia announced its Read more…

By Tiffany Trader

Top500 Purely Petaflops; US Maintains Performance Lead

June 17, 2019

With the kick-off of the International Supercomputing Conference (ISC) in Frankfurt this morning, the 53rd Top500 list made its debut, and this one's for petafl Read more…

By Tiffany Trader

AMD Launches Epyc Rome, First 7nm CPU

August 8, 2019

From a gala event at the Palace of Fine Arts in San Francisco yesterday (Aug. 7), AMD launched its second-generation Epyc Rome x86 chips, based on its 7nm proce Read more…

By Tiffany Trader

A Behind-the-Scenes Look at the Hardware That Powered the Black Hole Image

June 24, 2019

Two months ago, the first-ever image of a black hole took the internet by storm. A team of scientists took years to produce and verify the striking image – an Read more…

By Oliver Peckham

Cray – and the Cray Brand – to Be Positioned at Tip of HPE’s HPC Spear

May 22, 2019

More so than with most acquisitions of this kind, HPE’s purchase of Cray for $1.3 billion, announced last week, seems to have elements of that overused, often Read more…

By Doug Black and Tiffany Trader

Chinese Company Sugon Placed on US ‘Entity List’ After Strong Showing at International Supercomputing Conference

June 26, 2019

After more than a decade of advancing its supercomputing prowess, operating the world’s most powerful supercomputer from June 2013 to June 2018, China is keep Read more…

By Tiffany Trader

Qualcomm Invests in RISC-V Startup SiFive

June 7, 2019

Investors are zeroing in on the open standard RISC-V instruction set architecture and the processor intellectual property being developed by a batch of high-flying chip startups. Last fall, Esperanto Technologies announced a $58 million funding round. Read more…

By George Leopold

Intel 7nm GPU on Roadmap for 2021, OneAPI Coming This Year

May 8, 2019

At Intel's investor meeting today in Santa Clara, Calif., the company filled in details of its roadmap and product launch plans and sought to allay concerns about delays of its 10nm chips. In laying out its 10nm and 7nm timelines, Intel revealed that its first 7nm product would be... Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This