Intel Sets High Water Mark of One Teraflop with ‘Knights Corner’

By Michael Feldman

November 16, 2011

At SC11 in Seattle, Intel showed off an early silicon version of Intel’s Many Integrated Core (MIC) “Knight Corner,” the codename for its first commercial product based on their MIC architecture. The demonstration was performed for the benefit of reporters and analysts, who got to see the new chip in action at a press briefing here on Tuesday afternoon. The jury-rigged test setup had the chip running DGEMM (the double precision floating point version of the general matrix multiply algorithm) at a rather amazing one teraflop/second.

Rajeeb Hazra, GM of Intel’s Technical Computing, Datacenter and Connected Systems Group, waved one of the pre-production chip in front of audience, saying that they had produced “a few tens of chips” for early testing. According to Hazra, they were manufactured at one of their fabs using their 22nm process technology.

He was less forthcoming about other details on the chip however, dodging questions about core counts (once again reiterating that it will be more than 50), processor clock speed, and power consumption. On that last point, it’s likely that TDP is likely to be in the GPU-like 200 to 275 watt range, inasmuch as the coprocessors are destined for servers and workstations, which only have so much leeway with regard to power envelopes.

I did manage to find out the Knight Corner does indeed support ECC memory, although it wasn’t turned on for the DGEMM demo. According to the attending engineer, it doesn’t effect the flops on that code, but will lower performance somewhat on more general applications.

As Hazra pointed out in the briefing, this is the first general-purpose chip in history that is able to hit the one teraflop mark. And while that is true, it should be noted that NVIDIA’s “Kepler” GPU, which is likely to be in production prior to Knights Corner, will probably deliver somewhere between 1.2 to 1.4 double precision teraflops, or about twice that of the current Fermi-class Tesla GPUs.

Nonetheless, the early edition Knight Corner is a remarkable achievement by Intel, and something of a watershed moment for x86 chip making. In 1997, ASCI Red, an Pentium II Xeon-based supercomputer, needed 9,298 processor to hit this same one teraflop mark. And that machine, which was spread out over 72 cabinets, sucked up 800 KW of power.

The production Knights Corner chips delivered in a year or so may actually end up delivering something north of one teraflop, so it’s not a given that NVIDIA will win the flops battle in 2012. In any case, Intel is probably not overly concerned about absolute performance. It’s made a good case that the programming model for MIC will be the real differentiator here.

For some time Intel has been touting that its own x86 parallel compiler and development tools will offer complete support for MIC coprocessors, making the application porting effort much more productive than CUDA. When the code in question incorporates MIC-friendly parallel frameworks like OpenMP, initial porting may amount to no more than a recompile and a re-link. If that pans out as advertised, the ease-of-programming feature will ultimately be the deciding factor in MIC’s favor.

During the press briefing, R. Glenn Brook, a computational scientist at the National Institute for Computational Sciences, University of Tennessee, reported that his team had ported tens of million of lines of legacy science codes to MIC (on prototype “Knights Ferry” coprocessor-powered clusters) in under three months. According to Brook, some of these applications will probably never be ported to GPUs because the complexity of these codes would make the endeavor too onerous.

Clearly, Intel sees their manycore architecture as a path to exascale. In this realm power efficiency is the whole ball game, and MIC is inherently superior to more traditional x86 CPUs in this regard. If we assume Knights Corner is a 250 watt part, it will be able to deliver 4 gigaflops/watt today. That still a far cry from the 50 gigaflops/watt target for an exaflop system (which also has to include memory, interconnects, power supplies, etc.), but the performance/watt trajectory is much more in line with exascale efficiency compared Intel’s mainstream Xeon line.

Speaking of which, Hazra offered up some interesting performance stats on their new Xeon E5 (Sandy Bridge EP) processors. According to Intel testing, the Xeon E5-2680 chip delivers 172 gigaflops of peak performance. And while that bests any of the AMD Opteron 6200 series processors, it’s still well under 2 gigaflops/watt (hard to tell exactly since Intel hasn’t provided TDPs on these pre-launched parts). From that perspective, a traditional Xeon, at least without an on-chip MIC coprocessor, has a rather uncertain future in the exascale era.

But at least for the early petascale era, the Xeon processor is doing just fine. The previous generation Xeon 5600 line is in 223 of the top 500 supercomputers in the world. And the aforementioned Xeon E5 is already in 10 systems, despite the fact that the product won’t be officially launched until the first half of 2012 (which, to my mind, makes the term launch kind of meaningless).

In addition, the E5 will also be making an appearance in future top 10 systems, like GENCI’s 2-petaflop “Curie” super. It is also the CPU of choice for TACC’s 10-petaflop “Stampede” supercomputer, which is scheduled for deployment in early 2013. In this case though, the E5 will be eclipsed by the Knights Corner coprocessors, which will provide 8 of those 10 petaflops. If that trend holds, then MIC will indeed be Intel’s dominant supercomputing architecture for the second half the decade.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

DARPA Continues Investment in Post-Moore’s Technologies

July 24, 2017

The U.S. military long ago ceded dominance in electronics innovation to Silicon Valley, the DoD-backed powerhouse that has driven microelectronic generation for decades. With Moore's Law clearly running out of steam, the Read more…

By George Leopold

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in 2017 with scale-up production for enterprise datacenters and Read more…

By Tiffany Trader

Trinity Supercomputer’s Haswell and KNL Partitions Are Merged

July 19, 2017

Trinity supercomputer’s two partitions – one based on Intel Xeon Haswell processors and the other on Xeon Phi Knights Landing – have been fully integrated are now available for use on classified work in the Nationa Read more…

By HPCwire Staff

Fujitsu Continues HPC, AI Push

July 19, 2017

Summer is well under way, but the so-called summertime slowdown, linked with hot temperatures and longer vacations, does not seem to have impacted Fujitsu's output. The Japanese multinational has made a raft of HPC and A Read more…

By Tiffany Trader

HPE Extreme Performance Solutions

HPE Servers Deliver High Performance Remote Visualization

Whether generating seismic simulations, locating new productive oil reservoirs, or constructing complex models of the earth’s subsurface, energy, oil, and gas (EO&G) is a highly data-driven industry. Read more…

Researchers Use DNA to Store and Retrieve Digital Movie

July 18, 2017

From abacus to pencil and paper to semiconductor chips, the technology of computing has always been an ever-changing target. The human brain is probably the computer we use most (hopefully) and understand least. This mon Read more…

By John Russell

The Exascale FY18 Budget – The Next Step

July 17, 2017

On July 12, 2017, the U.S. federal budget for its Exascale Computing Initiative (ECI) took its next step forward. On that day, the full Appropriations Committee of the House of Representatives voted to accept the recomme Read more…

By Alex R. Larzelere

Summer Reading: IEEE Spectrum’s Chip Hall of Fame

July 17, 2017

Take a trip down memory lane – the Mostek MK4096 4-kilobit DRAM, for instance. Perhaps processors are more to your liking. Remember the Sh-Boom processor (1988), created by Russell Fish and Chuck Moore, and named after Read more…

By John Russell

Women in HPC Luncheon Shines Light on Female-Friendly Hiring Practices

July 13, 2017

The second annual Women in HPC luncheon was held on June 20, 2017, during the International Supercomputing Conference in Frankfurt, Germany. The luncheon provides participants the opportunity to network with industry lea Read more…

By Tiffany Trader

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in Read more…

By Tiffany Trader

Fujitsu Continues HPC, AI Push

July 19, 2017

Summer is well under way, but the so-called summertime slowdown, linked with hot temperatures and longer vacations, does not seem to have impacted Fujitsu's out Read more…

By Tiffany Trader

Researchers Use DNA to Store and Retrieve Digital Movie

July 18, 2017

From abacus to pencil and paper to semiconductor chips, the technology of computing has always been an ever-changing target. The human brain is probably the com Read more…

By John Russell

The Exascale FY18 Budget – The Next Step

July 17, 2017

On July 12, 2017, the U.S. federal budget for its Exascale Computing Initiative (ECI) took its next step forward. On that day, the full Appropriations Committee Read more…

By Alex R. Larzelere

Women in HPC Luncheon Shines Light on Female-Friendly Hiring Practices

July 13, 2017

The second annual Women in HPC luncheon was held on June 20, 2017, during the International Supercomputing Conference in Frankfurt, Germany. The luncheon provid Read more…

By Tiffany Trader

Satellite Advances, NSF Computation Power Rapid Mapping of Earth’s Surface

July 13, 2017

New satellite technologies have completely changed the game in mapping and geographical data gathering, reducing costs and placing a new emphasis on time series Read more…

By Ken Chiacchia and Tiffany Jolley

Intel Skylake: Xeon Goes from Chip to Platform

July 13, 2017

With yesterday’s New York unveiling of the new “Skylake” Xeon Scalable processors, Intel made multiple runs at multiple competitive threats and strategic Read more…

By Doug Black

Perverse Incentives? How Economics (Mis-)shaped Academic Science

July 12, 2017

The unintended consequences of how we fund academic research—in the U.S. and elsewhere—are strangling innovation, putting universities into debt and creatin Read more…

By Ken Chiacchia, Senior Science Writer, Pittsburgh Supercomputing Center

Google Pulls Back the Covers on Its First Machine Learning Chip

April 6, 2017

This week Google released a report detailing the design and performance characteristics of the Tensor Processing Unit (TPU), its custom ASIC for the inference Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Quantum Bits: D-Wave and VW; Google Quantum Lab; IBM Expands Access

March 21, 2017

For a technology that’s usually characterized as far off and in a distant galaxy, quantum computing has been steadily picking up steam. Just how close real-wo Read more…

By John Russell

HPC Compiler Company PathScale Seeks Life Raft

March 23, 2017

HPCwire has learned that HPC compiler company PathScale has fallen on difficult times and is asking the community for help or actively seeking a buyer for its a Read more…

By Tiffany Trader

Trump Budget Targets NIH, DOE, and EPA; No Mention of NSF

March 16, 2017

President Trump’s proposed U.S. fiscal 2018 budget issued today sharply cuts science spending while bolstering military spending as he promised during the cam Read more…

By John Russell

CPU-based Visualization Positions for Exascale Supercomputing

March 16, 2017

In this contributed perspective piece, Intel’s Jim Jeffers makes the case that CPU-based visualization is now widely adopted and as such is no longer a contrarian view, but is rather an exascale requirement. Read more…

By Jim Jeffers, Principal Engineer and Engineering Leader, Intel

Nvidia’s Mammoth Volta GPU Aims High for AI, HPC

May 10, 2017

At Nvidia's GPU Technology Conference (GTC17) in San Jose, Calif., this morning, CEO Jensen Huang announced the company's much-anticipated Volta architecture a Read more…

By Tiffany Trader

Facebook Open Sources Caffe2; Nvidia, Intel Rush to Optimize

April 18, 2017

From its F8 developer conference in San Jose, Calif., today, Facebook announced Caffe2, a new open-source, cross-platform framework for deep learning. Caffe2 is the successor to Caffe, the deep learning framework developed by Berkeley AI Research and community contributors. Read more…

By Tiffany Trader

Leading Solution Providers

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

Russian Researchers Claim First Quantum-Safe Blockchain

May 25, 2017

The Russian Quantum Center today announced it has overcome the threat of quantum cryptography by creating the first quantum-safe blockchain, securing cryptocurrencies like Bitcoin, along with classified government communications and other sensitive digital transfers. Read more…

By Doug Black

MIT Mathematician Spins Up 220,000-Core Google Compute Cluster

April 21, 2017

On Thursday, Google announced that MIT math professor and computational number theorist Andrew V. Sutherland had set a record for the largest Google Compute Engine (GCE) job. Sutherland ran the massive mathematics workload on 220,000 GCE cores using preemptible virtual machine instances. Read more…

By Tiffany Trader

Google Debuts TPU v2 and will Add to Google Cloud

May 25, 2017

Not long after stirring attention in the deep learning/AI community by revealing the details of its Tensor Processing Unit (TPU), Google last week announced the Read more…

By John Russell

Groq This: New AI Chips to Give GPUs a Run for Deep Learning Money

April 24, 2017

CPUs and GPUs, move over. Thanks to recent revelations surrounding Google’s new Tensor Processing Unit (TPU), the computing world appears to be on the cusp of Read more…

By Alex Woodie

Six Exascale PathForward Vendors Selected; DoE Providing $258M

June 15, 2017

The much-anticipated PathForward awards for hardware R&D in support of the Exascale Computing Project were announced today with six vendors selected – AMD Read more…

By John Russell

Top500 Results: Latest List Trends and What’s in Store

June 19, 2017

Greetings from Frankfurt and the 2017 International Supercomputing Conference where the latest Top500 list has just been revealed. Although there were no major Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This