Intel Sets High Water Mark of One Teraflop with ‘Knights Corner’

By Michael Feldman

November 16, 2011

At SC11 in Seattle, Intel showed off an early silicon version of Intel’s Many Integrated Core (MIC) “Knight Corner,” the codename for its first commercial product based on their MIC architecture. The demonstration was performed for the benefit of reporters and analysts, who got to see the new chip in action at a press briefing here on Tuesday afternoon. The jury-rigged test setup had the chip running DGEMM (the double precision floating point version of the general matrix multiply algorithm) at a rather amazing one teraflop/second.

Rajeeb Hazra, GM of Intel’s Technical Computing, Datacenter and Connected Systems Group, waved one of the pre-production chip in front of audience, saying that they had produced “a few tens of chips” for early testing. According to Hazra, they were manufactured at one of their fabs using their 22nm process technology.

He was less forthcoming about other details on the chip however, dodging questions about core counts (once again reiterating that it will be more than 50), processor clock speed, and power consumption. On that last point, it’s likely that TDP is likely to be in the GPU-like 200 to 275 watt range, inasmuch as the coprocessors are destined for servers and workstations, which only have so much leeway with regard to power envelopes.

I did manage to find out the Knight Corner does indeed support ECC memory, although it wasn’t turned on for the DGEMM demo. According to the attending engineer, it doesn’t effect the flops on that code, but will lower performance somewhat on more general applications.

As Hazra pointed out in the briefing, this is the first general-purpose chip in history that is able to hit the one teraflop mark. And while that is true, it should be noted that NVIDIA’s “Kepler” GPU, which is likely to be in production prior to Knights Corner, will probably deliver somewhere between 1.2 to 1.4 double precision teraflops, or about twice that of the current Fermi-class Tesla GPUs.

Nonetheless, the early edition Knight Corner is a remarkable achievement by Intel, and something of a watershed moment for x86 chip making. In 1997, ASCI Red, an Pentium II Xeon-based supercomputer, needed 9,298 processor to hit this same one teraflop mark. And that machine, which was spread out over 72 cabinets, sucked up 800 KW of power.

The production Knights Corner chips delivered in a year or so may actually end up delivering something north of one teraflop, so it’s not a given that NVIDIA will win the flops battle in 2012. In any case, Intel is probably not overly concerned about absolute performance. It’s made a good case that the programming model for MIC will be the real differentiator here.

For some time Intel has been touting that its own x86 parallel compiler and development tools will offer complete support for MIC coprocessors, making the application porting effort much more productive than CUDA. When the code in question incorporates MIC-friendly parallel frameworks like OpenMP, initial porting may amount to no more than a recompile and a re-link. If that pans out as advertised, the ease-of-programming feature will ultimately be the deciding factor in MIC’s favor.

During the press briefing, R. Glenn Brook, a computational scientist at the National Institute for Computational Sciences, University of Tennessee, reported that his team had ported tens of million of lines of legacy science codes to MIC (on prototype “Knights Ferry” coprocessor-powered clusters) in under three months. According to Brook, some of these applications will probably never be ported to GPUs because the complexity of these codes would make the endeavor too onerous.

Clearly, Intel sees their manycore architecture as a path to exascale. In this realm power efficiency is the whole ball game, and MIC is inherently superior to more traditional x86 CPUs in this regard. If we assume Knights Corner is a 250 watt part, it will be able to deliver 4 gigaflops/watt today. That still a far cry from the 50 gigaflops/watt target for an exaflop system (which also has to include memory, interconnects, power supplies, etc.), but the performance/watt trajectory is much more in line with exascale efficiency compared Intel’s mainstream Xeon line.

Speaking of which, Hazra offered up some interesting performance stats on their new Xeon E5 (Sandy Bridge EP) processors. According to Intel testing, the Xeon E5-2680 chip delivers 172 gigaflops of peak performance. And while that bests any of the AMD Opteron 6200 series processors, it’s still well under 2 gigaflops/watt (hard to tell exactly since Intel hasn’t provided TDPs on these pre-launched parts). From that perspective, a traditional Xeon, at least without an on-chip MIC coprocessor, has a rather uncertain future in the exascale era.

But at least for the early petascale era, the Xeon processor is doing just fine. The previous generation Xeon 5600 line is in 223 of the top 500 supercomputers in the world. And the aforementioned Xeon E5 is already in 10 systems, despite the fact that the product won’t be officially launched until the first half of 2012 (which, to my mind, makes the term launch kind of meaningless).

In addition, the E5 will also be making an appearance in future top 10 systems, like GENCI’s 2-petaflop “Curie” super. It is also the CPU of choice for TACC’s 10-petaflop “Stampede” supercomputer, which is scheduled for deployment in early 2013. In this case though, the E5 will be eclipsed by the Knights Corner coprocessors, which will provide 8 of those 10 petaflops. If that trend holds, then MIC will indeed be Intel’s dominant supercomputing architecture for the second half the decade.

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