Thanks to Moore’s Law and advances in silicon photonic fabrication, over the past 10 years more and more photonic components are being integrated onto chips. Such integration will present an opportunity for hardware engineers to reconsider basic computer designs.
That topic is the theme of a Disruptive Technology session at SC11 on Thursday, conducted by Keren Bergman of Columbia University and Nadya Bliss of MIT Lincoln Laboratory. In conjunction with photonic research at their respective organizations, Bergen and Bliss are working on the DARPA POEM Program (Photonically Optimized Embedded Microprocessor) led by Dr. Jagdeep Shah.
MIT Lincoln Laboratory’s role in the effort is to consider potential impact of silicon photonics on both applications and architectures. They are considering this problem both top down (i.e., what are the key application drivers that would benefit from or need performance advantage that photonic interconnects could provide) and bottom up (i.e., what possible architectural changes can be motivated by availability of photonic interconnects both on-chip and to memory).
At Columbia they have been developing an extensive suite of design tools for creating optically interconnected networks-on-chip that are physical layer accurate. This is the basis for their architectural design exploration and validation that the photonic technologies will function as intended.
Prior to their SC11 session, HPCwire asked Bergen and Bliss to discuss the technology issues surrounding integrated photonics and how it could impact computer systems, including HPC machines.
HPCwire: Where are photonic technologies deployed today and what are the main impacts it has had on computing to date?
Keren Bergman: Optical interconnects have historically been used in the longer distance connectivity of HPC systems to storage area networks. With increased bandwidth requirements optical links have been used for inter-rack cluster communications significantly reducing cabling congestion.
Current HPC systems with vastly increased parallelism have accelerated the need for communications bandwidth and driven optical interconnects further into backplane, even placing photonic technologies within the router package in the most advanced systems. Active cables have come into widespread use between racks. At modern 5 to 10 gigabits per second data rates, electrical cables don’t have adequate reach for this application in an HPC, and are far too bulky.
HPCwire: What is the current status of on-chip silicon photonics technology? What are some of the different approaches being explored?
Bergman: There has been significant progress in creating the key silicon photonics device components, however large scale monolithic integration with electrical circuitry in CMOS compatible processes remains a major challenge. Several schemes are currently under development for the integration of silicon photonic components with microelectronic components — both the transmitter and receiver circuits, and the microprocessor or memory components that will utilize the optical links.
The major approaches explored include front-end of CMOS line (FEOL) integration for building modulator and photodetector photonic circuitry and low-temperature processing where optical devices can be monolithically integrated with the metallization levels of the chip as a back-end of line (BEOL) fabrication step. The first use of silicon photonics utilizing some of these approaches appears to be in a module-based technology for the active optical cable market.
VCSEL-based optical modules are perhaps the most widely used technology today. Recent efforts have focused on approaches of directly integrating VCSELs onto the chip package.
HPCwire: How much better is on-chip silicon photonics compared to today’s copper interconnects?
Bergman: On-chip silicon photonic is a potentially disruptive communications platform for building high performance computing systems. Immense bandwidth densities are enabled by the low-loss single mode silicon photonic interconnect which can propagate numerous high bitrate — 40 to 100 gigabit per second — signals in dense WDM, corresponding to terabits per second in a single waveguide.
Furthermore, unlike electronic routing circuitry which requires individual switching elements for each data channel, a single broadband photonic switching element can route multiple high-bandwidth optical channels for the equivalent power of switching a single channel. The optical interconnect can therefore enable extremely high-bandwidth, low-latency end-to-end data transmission from on-chip to off-chip and potentially across the system without the need for power consuming repeaters, buffers, and regenerators.
Combining the power advantage with the bandwidth advantage could yield approximately an order of magnitude communication performance improvement over today’s interconnects — say 10 to 20x better.
HPCwire: How do you see on-chip silicon photonics changing processor, memory, and motherboard designs?
Nadya Bliss: This is exactly the right question to ask. While alone the bandwidth and energy efficiency improvements are significant, the true power of integrated silicon photonics can be demonstrated by considering new architectures and instruction sets. The physical and performance characteristics of silicon photonics enable consideration of new network architectures, new memory hierarchies such as flatter, fewer levels of cache, and pushing parallelism into the hardware.
All of the current computer architecture trends point to multicore systems, with increasing number of cores on chip. Photonic interconnects have the potential to both balance the compute capability of emerging multicore and simplify the programming model by enabling balanced communication.
Realizing these potential benefits in future commercial systems will require significant advancements in high density, low cost optical packaging technology that can meet the reliability challenges.
HPCwire: What will be the impact on system software: the operating system, compilers, communication libraries, etc.?
Bliss: While any new technology has the potential to require new compilers, libraries, etc, the current multicore platforms and the on-chip and to-memory communication challenges are requiring a re-evaluation of programming models. New programming models are emerging that improve programmability, reducing the burden on the programmer, while also allowing the users to increase parallel efficiency of computation. Better communication/computation balance and pushing parallelism closer to the hardware has the potential of simplifying programming models and therefore associated compilers and libraries.
HPCwire: Will applications have to change to take advantage of on-chip photonics?
Bliss: I don’t think applications have to change per se, but new capabilities can be enabled, for example: more complex algorithms can be implemented in smaller form factors.
HPCwire: When do you think we can expect to see on-chip photonics makes its way into commercial silicon?
Bliss: Given the existing research efforts and pending successful demonstrations of both technologies and application capabilities, it is possible to imagine that this would happen over the next 5 to 10 years. To be honest, if it doesn’t, the programmability and performance challenges will continue to get worse and we will see decreased performance scaling in the near future.