Integrated Photonics Coming of Age

By Nicole Hemsoth

November 17, 2011

Thanks to Moore’s Law and advances in silicon photonic fabrication, over the past 10 years more and more photonic components are being integrated onto chips. Such integration will present an opportunity for hardware engineers to reconsider basic computer designs.

That topic is the theme of a Disruptive Technology session at SC11 on Thursday, conducted by Keren Bergman of Columbia University and Nadya Bliss of MIT Lincoln Laboratory. In conjunction with photonic research at their respective organizations, Bergen and Bliss are working on the DARPA POEM Program (Photonically Optimized Embedded Microprocessor) led by Dr. Jagdeep Shah.

MIT Lincoln Laboratory’s role in the effort is to consider potential impact of silicon photonics on both applications and architectures. They are considering this problem both top down (i.e., what are the key application drivers that would benefit from or need performance advantage that photonic interconnects could provide) and bottom up (i.e., what possible architectural changes can be motivated by availability of photonic interconnects both on-chip and to memory).

At Columbia they have been developing an extensive suite of design tools for creating optically interconnected networks-on-chip that are physical layer accurate. This is the basis for their architectural design exploration and validation that the photonic technologies will function as intended.

Prior to their SC11 session, HPCwire asked Bergen and Bliss to discuss the technology issues surrounding integrated photonics and how it could impact computer systems, including HPC machines.

HPCwire: Where are photonic technologies deployed today and what are the main impacts it has had on computing to date?

Keren Bergman: Optical interconnects have historically been used in the longer distance connectivity of HPC systems to storage area networks. With increased bandwidth requirements optical links have been used for inter-rack cluster communications significantly reducing cabling congestion.

Current HPC systems with vastly increased parallelism have accelerated the need for communications bandwidth and driven optical interconnects further into backplane, even placing photonic technologies within the router package in the most advanced systems. Active cables have come into widespread use between racks. At modern 5 to 10 gigabits per second data rates, electrical cables don’t have adequate reach for this application in an HPC, and are far too bulky.

HPCwire: What is the current status of on-chip silicon photonics technology? What are some of the different approaches being explored?

Bergman: There has been significant progress in creating the key silicon photonics device components, however large scale monolithic integration with electrical circuitry in CMOS compatible processes remains a major challenge. Several schemes are currently under development for the integration of silicon photonic components with microelectronic components — both the transmitter and receiver circuits, and the microprocessor or memory components that will utilize the optical links.

The major approaches explored include front-end of CMOS line (FEOL) integration for building modulator and photodetector photonic circuitry and low-temperature processing where optical devices can be monolithically integrated with the metallization levels of the chip as a back-end of line (BEOL) fabrication step. The first use of silicon photonics utilizing some of these approaches appears to be in a module-based technology for the active optical cable market.

VCSEL-based optical modules are perhaps the most widely used technology today. Recent efforts have focused on approaches of directly integrating VCSELs onto the chip package.

HPCwire: How much better is on-chip silicon photonics compared to today’s copper interconnects?

Bergman: On-chip silicon photonic is a potentially disruptive communications platform for building high performance computing systems. Immense bandwidth densities are enabled by the low-loss single mode silicon photonic interconnect which can propagate numerous high bitrate — 40 to 100 gigabit per second — signals in dense WDM, corresponding to terabits per second in a single waveguide.

Furthermore, unlike electronic routing circuitry which requires individual switching elements for each data channel, a single broadband photonic switching element can route multiple high-bandwidth optical channels for the equivalent power of switching a single channel. The optical interconnect can therefore enable extremely high-bandwidth, low-latency end-to-end data transmission from on-chip to off-chip and potentially across the system without the need for power consuming repeaters, buffers, and regenerators.

Combining the power advantage with the bandwidth advantage could yield approximately an order of magnitude communication performance improvement over today’s interconnects — say 10 to 20x better.

HPCwire: How do you see on-chip silicon photonics changing processor, memory, and motherboard designs?

Nadya Bliss: This is exactly the right question to ask. While alone the bandwidth and energy efficiency improvements are significant, the true power of integrated silicon photonics can be demonstrated by considering new architectures and instruction sets. The physical and performance characteristics of silicon photonics enable consideration of new network architectures, new memory hierarchies such as flatter, fewer levels of cache, and pushing parallelism into the hardware.

All of the current computer architecture trends point to multicore systems, with increasing number of cores on chip. Photonic interconnects have the potential to both balance the compute capability of emerging multicore and simplify the programming model by enabling balanced communication.

Realizing these potential benefits in future commercial systems will require significant advancements in high density, low cost optical packaging technology that can meet the reliability challenges.

HPCwire: What will be the impact on system software: the operating system, compilers, communication libraries, etc.?

Bliss: While any new technology has the potential to require new compilers, libraries, etc, the current multicore platforms and the on-chip and to-memory communication challenges are requiring a re-evaluation of programming models. New programming models are emerging that improve programmability, reducing the burden on the programmer, while also allowing the users to increase parallel efficiency of computation. Better communication/computation balance and pushing parallelism closer to the hardware has the potential of simplifying programming models and therefore associated compilers and libraries.

HPCwire: Will applications have to change to take advantage of on-chip photonics?

Bliss: I don’t think applications have to change per se, but new capabilities can be enabled, for example: more complex algorithms can be implemented in smaller form factors.

HPCwire: When do you think we can expect to see on-chip photonics makes its way into commercial silicon?

Bliss: Given the existing research efforts and pending successful demonstrations of both technologies and application capabilities, it is possible to imagine that this would happen over the next 5 to 10 years. To be honest, if it doesn’t, the programmability and performance challenges will continue to get worse and we will see decreased performance scaling in the near future.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Pfizer HPC Engineer Aims to Automate Software Stack Testing

January 17, 2019

Seeking to reign in the tediousness of manual software testing, Pfizer HPC Engineer Shahzeb Siddiqui is developing an open source software tool called buildtest, aimed at automating software stack testing by providing the community with a central repository of tests for common HPC apps and the ability to automate execution of testing. Read more…

By Tiffany Trader

Senegal Prepares to Take Delivery of Atos Supercomputer

January 16, 2019

Update (Jan. 21): HPCwire has received confirmation from Atos that the system will have a peak speed of 537.6 teraflops, not 320 teraflops as had previously been reported. We plan to report additional details as we recei Read more…

By Tiffany Trader

Google Cloud Platform Extends GPU Instance Options

January 16, 2019

If it's Nvidia GPUs you're after to power your AI/HPC/visualization workload, Google Cloud has them, now claiming "broadest GPU availability." Each of the three big public cloud vendors has by turn touted the latest and Read more…

By Tiffany Trader

HPE Extreme Performance Solutions

HPE Systems With Intel Omni-Path: Architected for Value and Accessible High-Performance Computing

Today’s high-performance computing (HPC) and artificial intelligence (AI) users value high performing clusters. And the higher the performance that their system can deliver, the better. Read more…

IBM Accelerated Insights

Resource Management in the Age of Artificial Intelligence

New challenges demand fresh approaches

Fueled by GPUs, big data, and rapid advances in software, the AI revolution is upon us. Read more…

STAC Floats ML Benchmark for Financial Services Workloads

January 16, 2019

STAC (Securities Technology Analysis Center) recently released an ‘exploratory’ benchmark for machine learning which it hopes will evolve into a firm benchmark or suite of benchmarking tools to compare the performanc Read more…

By John Russell

Google Cloud Platform Extends GPU Instance Options

January 16, 2019

If it's Nvidia GPUs you're after to power your AI/HPC/visualization workload, Google Cloud has them, now claiming "broadest GPU availability." Each of the three Read more…

By Tiffany Trader

STAC Floats ML Benchmark for Financial Services Workloads

January 16, 2019

STAC (Securities Technology Analysis Center) recently released an ‘exploratory’ benchmark for machine learning which it hopes will evolve into a firm benchm Read more…

By John Russell

A Big Data Journey While Seeking to Catalog our Universe

January 16, 2019

It turns out, astronomers have lots of photos of the sky but seek knowledge about what the photos mean. Sound familiar? Big data problems are often characterize Read more…

By James Reinders

Intel Bets Big on 2-Track Quantum Strategy

January 15, 2019

Quantum computing has lived so long in the future it’s taken on a futuristic life of its own, with a Gartner-style hype cycle that includes triggers of innovation, inflated expectations and – though a useful quantum system is still years away – anticipatory troughs of disillusionment. Read more…

By Doug Black

IBM Quantum Update: Q System One Launch, New Collaborators, and QC Center Plans

January 10, 2019

IBM made three significant quantum computing announcements at CES this week. One was introduction of IBM Q System One; it’s really the integration of IBM’s Read more…

By John Russell

IBM’s New Global Weather Forecasting System Runs on GPUs

January 9, 2019

Anyone who has checked a forecast to decide whether or not to pack an umbrella knows that weather prediction can be a mercurial endeavor. It is a Herculean task: the constant modeling of incredibly complex systems to a high degree of accuracy at a local level within very short spans of time. Read more…

By Oliver Peckham

The Case Against ‘The Case Against Quantum Computing’

January 9, 2019

It’s not easy to be a physicist. Richard Feynman (basically the Jimi Hendrix of physicists) once said: “The first principle is that you must not fool yourse Read more…

By Ben Criger

The Deep500 – Researchers Tackle an HPC Benchmark for Deep Learning

January 7, 2019

How do you know if an HPC system, particularly a larger-scale system, is well-suited for deep learning workloads? Today, that’s not an easy question to answer Read more…

By John Russell

Quantum Computing Will Never Work

November 27, 2018

Amid the gush of money and enthusiastic predictions being thrown at quantum computing comes a proposed cold shower in the form of an essay by physicist Mikhail Read more…

By John Russell

Cray Unveils Shasta, Lands NERSC-9 Contract

October 30, 2018

Cray revealed today the details of its next-gen supercomputing architecture, Shasta, selected to be the next flagship system at NERSC. We've known of the code-name "Shasta" since the Argonne slice of the CORAL project was announced in 2015 and although the details of that plan have changed considerably, Cray didn't slow down its timeline for Shasta. Read more…

By Tiffany Trader

AMD Sets Up for Epyc Epoch

November 16, 2018

It’s been a good two weeks, AMD’s Gary Silcott and Andy Parma told me on the last day of SC18 in Dallas at the restaurant where we met to discuss their show news and recent successes. Heck, it’s been a good year. Read more…

By Tiffany Trader

The Case Against ‘The Case Against Quantum Computing’

January 9, 2019

It’s not easy to be a physicist. Richard Feynman (basically the Jimi Hendrix of physicists) once said: “The first principle is that you must not fool yourse Read more…

By Ben Criger

US Leads Supercomputing with #1, #2 Systems & Petascale Arm

November 12, 2018

The 31st Supercomputing Conference (SC) - commemorating 30 years since the first Supercomputing in 1988 - kicked off in Dallas yesterday, taking over the Kay Ba Read more…

By Tiffany Trader

Contract Signed for New Finnish Supercomputer

December 13, 2018

After the official contract signing yesterday, configuration details were made public for the new BullSequana system that the Finnish IT Center for Science (CSC Read more…

By Tiffany Trader

Nvidia’s Jensen Huang Delivers Vision for the New HPC

November 14, 2018

For nearly two hours on Monday at SC18, Jensen Huang, CEO of Nvidia, presented his expansive view of the future of HPC (and computing in general) as only he can do. Animated. Backstopped by a stream of data charts, product photos, and even a beautiful image of supernovae... Read more…

By John Russell

HPE No. 1, IBM Surges, in ‘Bucking Bronco’ High Performance Server Market

September 27, 2018

Riding healthy U.S. and global economies, strong demand for AI-capable hardware and other tailwind trends, the high performance computing server market jumped 28 percent in the second quarter 2018 to $3.7 billion, up from $2.9 billion for the same period last year, according to industry analyst firm Hyperion Research. Read more…

By Doug Black

Leading Solution Providers

SC 18 Virtual Booth Video Tour

Advania @ SC18 AMD @ SC18
ASRock Rack @ SC18
DDN Storage @ SC18
HPE @ SC18
IBM @ SC18
Lenovo @ SC18 Mellanox Technologies @ SC18
NVIDIA @ SC18
One Stop Systems @ SC18
Oracle @ SC18 Panasas @ SC18
Supermicro @ SC18 SUSE @ SC18 TYAN @ SC18
Verne Global @ SC18

HPC Reflections and (Mostly Hopeful) Predictions

December 19, 2018

So much ‘spaghetti’ gets tossed on walls by the technology community (vendors and researchers) to see what sticks that it is often difficult to peer through Read more…

By John Russell

Intel Confirms 48-Core Cascade Lake-AP for 2019

November 4, 2018

As part of the run-up to SC18, taking place in Dallas next week (Nov. 11-16), Intel is doling out info on its next-gen Cascade Lake family of Xeon processors, specifically the “Advanced Processor” version (Cascade Lake-AP), architected for high-performance computing, artificial intelligence and infrastructure-as-a-service workloads. Read more…

By Tiffany Trader

Germany Celebrates Launch of Two Fastest Supercomputers

September 26, 2018

The new high-performance computer SuperMUC-NG at the Leibniz Supercomputing Center (LRZ) in Garching is the fastest computer in Germany and one of the fastest i Read more…

By Tiffany Trader

Microsoft to Buy Mellanox?

December 20, 2018

Networking equipment powerhouse Mellanox could be an acquisition target by Microsoft, according to a published report in an Israeli financial publication. Microsoft has reportedly gone so far as to engage Goldman Sachs to handle negotiations with Mellanox. Read more…

By Doug Black

Houston to Field Massive, ‘Geophysically Configured’ Cloud Supercomputer

October 11, 2018

Based on some news stories out today, one might get the impression that the next system to crack number one on the Top500 would be an industrial oil and gas mon Read more…

By Tiffany Trader

The Deep500 – Researchers Tackle an HPC Benchmark for Deep Learning

January 7, 2019

How do you know if an HPC system, particularly a larger-scale system, is well-suited for deep learning workloads? Today, that’s not an easy question to answer Read more…

By John Russell

Summit Supercomputer is Already Making its Mark on Science

September 20, 2018

Summit, now the fastest supercomputer in the world, is quickly making its mark in science – five of the six finalists just announced for the prestigious 2018 Read more…

By John Russell

IBM Quantum Update: Q System One Launch, New Collaborators, and QC Center Plans

January 10, 2019

IBM made three significant quantum computing announcements at CES this week. One was introduction of IBM Q System One; it’s really the integration of IBM’s Read more…

By John Russell

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This