Revisiting Supercomputer Architectures

By Chris Willard

December 8, 2011

The chronology of high performance computing can be divided into “ages” based on the predominant systems architectures for the period. Starting in the late 1970s vector processors dominated HPC. By the end of the next decade massively parallel processors were able to make a play for market leader. For the last half of the 1990s, RISC based SMPs were the leading technology. And finally, clustered x86 based servers captured market priority in the early part of this century. 

This architectural path was dictated by the technical and economic effect of Moore’s Law. Specifically, the doubling of processor clock speed every 18 to 24 months meant that without doing anything, applications also roughly doubled in speed at the same rate. One effect of this “free ride” was to drive companies attempting to create new HPC architectures from the market. Development cycles for new technology simply could not outpace Moore’s Law-driven gains in commodity technology, and product development costs for specialized systems could not compete against products sold to volume markets.

The more general-purpose systems were admittedly not the best architectures for HPC users’ problems. However commodity component based computers were inexpensive, could be racked and stacked, and were continually getting faster. In addition, users could attempt to parallelize their applications across multiple compute nodes to get additional speed ups. In a recent Intersect360 study, users reported a wide range of scalable applications, with some using over 10,000 cores, but with the median number of cores used by a typical HPC application of only 36 cores.

In the mid 2000s, Moore’s Law went through a major course correction. While the number of transistors on a chip continued to double on schedule, the ability to increase clock speed hit a practical barrier — “the power wall.” The exponential increase in power required to increase processor cycle times hit practical cost and design limits. The power wall led to clock speeds stabilizing at roughly 3GHz and multiple processor cores being placed on a single chip with core counts now ranging from 2 to 16. This ended the free ride for HPC users based on ever faster single-core processors and is forcing them to rewrite applications for parallelism.

In addition to the power wall, the scale out strategy of adding capacity by simply racking and stacking more compute server nodes caused some users to hit other walls, specifically the computer room wall (or “wall wall”) where facilities issues became a major problem. These include physical space, structural support for high density configurations, cooling, and getting enough electricity into the building.

The market is currently looking to a combination of four strategies to increase the performance of HPC systems and applications: parallel applications development; adding accelerators to standard commodity compute nodes; developing new purpose-built systems; and waiting for a technology breakthrough.

Parallelism is like the “little girl with the curl,” when parallelism is good it is very, very good, and when it is bad it is horrid. Very good parallel applications (aka embarrassingly parallel) fall into such categories as: signal processing, Monte Carlo analysis, image rendering, and the TOP500 benchmark. The success of these areas can obscure the difficulty in developing parallel applications in other areas. Embarrassingly parallel applications have a few characteristics in common:

  • The problem can be broken up into a large number of sub-problems.
  • These sub-problem are independent of one another, that is they can be solved in any order and without requiring any data transfer to or from other sub-problems,
  • The sub-problems are small enough to be effectively solved on whatever the compute node du jour might be.

When these constraints break down, the programming problem first becomes interesting, then challenging, then maddening, then virtually impossible. The programmer must manage ever more complex data traffic patterns between sub-problems, plus control the order of operations of various tasks, plus attempt to find ways to break larger sub-problems into sub-sub-problems, and so on. If this were easy it would have been done long ago.

Adding accelerators to standard computer architectures is a technique that has been used throughout the history of computer architecture development. Current HPC markets are experimenting with graphics processing units (GPUs) and to a lesser extent field programmable gate arrays (FPGAs).

GPUs have long been a standard component in desktop computers. GPUs are of interest for several reasons: they are inexpensive commodity components, they have fast independent memories, and they provide significant parallel computational power.

FPGAs are standard devices long in use within the electronics industry for quickly developing and fielding specialty chips that are often replaced in products by standard ASICs over time. FPGAs allow HPC users to essentially customize the computer to the requirements of their applications. In addition they should benefit from Moore’s Law advancements over time.

Challenges for accelerator-based systems stem from a single program being run over two different processing devices, one a general-purpose processor with limited speed, and the other an accelerator with high processing speed but with limited overall functionality. Challenges fall into three major areas:

  • Programming — Computers can be built to arbitrarily high levels of complexity, however the average complexity of computer programmers remains a constant. Accelerators add two levels of complexity for applications development, first writing a single program that is divided between two different processor types, and second, writing a program that can take advantage of the specific characteristics of the accelerator.
  • Control and communications — Performance gains from accelerations can be diminished or lost from compute overhead generated from setting up the problem on the accelerator, moving data between the standard processor and the accelerator, and coordinating the operations of both compute units.
  • Data management — Programming complexity is increased and performance is reduced in cases where the standard processor and accelerator use separate independent memories. Issues for managing data across multiple processors range from determining proper data decomposition, to efficiently moving data in and out of the proper memories, to stalling processes while waiting on data from another memory, to debugging programs where it is unclear which processor has last modified a data item.

Many of these issues are associated with parallel computing in general, however they are still significant for accelerator-based operations, and the close coupling between the processor and the accelerator may require programmers to have a deep understanding of the behavior of the physical hardware components.

Purpose-built systems are systems that are designed to meet the requirements of HPC workflows. (These systems were initially called supercomputers.) In today’s market, new HPC architectures still make use of commodity components such as processor chips, memory chips/DIMMS, accelerators, I/O ports, and so on. However they introduce novel technologies in such areas as:

  • Memory subsystems — Arguably the most important part of any HPC computer is the memory system. HPC applications tend to stream a few large data sets from storage through memory, into processors, and back again for a normal workflow. In addition, such requirements as spare matrix calculations lead to requirements for fast access to non-contiguous data elements. The speed at which the data can be moved is the determining factor in the ultimate performance in a large portion, if not the majority, of HPC applications.
  • Parallel system interconnects — Parallel computer essentially address the memory bandwidth problem by creating a logically two dimension memory structure, one dimension is within nodes. i.e., between a nodes local memory and local processors. Total bandwidth in this case is the sum off all node bandwidths and is very high. The second dimension is the node to node interconnect, which is essentially a specialized local area network that is significantly slower in both bandwidth and latency measures than local node memories. As applications become less embarrassingly parallel the communications over the interconnect increases, and the interconnect performance tends to become the limiting factor in overall applications performance.
  • Packaging — The speed of computer components. i.e., processors and memories can be increased by reducing the temperature at which they run. In addition, parallel computing latency issues can be addressed by simply packing nodes closer together, which requires both fitting more wires into a smaller space, and removing high amounts of heat from relatively small volumes.

Developing specialized HPC architectures has, up until recently, been limited by the effects of Moore’s Law, which has shortened product cycle times for standard products, and limited market opportunities for specialized systems. Those HPC architecture efforts that have gone forward have generally received support from government and/or large corporation R&D funds.

Waiting for a technology breakthrough (or the “then a miracle happens” strategy) is always an alternative; it is also the path of least resistance, and one step short of despair. Today we are looking at such technologies as optical computing, quantum entanglement communications, and quantum computers for potential future breakthroughs.

The issue with relying on future technologies is there is no way to tell first, if a technology concept can be turned into viable a product — there is many a slip between the lab and loading dock. Second, even if it can be shown that a concept can be productized, it is virtually impossible to predict when the product will actually reach the market. Even products based on well understood production technologies can badly overrun schedules, sometimes bringing to grief those vendors and users who bet on new products.

The above arguments suggests that the next age of high performance computing could be based on anything from reliance on clusters with speed boosts add-ons, to a brave new computer based on technologies that may not have been heard of yet. (You can never go wrong with a forecast like that.) That said, I am willing to lay odds on purpose-built computers becoming a major component, if not the defining technology of the HPC market within the next five years, for two major reasons.

First, there is no “easy” technical solution. Single thread performance has plateaued; the usefulness of accelerators is dependent on both the parallelism inherent to the application and the connectivity between the accelerator and the rest of the system; and parallelism, while an advantage where it can be found, is not a panacea for computing performance.

Second, the economics of HPC system development have changed. Users cannot simply sit back and wait for a faster CPU, but must make significant investments in either new software, or new architectures, or both. Staying with old economic models will lead to the computation tools defining the science, where work will be restricted to those areas that will run well on off-the-shelf computers.

The HPC market is at a point where the business climate will support greater levels of innovation at the architectural level, which should lead to new organizing principle for HPC systems. The goal here is to find new approaches that will effectively combine and optimize the various standard components into systems that can continue to grow performance across a broad range of applications.

Of course we can always wait for a miracle to happen.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

NSF Project Sets Up First Machine Learning Cyberinfrastructure – CHASE-CI

July 25, 2017

Earlier this month, the National Science Foundation issued a $1 million grant to Larry Smarr, director of Calit2, and a group of his colleagues to create a community infrastructure in support of machine learning research Read more…

By John Russell

DARPA Continues Investment in Post-Moore’s Technologies

July 24, 2017

The U.S. military long ago ceded dominance in electronics innovation to Silicon Valley, the DoD-backed powerhouse that has driven microelectronic generation for decades. With Moore's Law clearly running out of steam, the Read more…

By George Leopold

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in 2017 with scale-up production for enterprise datacenters and Read more…

By Tiffany Trader

HPE Extreme Performance Solutions

HPE Servers Deliver High Performance Remote Visualization

Whether generating seismic simulations, locating new productive oil reservoirs, or constructing complex models of the earth’s subsurface, energy, oil, and gas (EO&G) is a highly data-driven industry. Read more…

Trinity Supercomputer’s Haswell and KNL Partitions Are Merged

July 19, 2017

Trinity supercomputer’s two partitions – one based on Intel Xeon Haswell processors and the other on Xeon Phi Knights Landing – have been fully integrated are now available for use on classified work in the Nationa Read more…

By HPCwire Staff

NSF Project Sets Up First Machine Learning Cyberinfrastructure – CHASE-CI

July 25, 2017

Earlier this month, the National Science Foundation issued a $1 million grant to Larry Smarr, director of Calit2, and a group of his colleagues to create a comm Read more…

By John Russell

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in Read more…

By Tiffany Trader

Fujitsu Continues HPC, AI Push

July 19, 2017

Summer is well under way, but the so-called summertime slowdown, linked with hot temperatures and longer vacations, does not seem to have impacted Fujitsu's out Read more…

By Tiffany Trader

Researchers Use DNA to Store and Retrieve Digital Movie

July 18, 2017

From abacus to pencil and paper to semiconductor chips, the technology of computing has always been an ever-changing target. The human brain is probably the com Read more…

By John Russell

The Exascale FY18 Budget – The Next Step

July 17, 2017

On July 12, 2017, the U.S. federal budget for its Exascale Computing Initiative (ECI) took its next step forward. On that day, the full Appropriations Committee Read more…

By Alex R. Larzelere

Women in HPC Luncheon Shines Light on Female-Friendly Hiring Practices

July 13, 2017

The second annual Women in HPC luncheon was held on June 20, 2017, during the International Supercomputing Conference in Frankfurt, Germany. The luncheon provid Read more…

By Tiffany Trader

Satellite Advances, NSF Computation Power Rapid Mapping of Earth’s Surface

July 13, 2017

New satellite technologies have completely changed the game in mapping and geographical data gathering, reducing costs and placing a new emphasis on time series Read more…

By Ken Chiacchia and Tiffany Jolley

Intel Skylake: Xeon Goes from Chip to Platform

July 13, 2017

With yesterday’s New York unveiling of the new “Skylake” Xeon Scalable processors, Intel made multiple runs at multiple competitive threats and strategic Read more…

By Doug Black

Google Pulls Back the Covers on Its First Machine Learning Chip

April 6, 2017

This week Google released a report detailing the design and performance characteristics of the Tensor Processing Unit (TPU), its custom ASIC for the inference Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Quantum Bits: D-Wave and VW; Google Quantum Lab; IBM Expands Access

March 21, 2017

For a technology that’s usually characterized as far off and in a distant galaxy, quantum computing has been steadily picking up steam. Just how close real-wo Read more…

By John Russell

HPC Compiler Company PathScale Seeks Life Raft

March 23, 2017

HPCwire has learned that HPC compiler company PathScale has fallen on difficult times and is asking the community for help or actively seeking a buyer for its a Read more…

By Tiffany Trader

Trump Budget Targets NIH, DOE, and EPA; No Mention of NSF

March 16, 2017

President Trump’s proposed U.S. fiscal 2018 budget issued today sharply cuts science spending while bolstering military spending as he promised during the cam Read more…

By John Russell

CPU-based Visualization Positions for Exascale Supercomputing

March 16, 2017

In this contributed perspective piece, Intel’s Jim Jeffers makes the case that CPU-based visualization is now widely adopted and as such is no longer a contrarian view, but is rather an exascale requirement. Read more…

By Jim Jeffers, Principal Engineer and Engineering Leader, Intel

Nvidia’s Mammoth Volta GPU Aims High for AI, HPC

May 10, 2017

At Nvidia's GPU Technology Conference (GTC17) in San Jose, Calif., this morning, CEO Jensen Huang announced the company's much-anticipated Volta architecture a Read more…

By Tiffany Trader

Facebook Open Sources Caffe2; Nvidia, Intel Rush to Optimize

April 18, 2017

From its F8 developer conference in San Jose, Calif., today, Facebook announced Caffe2, a new open-source, cross-platform framework for deep learning. Caffe2 is the successor to Caffe, the deep learning framework developed by Berkeley AI Research and community contributors. Read more…

By Tiffany Trader

Leading Solution Providers

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

Russian Researchers Claim First Quantum-Safe Blockchain

May 25, 2017

The Russian Quantum Center today announced it has overcome the threat of quantum cryptography by creating the first quantum-safe blockchain, securing cryptocurrencies like Bitcoin, along with classified government communications and other sensitive digital transfers. Read more…

By Doug Black

MIT Mathematician Spins Up 220,000-Core Google Compute Cluster

April 21, 2017

On Thursday, Google announced that MIT math professor and computational number theorist Andrew V. Sutherland had set a record for the largest Google Compute Engine (GCE) job. Sutherland ran the massive mathematics workload on 220,000 GCE cores using preemptible virtual machine instances. Read more…

By Tiffany Trader

Google Debuts TPU v2 and will Add to Google Cloud

May 25, 2017

Not long after stirring attention in the deep learning/AI community by revealing the details of its Tensor Processing Unit (TPU), Google last week announced the Read more…

By John Russell

Groq This: New AI Chips to Give GPUs a Run for Deep Learning Money

April 24, 2017

CPUs and GPUs, move over. Thanks to recent revelations surrounding Google’s new Tensor Processing Unit (TPU), the computing world appears to be on the cusp of Read more…

By Alex Woodie

Six Exascale PathForward Vendors Selected; DoE Providing $258M

June 15, 2017

The much-anticipated PathForward awards for hardware R&D in support of the Exascale Computing Project were announced today with six vendors selected – AMD Read more…

By John Russell

Top500 Results: Latest List Trends and What’s in Store

June 19, 2017

Greetings from Frankfurt and the 2017 International Supercomputing Conference where the latest Top500 list has just been revealed. Although there were no major Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This