Designer of Microprocessor-Memory Chip Aims to Topple Memory and Power Walls

By Michael Feldman

January 17, 2012

Whether you’re talking about high performance computers, enterprise servers, or mobile devices, the two biggest impediments to application performance in computing today are the memory wall and the power wall. Venray Technology is aiming to knock down those walls with a unique approach that puts CPU cores and DRAM on the same die. The company has been in semi-stealth mode since it inception seven years ago, but is now trying to get the word out about its technology as it searches for a commercial buyer.

Dallas-based Venray is the brainchild of Russell Fish, who made himself the CTO (there is no CEO listed on the website) and the principal architect. Fish is co-designer of the Sh-Boom Processor, and holder of multiple microprocessor patents. These patents turned out to be fundamental to the operation of modern microprocessors and have been licensed by practically every computer and semiconductor manufacturer on the planet. The proceeds from those patents are being used to fund Venray.

Since 2007, Fish and company have been engaged in the design and marketing of a novel CPU-DRAM technology, known as TOMI, which stands for Thread Optimized Multiprocessor. With TOMI, the company aims to do what no other chip maker has done before, namely embed a general-purpose processor in vanilla DRAM. The idea is to use the physical proximity of the CPU and memory, as well as extra-wide busses (4,096 bits, in the case of the first TOMI designs), to flatten the memory wall.

The memory wall is huge problem in high performance computing and big data applications today and will soon limit computing across all segments. The problem was brought home by a 2008 study of multicore performance at Sandia National Labs, in which researchers demonstrated that for certain classes of data-intensive applications, the use of extra cores to increase performance is counter-productive.

For these application profiles, performance basically flattened between four and eight cores, and actually declined beyond that. The problem was that as more cores were added, they were starved for the limited amount of memory bandwidth available, and after a certain point, the overhead of memory contention actually decreased performance. Prospective solutions, such as memory chip stacking (for example, Micron’s Hybrid Memory Cube) are unproven and have yet to find their way into the commercial market.

Some microprocessor-memory integration has been attempted with embedded DRAM (eDRAM), a technology that promises a lot more capacity than can be delivered by on-chip cache memory. It has been used as a foundation for some integrated SoC devices including IBM’s Power7 CPU and Blue Gene ASIC, as well as for many of the processors that power game console devices, such as the Sony PlayStation. Embedded DRAM was also the memory technology of choice for the 2000-era IRAM research effort, which aimed to integrate a 256-bit vector microprocessor with 16MB of memory.

But even though eDRAM is much denser than cache memory, it can’t provide the storage capacity of conventional DRAM. It is also hundreds of times as expensive as regular memory. “The people that have tried to combine CPUs and memory before have usually erred on the side of having the CPUs too big and the memory too small,” says Fish. “They did not understand the difference between embedding DRAM in CPUs and making CPUs in DRAMs.”

The challenge of melding CPUs with DRAM is that microprocessors are much more complex beasts than memories, and as a result, are manufactured with entirely different semiconductor processes. Typically semiconductor logic require ten or more layers of material to be laid down on the die, compared to just three for DRAM. However, if a microprocessor can be designed much more simply, reducing the number and complexity of logic gate connections, it is possible to more or less flatten the layout and use just three layers.

That is the fundamental magic used by TOMI. Its second-generation design, named Borealis, consists of an 8-core RISC CPU built using the three-layer DRAM process. The CPU itself is made up of just 22 thousand transistors (not including cache and the memory controller), embedded in a 1 Gbit DRAM chip. On the 42nm process node, the CPU takes up just 14 percent of the die.

It is possible to use the TOMI technology to implement legacy microprocessor architectures, but big CPUs, in particular, would not be able to squeeze onto their DRAM process technology — at least not at current CMOS geometries. In any case, Fish seem to think the optimal mix of memory to logic is around 5 to 1.

To get to that level, Fish and company pared down its CPU to just the basics: 32-bit integer hardware, and a small set of instructions (forgoing less useful instructions like auto-index and auto-decrement). The lack of floating point hardware, which tend to suck up a lot of silicon real estate, doesn’t rule out for support for those operations; they are just emulated via software libraries.

A very useful side effect of using the simpler DRAM processes is that it’s much cheaper to produce a CPU this way. The cost of manufacturing a billion DRAM transistors is less than a dollar versus more than $300 for a microprocessor. But another big savings is in power draw. The Borealis CPU at 2.1 GHz draws a measly 98 mW. Compare that to the 100-plus watts for an x86 CPU sporting a billion transistors.

Of course, the Borealis microprocessor is much less performant than a billion transistor CPU in raw compute power. It’s specifically built to maximize the throughput of analytics applications chewing on large datasets, aka big data. “We’ve probably built the most efficient big data processor in existence,” claims Fish.

To prove their point, Venray benchmarked their hardware with Sandia Labs’ MapReduce-MPI software and an unstructured data application running on their hardware — a circuit board with 16 Borealis chips (128 cores, 16GB of DRAM). According to the company, the TOMI system was able to achieve nearly 12 times the performance and use less than 1/10 the power compared to the same code running on an Intel Xeon-based cluster. Venray says the hardware would cost about $35 thousand versus $1.65 million for the equivalent x86 system.

Beyond benchmarks, TOMI is built for all sorts of data mining, high-end analytics, and pattern recognition software. To Fish, these are the killer applications that will drive the industry in the future. And since the architecture is naturally energy efficient, TOMI would be equally at home in mobile devices and in cloud servers.

The downside, of course, is that unlike x86 and ARM, the architecture has no vast ecosystem behind it. But according to Fish, by providing a C/C++ compiler via gcc, the whole Linux toolchain can be leveraged. For legacy applications, the bigger problem is the recoding that would have to be done. Most applications assume powerful single-threaded CPUs and small memory footprints, rather than the inverse. None of this deters Fish, who sees the legacy CPU architectures as a dead end, especially for big data applications that is poised to drive a lot of growth in the IT sector.

At this point, Fish and his cohorts are actively in search of a single buyer for TOMI, most likely a computer manufacturer of some sort. According to him, the advantage of the technology is wrapped up in its exclusivity, so licensing the IP would dilute the value to prospective customers. To date, they have received the most attention from buyers outside the US. One overseas group was ready to write “a large check,” but Fish declined, wanting to give US-based companies a shot. According to him, in the past five or six months, prospective buyers in the US have shown increased interest. “Lots of people want to be our friends right now,” he says.

Related articles

IBM Will Chip in on Micron’s 3D Hybrid Memory Cube

Up Against the Memory Wall

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Long Flights to Cluster Fights: Meet the Asian Student Cluster Teams

November 22, 2017

Five teams from Asia traveled thousands of miles to compete at the SC17 Student Cluster Competition in Denver. Our cameras were there to meet ‘em, greet ‘em, and grill ‘em about their clusters and how they’re doi Read more…

By Dan Olds

Japan Unveils Quantum Neural Network

November 22, 2017

The U.S. and China are leading the race toward productive quantum computing, but it's early enough that ultimate leadership is still something of an open question. The latest geo-region to throw its hat in the quantum co Read more…

By Tiffany Trader

Perspective: What Really Happened at SC17?

November 22, 2017

SC is over. Now comes the myriad of follow-ups. Inboxes are filled with templated emails from vendors and other exhibitors hoping to win a place in the post-SC thinking of booth visitors. Attendees of tutorials, workshop Read more…

By Andrew Jones

HPE Extreme Performance Solutions

HPE Wins “Best HPC Server” for the Apollo 6000 Gen10 System

Hewlett Packard Enterprise (HPE) was nominated for 14 HPCwire Readers’ and Editors’ Choice Awards—including “Best High Performance Computing (HPC) Server Product or Technology” and “Top Supercomputing Achievement.” The HPE Apollo 6000 Gen10 was named “Best HPC Server” of 2017. Read more…

Turnaround Complete, HPE’s Whitman Departs

November 22, 2017

Having turned around the aircraft carrier the Silicon Valley icon had become, Meg Whitman is leaving the helm of a restructured Hewlett Packard. Her successor, technologist Antonio Neri will now guide what Whitman assert Read more…

By George Leopold

Long Flights to Cluster Fights: Meet the Asian Student Cluster Teams

November 22, 2017

Five teams from Asia traveled thousands of miles to compete at the SC17 Student Cluster Competition in Denver. Our cameras were there to meet ‘em, greet ‘em Read more…

By Dan Olds

Perspective: What Really Happened at SC17?

November 22, 2017

SC is over. Now comes the myriad of follow-ups. Inboxes are filled with templated emails from vendors and other exhibitors hoping to win a place in the post-SC Read more…

By Andrew Jones

SC Bids Farewell to Denver, Heads to Dallas for 30th Anniversary

November 17, 2017

After a jam-packed four-day expo and intensive six-day technical program, SC17 has wrapped up another successful event that brought together nearly 13,000 visit Read more…

By Tiffany Trader

SC17 Keynote – HPC Powers SKA Efforts to Peer Deep into the Cosmos

November 17, 2017

This week’s SC17 keynote – Life, the Universe and Computing: The Story of the SKA Telescope – was a powerful pitch for the potential of Big Science projects that also showcased the foundational role of high performance computing in modern science. It was also visually stunning. Read more…

By John Russell

How Cities Use HPC at the Edge to Get Smarter

November 17, 2017

Cities are sensoring up, collecting vast troves of data that they’re running through predictive models and using the insights to solve problems that, in some Read more…

By Doug Black

Student Cluster LINPACK Record Shattered! More LINs Packed Than Ever before!

November 16, 2017

Nanyang Technological University, the pride of Singapore, utterly destroyed the Student Cluster Competition LINPACK record by posting a score of 51.77 TFlop/s a Read more…

By Dan Olds

Hyperion Market Update: ‘Decent’ Growth Led by HPE; AI Transparency a Risk Issue

November 15, 2017

The HPC market update from Hyperion Research (formerly IDC) at the annual SC conference is a business and social “must,” and this year’s presentation at S Read more…

By Doug Black

Nvidia Focuses Its Cloud Containers on HPC Applications

November 14, 2017

Having migrated its top-of-the-line datacenter GPU to the largest cloud vendors, Nvidia is touting its Volta architecture for a range of scientific computing ta Read more…

By George Leopold

US Coalesces Plans for First Exascale Supercomputer: Aurora in 2021

September 27, 2017

At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, in Arlington, Va., yesterday (Sept. 26), it was revealed that the "Aurora" supercompute Read more…

By Tiffany Trader

NERSC Scales Scientific Deep Learning to 15 Petaflops

August 28, 2017

A collaborative effort between Intel, NERSC and Stanford has delivered the first 15-petaflops deep learning software running on HPC platforms and is, according Read more…

By Rob Farber

Oracle Layoffs Reportedly Hit SPARC and Solaris Hard

September 7, 2017

Oracle’s latest layoffs have many wondering if this is the end of the line for the SPARC processor and Solaris OS development. As reported by multiple sources Read more…

By John Russell

AMD Showcases Growing Portfolio of EPYC and Radeon-based Systems at SC17

November 13, 2017

AMD’s charge back into HPC and the datacenter is on full display at SC17. Having launched the EPYC processor line in June along with its MI25 GPU the focus he Read more…

By John Russell

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Google Releases Deeplearn.js to Further Democratize Machine Learning

August 17, 2017

Spreading the use of machine learning tools is one of the goals of Google’s PAIR (People + AI Research) initiative, which was introduced in early July. Last w Read more…

By John Russell

GlobalFoundries Puts Wind in AMD’s Sails with 12nm FinFET

September 24, 2017

From its annual tech conference last week (Sept. 20), where GlobalFoundries welcomed more than 600 semiconductor professionals (reaching the Santa Clara venue Read more…

By Tiffany Trader

Amazon Debuts New AMD-based GPU Instances for Graphics Acceleration

September 12, 2017

Last week Amazon Web Services (AWS) streaming service, AppStream 2.0, introduced a new GPU instance called Graphics Design intended to accelerate graphics. The Read more…

By John Russell

Leading Solution Providers

SC17 Booth Video Tours

EU Funds 20 Million Euro ARM+FPGA Exascale Project

September 7, 2017

At the Barcelona Supercomputer Centre on Wednesday (Sept. 6), 16 partners gathered to launch the EuroEXA project, which invests €20 million over three-and-a-half years into exascale-focused research and development. Led by the Horizon 2020 program, EuroEXA picks up the banner of a triad of partner projects — ExaNeSt, EcoScale and ExaNoDe — building on their work... Read more…

By Tiffany Trader

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Cray Moves to Acquire the Seagate ClusterStor Line

July 28, 2017

This week Cray announced that it is picking up Seagate's ClusterStor HPC storage array business for an undisclosed sum. "In short we're effectively transitioning the bulk of the ClusterStor product line to Cray," said CEO Peter Ungaro. Read more…

By Tiffany Trader

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

Intel Launches Software Tools to Ease FPGA Programming

September 5, 2017

Field Programmable Gate Arrays (FPGAs) have a reputation for being difficult to program, requiring expertise in specialty languages, like Verilog or VHDL. Easin Read more…

By Tiffany Trader

HPC Chips – A Veritable Smorgasbord?

October 10, 2017

For the first time since AMD's ill-fated launch of Bulldozer the answer to the question, 'Which CPU will be in my next HPC system?' doesn't have to be 'Whichever variety of Intel Xeon E5 they are selling when we procure'. Read more…

By Dairsie Latimer

Flipping the Flops and Reading the Top500 Tea Leaves

November 13, 2017

The 50th edition of the Top500 list, the biannual publication of the world’s fastest supercomputers based on public Linpack benchmarking results, was released Read more…

By Tiffany Trader

IBM Advances Web-based Quantum Programming

September 5, 2017

IBM Research is pairing its Jupyter-based Data Science Experience notebook environment with its cloud-based quantum computer, IBM Q, in hopes of encouraging a new class of entrepreneurial user to solve intractable problems that even exceed the capabilities of the best AI systems. Read more…

By Alex Woodie

Share This