Designer of Microprocessor-Memory Chip Aims to Topple Memory and Power Walls

By Michael Feldman

January 17, 2012

Whether you’re talking about high performance computers, enterprise servers, or mobile devices, the two biggest impediments to application performance in computing today are the memory wall and the power wall. Venray Technology is aiming to knock down those walls with a unique approach that puts CPU cores and DRAM on the same die. The company has been in semi-stealth mode since it inception seven years ago, but is now trying to get the word out about its technology as it searches for a commercial buyer.

Dallas-based Venray is the brainchild of Russell Fish, who made himself the CTO (there is no CEO listed on the website) and the principal architect. Fish is co-designer of the Sh-Boom Processor, and holder of multiple microprocessor patents. These patents turned out to be fundamental to the operation of modern microprocessors and have been licensed by practically every computer and semiconductor manufacturer on the planet. The proceeds from those patents are being used to fund Venray.

Since 2007, Fish and company have been engaged in the design and marketing of a novel CPU-DRAM technology, known as TOMI, which stands for Thread Optimized Multiprocessor. With TOMI, the company aims to do what no other chip maker has done before, namely embed a general-purpose processor in vanilla DRAM. The idea is to use the physical proximity of the CPU and memory, as well as extra-wide busses (4,096 bits, in the case of the first TOMI designs), to flatten the memory wall.

The memory wall is huge problem in high performance computing and big data applications today and will soon limit computing across all segments. The problem was brought home by a 2008 study of multicore performance at Sandia National Labs, in which researchers demonstrated that for certain classes of data-intensive applications, the use of extra cores to increase performance is counter-productive.

For these application profiles, performance basically flattened between four and eight cores, and actually declined beyond that. The problem was that as more cores were added, they were starved for the limited amount of memory bandwidth available, and after a certain point, the overhead of memory contention actually decreased performance. Prospective solutions, such as memory chip stacking (for example, Micron’s Hybrid Memory Cube) are unproven and have yet to find their way into the commercial market.

Some microprocessor-memory integration has been attempted with embedded DRAM (eDRAM), a technology that promises a lot more capacity than can be delivered by on-chip cache memory. It has been used as a foundation for some integrated SoC devices including IBM’s Power7 CPU and Blue Gene ASIC, as well as for many of the processors that power game console devices, such as the Sony PlayStation. Embedded DRAM was also the memory technology of choice for the 2000-era IRAM research effort, which aimed to integrate a 256-bit vector microprocessor with 16MB of memory.

But even though eDRAM is much denser than cache memory, it can’t provide the storage capacity of conventional DRAM. It is also hundreds of times as expensive as regular memory. “The people that have tried to combine CPUs and memory before have usually erred on the side of having the CPUs too big and the memory too small,” says Fish. “They did not understand the difference between embedding DRAM in CPUs and making CPUs in DRAMs.”

The challenge of melding CPUs with DRAM is that microprocessors are much more complex beasts than memories, and as a result, are manufactured with entirely different semiconductor processes. Typically semiconductor logic require ten or more layers of material to be laid down on the die, compared to just three for DRAM. However, if a microprocessor can be designed much more simply, reducing the number and complexity of logic gate connections, it is possible to more or less flatten the layout and use just three layers.

That is the fundamental magic used by TOMI. Its second-generation design, named Borealis, consists of an 8-core RISC CPU built using the three-layer DRAM process. The CPU itself is made up of just 22 thousand transistors (not including cache and the memory controller), embedded in a 1 Gbit DRAM chip. On the 42nm process node, the CPU takes up just 14 percent of the die.

It is possible to use the TOMI technology to implement legacy microprocessor architectures, but big CPUs, in particular, would not be able to squeeze onto their DRAM process technology — at least not at current CMOS geometries. In any case, Fish seem to think the optimal mix of memory to logic is around 5 to 1.

To get to that level, Fish and company pared down its CPU to just the basics: 32-bit integer hardware, and a small set of instructions (forgoing less useful instructions like auto-index and auto-decrement). The lack of floating point hardware, which tend to suck up a lot of silicon real estate, doesn’t rule out for support for those operations; they are just emulated via software libraries.

A very useful side effect of using the simpler DRAM processes is that it’s much cheaper to produce a CPU this way. The cost of manufacturing a billion DRAM transistors is less than a dollar versus more than $300 for a microprocessor. But another big savings is in power draw. The Borealis CPU at 2.1 GHz draws a measly 98 mW. Compare that to the 100-plus watts for an x86 CPU sporting a billion transistors.

Of course, the Borealis microprocessor is much less performant than a billion transistor CPU in raw compute power. It’s specifically built to maximize the throughput of analytics applications chewing on large datasets, aka big data. “We’ve probably built the most efficient big data processor in existence,” claims Fish.

To prove their point, Venray benchmarked their hardware with Sandia Labs’ MapReduce-MPI software and an unstructured data application running on their hardware — a circuit board with 16 Borealis chips (128 cores, 16GB of DRAM). According to the company, the TOMI system was able to achieve nearly 12 times the performance and use less than 1/10 the power compared to the same code running on an Intel Xeon-based cluster. Venray says the hardware would cost about $35 thousand versus $1.65 million for the equivalent x86 system.

Beyond benchmarks, TOMI is built for all sorts of data mining, high-end analytics, and pattern recognition software. To Fish, these are the killer applications that will drive the industry in the future. And since the architecture is naturally energy efficient, TOMI would be equally at home in mobile devices and in cloud servers.

The downside, of course, is that unlike x86 and ARM, the architecture has no vast ecosystem behind it. But according to Fish, by providing a C/C++ compiler via gcc, the whole Linux toolchain can be leveraged. For legacy applications, the bigger problem is the recoding that would have to be done. Most applications assume powerful single-threaded CPUs and small memory footprints, rather than the inverse. None of this deters Fish, who sees the legacy CPU architectures as a dead end, especially for big data applications that is poised to drive a lot of growth in the IT sector.

At this point, Fish and his cohorts are actively in search of a single buyer for TOMI, most likely a computer manufacturer of some sort. According to him, the advantage of the technology is wrapped up in its exclusivity, so licensing the IP would dilute the value to prospective customers. To date, they have received the most attention from buyers outside the US. One overseas group was ready to write “a large check,” but Fish declined, wanting to give US-based companies a shot. According to him, in the past five or six months, prospective buyers in the US have shown increased interest. “Lots of people want to be our friends right now,” he says.

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IBM Will Chip in on Micron’s 3D Hybrid Memory Cube

Up Against the Memory Wall

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