Silicon Valley-based Samplify Systems has launched an application acceleration technology designed to speed up codes that sling a lot of numerical data. But rather than throwing bigger, faster hardware at the problem, the company aims to make programs speedier by optimizing the data flow between the compute cores and the outside world.
Samplify, whose roots are in signal compression has extended the technology to address all numerically-intensive applications. For HPC users, Samplify’s heart is certainly in the right place. In high performance computing, application acceleration is the thirst that can never to be quenched.
The current performance issue in the industry is related to multicore designs. Processors are getting more powerful at a Moore’s Law clip thanks to a proliferation of cores, while bandwidth of external subsystems like memory and I/O is increasing much more slowly (and in discrete steps). That imbalance is the principle reason that HPC applications typically utilize just a small fraction of their hardware hosts.
For example, a science code called ECCO (Estimating Circulation and Climate of Ocean), one of the workhouse applications on NASA’s Pleiades supercomputer, uses only about 1.4 percent of the 1.3 petaflop peak performance of the machine. That’s due mainly to the fact that the CPUs are spending the majority of their time idly waiting for data to arrive. Unfortunately, that scenario is not much of an outlier. According to a research study at NASA, most of the applications on Pleiades have sustained performance in the 3 to 8 percent range.
Such stark inefficiencies are what drove Samplify to come up with its application acceleration offering, known as APAX. In a nutshell, APAX compresses numerical data (both integer and floating point) that flows through a system, thereby increasing data throughput. And it does so in a manner that is transparent to the application.
The technology is being offered in both hardware and software forms and can be deployed in a variety of ways. Specifically, the compression technology can be inserted at all the usual choke points in a computer system — memory, I/O, networks and storage — in order to attack application bottlenecks at their source.
According to Al Wegener, Samplify founder and CTO, most HPC users are not aware that there are a significant number of bits that can be squeezed out of their codes. In today’s supercomputing culture, the traditional solution to data bandwidth constraints has been to over-provision the hardware. “All of the HPC customers we talked to have never even thought of using compression for their applications,” Wegener told HPCwire.
The APAX technology supports both lossless and lossy compression schemes. Under APAX, the lossless scheme usually attains at least a 2:1 compression, effectively doubling bandwidth at the intended choke point. With lossy schemes, which are under user control, APAX compression can easily hit 4:1 and go as high as 8:1.
Here though, the user has to be somewhat careful, since lossy schemes rely on trimming off some of the numerical precision. In general, application programmers tend to be a bit lazy with precision, preferring to use generic data types in their codes and gravitating towards double precision floating point. But casting 12-bit integer inputs into 64-bit floating point values for the sake of convenience doesn’t magically increase the accuracy of the results and ends up wasting a lot of bits. In working with trial customers, Samplify has found that most applications can tolerate lossy compression in the 4:1 to 6:1 range before the results start to diverge.
From a performance per watt perspective, APAX hardware is probably the most efficient way to go. For example, if a chipmaker wanted to insert compression into its memory controller design, it would simply license the APAX IP block (a couple of hundred logic gates) from Samplify.
Once in the controller, the compression logic, along with compatible drivers, would squeeze the bits sent from the compute cores such that all numerical data would be stored in DRAM in a compressed format. When reading from memory, the same logic would decompress the data before passing it back to the number crunching silicon. Assuming 2:1 compression, memory bandwidth for all numerical data traffic would be doubled. Conveniently, it would also double the effective memory storage.
In an HPC environment, that can add up quickly. Wegener offers the case of NVIDIA’s Tesla GPU devices. Using 2:1 compression, the GPU card’s 6 GB of GDDR5 memory turn into 12 GB of effective storage. Likewise, the 150 GB/sec of bandwidth becomes 300 GB/sec. “I think that would be a big deal,” says Wegener.
Other likely targets for the compression technology would be network adapters, such as InfiniBand or Ethernet NICs, storage controllers, and Southbridge chips. Along with modified drivers, the compression-spiked ASICs would be able to turbo-charge data performance across a system, cluster or even a whole datacenter.
For HPC applications on existing hardware, the most straightforward method is to insert the APAX software into existing applications or wrap it around MPI libraries. This could be especially useful on more generic cloud infrastructure, such as what Amazon offers, where network capability and topology is much less conducive to HPC communication compared to a purpose-built supercomputer.
While the technology Samplify is offering is not a panacea for all these data bottlenecks, it has the potential to make a significant dent in throughput and storage. Right now the company is in the process of collecting proof points for the technology. According the Wegener, APAX has been validated by two Samplify investors: Schlumberger, an oil & gas exploration firm, and Mamiya, a Japanese manufacture of high-end digital cameras. In the case of Schlumberger, the technology is being used in its software incarnation, while Mamiya has inserted the APAX into its FPGA chips. Other trials are in process with seismic and multiphysics customers, but the company is not willing to name names at this point.
Samplify envisions a market for APAX in high performance and cloud computing as well as at the other end of the IT spectrum in mobile computing devices and consumer electronics. The company estimates a total addressable market of $700 million by 2014: $370 million for APAX IP blocks (Verilog RTL) on 1.8 billion devices and $330 million for APAX software on 16.7 million cores.
As of this week, the APAX technology is ready to ship in software form. The hardware IP block will be available for licensing in the middle of the year. Pricing has not been disclosed.