Retrofitting Programming Languages for a Parallel World

By James Reinders

February 23, 2012

The most widely used computer programming languages today were not designed as parallel programming languages. But retrofitting existing programming languages for parallel programming is underway. We can compare and contrast retrofits by looking at four key features, five key qualities, and the various implementation approaches.

In this article, I focus on the features and qualities, leaving the furious debates over best approaches (language vs. library vs. directives, and abstract and portable vs. low-level with lots of controls) for another day.

Four features we need

Features that any parallel programming solution, including retrofits, should include a defined memory model, synchronization, tasks, and data parallelism.

Memory model

Defining how changes in shared data are observable by different tasks had been an under-appreciated problem. Hans-J. Boehm wrote a report in 2004, titled Threads Cannot Be Implemented As a Library, which explains these issues. Having a well-defined ordering among accesses to distinct variables, and enabling the independence of updates to distinct variables, is so important that they have been addressed in Java, C11 and C++11. Without these retrofits, every parallel program sits on a crumbling foundation.

Synchronization

The need for portable and efficient synchronization is substantial. Boost libraries, Intel’s Threading Building Blocks (TBB) and OpenMP offer solutions that are widely utilized. C++11 and C11 now offer support. Beyond these, the concept of transactions is a topic worth exploring in a future article. Synchronization retrofitting is helping portability. Substantial opportunities remain for helping efficiency.

Tasks, not threads

Programming should be an exercise in writing tasks that can run concurrently, without the programmer specifying the precise mapping of tasks onto hardware threads. An introduction to this challenge is The Problem with Threads by Edward A. Lee.

Mapping should be the job of tools, including run-time schedulers, not explicit programming. This philosophy is being well supported by retrofits like OpenMP, TBB, Cilk Plus, Microsoft’s Parallel Patterns Library (PPL) and Apple’s Grand Central Dispatch (GCD). The need to assert some control over task to thread mapping to maximize performance is still present when using such systems today, but not always supported.

Nevertheless, programming directly to native threads (e.g., pthreads) in applications is something that should be completely avoided. Retrofits are sufficient today to make tasks the method of choice.

Data parallel support

It should be reasonably straightforward to write a portable program that takes advantage of data parallel hardware. Ideally, data parallel support should be able to utilize vector and task parallel capabilities without a programmer having to explicitly code the division between the two.

Unfortunately, no such solution is in wide spread use today even for vectorization alone. Effective auto-parallelization is very dependent on highly optimizing compilers. Compiler intrinsics lock code into a particular vector width (MMX=64, SSE=128, AVX=256, etc.). Elemental functions in CUDA, OpenCL, and Cilk Plus offer a glimpse into possible retrofits. Intel proposes we adopt the vectorization benefits of Fortran 90 array notations into C and C++ as part of the Cilk Plus project.

Vector hardware is increasingly important in processors, GPUs and co-processors. OpenCL and OpenMP wrestle today with how to embrace data parallel hardware and how tightly tied programming will be to it. Microsoft C++ AMP has similar challenges when it comes to market with the next Microsoft Visual Studio. Standard, abstract, portable and effective solutions wanted!

Five qualities we should desire

Five key qualities that are desirable, for parallel programming, include composability, sequential reasoning, communication minimization, performance portability and safety.

All of these qualities are unobtainable, in an absolute sense, whether as retrofits in an old language or with a clean slate and a new language. That is why we cannot call them features. The more of these qualities we obtain the better off we are. That makes them very important to keep in mind.

Composability

Composability is a well-known concept in programming, offering rules for combining different things together (functions, objects, modules, etc.) so that it is easy to compose (think: combine in unanticipated ways). It is important to think of composability in terms of both correctness and performance.

OpenCL, largely because it is less abstract, has low composability on both accounts. OpenMP and OpenCL have very serious performance composability unless they are used very carefully. New and abstract retrofits (TBB, Cilk, PPL, GCD) are much more tolerant and able to deliver high composability.

Self-composability is an essential first step, but the ability to compose multiple retrofits together is essential in the long run as well. A welcome solution for tool vendors, Microsoft’s Concurrency Runtime has allowed retrofits from multiple vendors to coexist with increased composability. Parallel programming without the ability to mix and match freely, is undesirable and counterproductive.

Composability deserves more attention than it gets.

Sequential reasoning

Sequential reasoning, the norm for reading a serial implementation, can apply with an appropriately expressed parallel program. OpenMP uses hints to create the use of parallelism instead of code changes. This allows the intent of a program to remain evident in the code. TBB and PPL emphasize relaxed sequential semantics to provide parallelism as an accelerator without making it mandatory for correctness. Writing a program in a sequentially consistent fashion is permitted and encouraged.

An explicit goal of Cilk Plus is to offer sequential semantics to set it apart from other retrofits. The serial elision (or C elision) of a Cilk program is touted in papers from MIT. Programming that preserves sequential semantics has received praise as easier to learn and use. The elemental functions in OpenCL, CUDA and Cilk Plus have similar objectives.

It is fair to say that programming in a manner that requires understanding parallel semantics, in order to understand intent, is both unpopular and out of vogue today. Such mandatory parallelism is harder to understand and to debug.

Sequential reasoning can be extended to debuggers too. A hot area to watch here is debuggers working to present a debugging experience more akin to sequential experiences, with features like Rogue Wave’s replay capabilities in the Totalview debugger.

Instead of sequential reasoning being a retrofit, it is more accurate to think of sequential reasoning as often being purposefully sought and preserved in a parallel world.

Communication minimization

Performance tuning on parallel systems often focuses on ensuring data is local when you use it and minimizing the need to move it around. Data motion means communication of some sort, and communication is generally expensive. Decisions in the design and implementation of retrofits, as well as the application programming itself, often impact performance dramatically. The task stealing algorithms of TBB, Cilk, PPL and GCD all have cache reuse strongly in mind in their designs. Retrofits to help, with communication minimization, are a tricky business and could use more attention.

Performance portability

The goal here is that a tuned program on one piece of hardware performs reasonably well on another piece of hardware. It is desirable to be able to describe data and tasks in such a way that performance scales as parallelism increases (number of cores, or size of vectors, or cache size, etc.). Nothing is ever fully performance portable, but more abstract retrofits tend to hold up better.

Unfortunately, implementations of abstractions can struggle to offer peak performance. It took years for compilers to offer performance for MMX or SSE that was competitive with assembly language programming. Use of cache-agnostic algorithms generally increase performance portability. Today, competing on performance with carefully-crafted CUDA and OpenCL code can be challenging because the coding is low level enough to encourage, or even require, the program structure to match the hardware. The lack of performance portability of such code is frequently shown, but effective alternatives remain works-in-progress. Language design, algorithm choices and programming style can affect performance portability a great deal.

Safety

The freedom from deadlocks and race conditions, may be the most difficult to provide via a retrofit. No method to add complete safety to C or C++ has gained wide popularity. Safety has not been incorporated into non-managed languages easily, despite some valiant efforts to do so.

To make a language safe, pointers have to be removed or severely restricted. Meanwhile, tools are maturing to help us cope with safety despite lack of direct language support, and safer coding style and safer retrofits appear to help as well. Perhaps safety comes via a combination of “good enough” and “we can cope using tools.”

A journey ahead, together

There are at least four key programming problems that any parallel programming solution should address, and five key qualities that can make a programming model, retrofit or otherwise, more desirable. Evolution in hardware will help as well.

—–

About the author

James Reinders has helped develop supercomputers, microprocessors and software tools for 25 years. He is a senior engineer for Intel in Hillsboro Oregon.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

IDC: Will the Real Exascale Race Please Stand Up?

February 21, 2017

So the exascale race is on. And lots of organizations are in the pack. Government announcements from the US, China, India, Japan, and the EU indicate that they are working hard to make it happen – some sooner, some later. Read more…

By Bob Sorensen, IDC

ExxonMobil, NCSA, Cray Scale Reservoir Simulation to 700,000+ Processors

February 17, 2017

In a scaling breakthrough for oil and gas discovery, ExxonMobil geoscientists report they have harnessed the power of 717,000 processors – the equivalent of 22,000 32-processor computers – to run complex oil and gas reservoir simulation models. Read more…

By Doug Black

TSUBAME3.0 Points to Future HPE Pascal-NVLink-OPA Server

February 17, 2017

Since our initial coverage of the TSUBAME3.0 supercomputer yesterday, more details have come to light on this innovative project. Of particular interest is a new board design for NVLink-equipped Pascal P100 GPUs that will create another entrant to the space currently occupied by Nvidia's DGX-1 system, IBM's "Minsky" platform and the Supermicro SuperServer (1028GQ-TXR). Read more…

By Tiffany Trader

Tokyo Tech’s TSUBAME3.0 Will Be First HPE-SGI Super

February 16, 2017

In a press event Friday afternoon local time in Japan, Tokyo Institute of Technology (Tokyo Tech) announced its plans for the TSUBAME3.0 supercomputer, which will be Japan’s “fastest AI supercomputer,” Read more…

By Tiffany Trader

HPE Extreme Performance Solutions

O&G Companies Create Value with High Performance Remote Visualization

Today’s oil and gas (O&G) companies are striving to process datasets that have become not only tremendously large, but extremely complex. And the larger that data becomes, the harder it is to move and analyze it – particularly with a workforce that could be distributed between drilling sites, offshore rigs, and remote offices. Read more…

Drug Developers Use Google Cloud HPC in the Fight Against ALS

February 16, 2017

Within the haystack of a lethal disease such as ALS (amyotrophic lateral sclerosis / Lou Gehrig’s Disease) there exists, somewhere, the needle that will pierce this therapy-resistant affliction. Read more…

By Doug Black

Weekly Twitter Roundup (Feb. 16, 2017)

February 16, 2017

Here at HPCwire, we aim to keep the HPC community apprised of the most relevant and interesting news items that get tweeted throughout the week. Read more…

By Thomas Ayres

Alexander Named Dep. Dir. of Brookhaven Computational Initiative

February 15, 2017

Francis Alexander, a physicist with extensive management and leadership experience in computational science research, has been named Deputy Director of the Computational Science Initiative at the U.S. Read more…

Here’s What a Neural Net Looks Like On the Inside

February 15, 2017

Ever wonder what the inside of a machine learning model looks like? Today Graphcore released fascinating images that show how the computational graph concept maps to a new graph processor and graph programming framework it’s creating. Read more…

By Alex Woodie

IDC: Will the Real Exascale Race Please Stand Up?

February 21, 2017

So the exascale race is on. And lots of organizations are in the pack. Government announcements from the US, China, India, Japan, and the EU indicate that they are working hard to make it happen – some sooner, some later. Read more…

By Bob Sorensen, IDC

TSUBAME3.0 Points to Future HPE Pascal-NVLink-OPA Server

February 17, 2017

Since our initial coverage of the TSUBAME3.0 supercomputer yesterday, more details have come to light on this innovative project. Of particular interest is a new board design for NVLink-equipped Pascal P100 GPUs that will create another entrant to the space currently occupied by Nvidia's DGX-1 system, IBM's "Minsky" platform and the Supermicro SuperServer (1028GQ-TXR). Read more…

By Tiffany Trader

Tokyo Tech’s TSUBAME3.0 Will Be First HPE-SGI Super

February 16, 2017

In a press event Friday afternoon local time in Japan, Tokyo Institute of Technology (Tokyo Tech) announced its plans for the TSUBAME3.0 supercomputer, which will be Japan’s “fastest AI supercomputer,” Read more…

By Tiffany Trader

Drug Developers Use Google Cloud HPC in the Fight Against ALS

February 16, 2017

Within the haystack of a lethal disease such as ALS (amyotrophic lateral sclerosis / Lou Gehrig’s Disease) there exists, somewhere, the needle that will pierce this therapy-resistant affliction. Read more…

By Doug Black

Azure Edges AWS in Linpack Benchmark Study

February 15, 2017

The “when will clouds be ready for HPC” question has ebbed and flowed for years. Read more…

By John Russell

Is Liquid Cooling Ready to Go Mainstream?

February 13, 2017

Lost in the frenzy of SC16 was a substantial rise in the number of vendors showing server oriented liquid cooling technologies. Three decades ago liquid cooling was pretty much the exclusive realm of the Cray-2 and IBM mainframe class products. That’s changing. We are now seeing an emergence of x86 class server products with exotic plumbing technology ranging from Direct-to-Chip to servers and storage completely immersed in a dielectric fluid. Read more…

By Steve Campbell

Cray Posts Best-Ever Quarter, Visibility Still Limited

February 10, 2017

On its Wednesday earnings call, Cray announced the largest revenue quarter in the company’s history and the second-highest revenue year. Read more…

By Tiffany Trader

HPC Cloud Startup Launches ‘App Store’ for HPC Workflows

February 9, 2017

“Civilization advances by extending the number of important operations which we can perform without thinking about them,” Read more…

By Tiffany Trader

For IBM/OpenPOWER: Success in 2017 = (Volume) Sales

January 11, 2017

To a large degree IBM and the OpenPOWER Foundation have done what they said they would – assembling a substantial and growing ecosystem and bringing Power-based products to market, all in about three years. Read more…

By John Russell

US, China Vie for Supercomputing Supremacy

November 14, 2016

The 48th edition of the TOP500 list is fresh off the presses and while there is no new number one system, as previously teased by China, there are a number of notable entrants from the US and around the world and significant trends to report on. Read more…

By Tiffany Trader

Lighting up Aurora: Behind the Scenes at the Creation of the DOE’s Upcoming 200 Petaflops Supercomputer

December 1, 2016

In April 2015, U.S. Department of Energy Undersecretary Franklin Orr announced that Intel would be the prime contractor for Aurora: Read more…

By Jan Rowell

D-Wave SC16 Update: What’s Bo Ewald Saying These Days

November 18, 2016

Tucked in a back section of the SC16 exhibit hall, quantum computing pioneer D-Wave has been talking up its new 2000-qubit processor announced in September. Forget for a moment the criticism sometimes aimed at D-Wave. This small Canadian company has sold several machines including, for example, ones to Lockheed and NASA, and has worked with Google on mapping machine learning problems to quantum computing. In July Los Alamos National Laboratory took possession of a 1000-quibit D-Wave 2X system that LANL ordered a year ago around the time of SC15. Read more…

By John Russell

Enlisting Deep Learning in the War on Cancer

December 7, 2016

Sometime in Q2 2017 the first ‘results’ of the Joint Design of Advanced Computing Solutions for Cancer (JDACS4C) will become publicly available according to Rick Stevens. He leads one of three JDACS4C pilot projects pressing deep learning (DL) into service in the War on Cancer. Read more…

By John Russell

IBM Wants to be “Red Hat” of Deep Learning

January 26, 2017

IBM today announced the addition of TensorFlow and Chainer deep learning frameworks to its PowerAI suite of deep learning tools, which already includes popular offerings such as Caffe, Theano, and Torch. Read more…

By John Russell

HPC Startup Advances Auto-Parallelization’s Promise

January 23, 2017

The shift from single core to multicore hardware has made finding parallelism in codes more important than ever, but that hasn’t made the task of parallel programming any easier. Read more…

By Tiffany Trader

CPU Benchmarking: Haswell Versus POWER8

June 2, 2015

With OpenPOWER activity ramping up and IBM’s prominent role in the upcoming DOE machines Summit and Sierra, it’s a good time to look at how the IBM POWER CPU stacks up against the x86 Xeon Haswell CPU from Intel. Read more…

By Tiffany Trader

Leading Solution Providers

Nvidia Sees Bright Future for AI Supercomputing

November 23, 2016

Graphics chipmaker Nvidia made a strong showing at SC16 in Salt Lake City last week. Read more…

By Tiffany Trader

BioTeam’s Berman Charts 2017 HPC Trends in Life Sciences

January 4, 2017

Twenty years ago high performance computing was nearly absent from life sciences. Today it’s used throughout life sciences and biomedical research. Genomics and the data deluge from modern lab instruments are the main drivers, but so is the longer-term desire to perform predictive simulation in support of Precision Medicine (PM). There’s even a specialized life sciences supercomputer, ‘Anton’ from D.E. Shaw Research, and the Pittsburgh Supercomputing Center is standing up its second Anton 2 and actively soliciting project proposals. There’s a lot going on. Read more…

By John Russell

Tokyo Tech’s TSUBAME3.0 Will Be First HPE-SGI Super

February 16, 2017

In a press event Friday afternoon local time in Japan, Tokyo Institute of Technology (Tokyo Tech) announced its plans for the TSUBAME3.0 supercomputer, which will be Japan’s “fastest AI supercomputer,” Read more…

By Tiffany Trader

IDG to Be Bought by Chinese Investors; IDC to Spin Out HPC Group

January 19, 2017

US-based publishing and investment firm International Data Group, Inc. (IDG) will be acquired by a pair of Chinese investors, China Oceanwide Holdings Group Co., Ltd. Read more…

By Tiffany Trader

Dell Knights Landing Machine Sets New STAC Records

November 2, 2016

The Securities Technology Analysis Center, commonly known as STAC, has released a new report characterizing the performance of the Knight Landing-based Dell PowerEdge C6320p server on the STAC-A2 benchmarking suite, widely used by the financial services industry to test and evaluate computing platforms. The Dell machine has set new records for both the baseline Greeks benchmark and the large Greeks benchmark. Read more…

By Tiffany Trader

What Knights Landing Is Not

June 18, 2016

As we get ready to launch the newest member of the Intel Xeon Phi family, code named Knights Landing, it is natural that there be some questions and potentially some confusion. Read more…

By James Reinders, Intel

KNUPATH Hermosa-based Commercial Boards Expected in Q1 2017

December 15, 2016

Last June tech start-up KnuEdge emerged from stealth mode to begin spreading the word about its new processor and fabric technology that’s been roughly a decade in the making. Read more…

By John Russell

Intel and Trump Announce $7B for Fab 42 Targeting 7nm

February 8, 2017

In what may be an attempt by President Trump to reset his turbulent relationship with the high tech industry, he and Intel CEO Brian Krzanich today announced plans to invest more than $7 billion to complete Fab 42. Read more…

By John Russell

  • arrow
  • Click Here for More Headlines
  • arrow
Share This