HP Scientists Envision 10-Teraflop Manycore Chip

By Michael Feldman

March 15, 2012

In high performance computing, Hewlett-Packard is best known for supplying bread-and-butter HPC systems, built with standard processors and interconnects. But the company’s research arm has been devising a manycore chipset, which would outrun the average-sized HPC cluster of today. The design represents a radical leap in performance, and if implemented, would fulfill the promise of exascale computing.

The architecture, known as Corona, first conceived back in 2008, consists of a 256-core CPU, an optical memory module, integrated nanophotonics and 3D chip stacking employing through-silicon-vias (TSVs). At peak output, Corona should deliver 10 teraflops of performance. That’s assuming 16 nm CMOS process technology, which is expected to be on tap by 2017.

The Corona design is aimed squarely at data-intensive types of application, whose speed is limited by the widening gap between CPU performance and available bandwidth to DRAM — the so-called memory wall. Basically any workload whose data does not fit into processor cache is a candidate. This includes not just traditional big data applications, but also a whole bunch of interesting HPC simulations and analytics codes that have to manipulate large or irregular data sets, and are thus memory-constrained.

At the CPU level, Corona contains 256 cores, each supporting up to four threads simultaneously. The Corona cores themselves are nothing exotic. The HP researchers originally assumed low-power Intel x86 Penryn and Silverthorne CPU core architectures for their design simulations, but presumably ARM or other low-power designs could be substituted.

The processor is divided into 16 quad-core “clusters,” with an integrated memory controller on every cluster. The rationale for the hierarchy is to ensure that memory bandwidth grows in concert with the core count and local memory access maintains low latency.

The processor is stacked with the memory controller/L2 cache, the analog electronics and the optical die (which includes on-chip lasers). Everything is hooked together by a 20 TB/sec dense wavelength division multiplexing (DWDM) crossbar, enabling cache coherency between cores, as well as superfast access to that cache.

The memory module, known as optically connected memory (OCM), is a separate chip stack made up of DRAM chips, plus the optical die and interface. It’s connected to the CPU stack at a still rather impressive 10 TB/sec.

To put that into perspective, the current crop of commercial processors have to get by with just a fraction of that bandwidth. The latest 8-core Intel E5-2600 Xeons, for example, can manage about 80 GB/sec of memory bandwidth and the SPARC64 VIIIfx CPU, of K computer fame, supports 64 GB/sec. Even GPUs, which generally support bigger memory pipes (but have to feed hundreds of cores), are bandwidth constrained. NVIDIA fastest Tesla card, the M2090, maxes out at 177 GB/sec.

The main function of Corona’s optical interconnect is to redress the worsening bytes-to-flop ratio that HPC’ers have been lamenting about for over a decade. For memory-constrained applications, it’s preferable to have a byte-to-flop ratio of at least one. Back in the good old days of the late 20th century, computers delivered 8 bytes or more per flop. Now, for current CPUs and GPUs, it’s down to between a half and a quarter of byte per flop.

The primary reasons for the poor ratio are the pin limitations on multicore processors, the inability to extend chip-level communication links across an entire node or computer, and the energy costs of electrical signaling. Photonics ameliorates these problems significantly since light is a much more efficient communication medium than electrons — something long-haul network providers discovered awhile ago.

Energy efficiency, in particular, is a hallmark of photonic communication. The HP researchers calculate that a memory system using an electrical interconnect to drive 10 GB/sec of data to DRAM would take 80 watts. Using nanophotonics and DRAMs optimized to read or write just a cache line at a time, they think they achieve the same bandwidth with just 8 watts.

The trick is to get the optical hardware down onto the silicon. Thanks to recent advances in integrated photonics, the technology is getting close. For example, the Corona design specifies crystalline and silicon dioxide for the wave guides, which are two commonly used materials in CMOS manufacturing. Slightly more exotic is the use of Germanium for the receptors (to absorb the light so that it can be converted back into electrical signals), a less often used, but still CMOS-compatible material. Finally, for the light source, the Corona designers opted for mode-locked lasers, since they believe a single device can provide up to 64 wavelengths of light for the DWDM interconnect.

Using the SPLASH-2, the second version of the Stanford Parallel Applications for Shared Memory benchmark suite, the HP researchers demonstrated a performance improvement of 2 to 6 times on Corona compared to a similar system outfitted with an electrical interconnect, and those speed increases were achieved using much less power. They also showed significant performance improvements on five of the six HPC Challenge benchmarks: PTRANS (22X), STREAM (19X), GUPS (19X), MPI (19X), FFT (2X). DGEMM, which is not bandwidth limited, showed no improvement.

It’s not all a slam dunk, however. 3D chipmaking and TSV technology is still a work in progress. And integrating photonic hardware using CMOS is in its infancy. But integrated photonics, 3D chip stacking, and the use of low-power cores for computation are all hot technologies now, especially for those in the supercomputing community looking down the road to exascale. The UHPC project (now apparently stuck in Phase 1) that was aimed at developing low-power extreme-scale computing, attracted proposals from Intel, MIT, NVIDIA, and Sandia that incorporated one or more of these technologies.

With Corona though, you get the whole package, so to speak. But all of the work to date appears to be with simulated hardware, and there was no mention in any of the research work of plans to create a working prototype. So whether this is destined to remain a research project at HP or something that gets transformed into a commercial offering remains to be seen.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Exascale Escapes 2018 Budget Axe; Rest of Science Suffers

May 23, 2017

President Trump's proposed $4.1 trillion FY 2018 budget is good for U.S. exascale computing development, but grim for the rest of science and technology spend Read more…

By Tiffany Trader

Hedge Funds (with Supercomputing help) Rank First Among Investors

May 22, 2017

In case you didn’t know, The Quants Run Wall Street Now, or so says a headline in today’s Wall Street Journal. Quant-run hedge funds now control the largest Read more…

By John Russell

IBM, D-Wave Report Quantum Computing Advances

May 18, 2017

IBM said this week it has built and tested a pair of quantum computing processors, including a prototype of a commercial version. That progress follows an an Read more…

By George Leopold

PRACEdays 2017 Wraps Up in Barcelona

May 18, 2017

Barcelona has been absolutely lovely; the weather, the food, the people. I am, sadly, finishing my last day at PRACEdays 2017 with two sessions: an in-depth loo Read more…

By Kim McMahon

HPE Extreme Performance Solutions

Exploring the Three Models of Remote Visualization

The explosion of data and advancement of digital technologies are dramatically changing the way many companies do business. With the help of high performance computing (HPC) solutions and data analytics platforms, manufacturers are developing products faster, healthcare providers are improving patient care, and energy companies are improving planning, exploration, and production. Read more…

US, Europe, Japan Deepen Research Computing Partnership

May 18, 2017

On May 17, 2017, a ceremony was held during the PRACEdays 2017 conference in Barcelona to announce the memorandum of understanding (MOU) between PRACE in Europe Read more…

By Tiffany Trader

NSF, IARPA, and SRC Push into “Semiconductor Synthetic Biology” Computing

May 18, 2017

Research into how biological systems might be fashioned into computational technology has a long history with various DNA-based computing approaches explored. N Read more…

By John Russell

DOE’s HPC4Mfg Leads to Paper Manufacturing Improvement

May 17, 2017

Papermaking ranks third behind only petroleum refining and chemical production in terms of energy consumption. Recently, simulations made possible by the U.S. D Read more…

By John Russell

PRACEdays 2017: The start of a beautiful week in Barcelona

May 17, 2017

Touching down in Barcelona on Saturday afternoon, it was warm, sunny, and oh so Spanish. I was greeted at my hotel with a glass of Cava to sip and treated to a Read more…

By Kim McMahon

Exascale Escapes 2018 Budget Axe; Rest of Science Suffers

May 23, 2017

President Trump's proposed $4.1 trillion FY 2018 budget is good for U.S. exascale computing development, but grim for the rest of science and technology spend Read more…

By Tiffany Trader

Cray Offers Supercomputing as a Service, Targets Biotechs First

May 16, 2017

Leading supercomputer vendor Cray and datacenter/cloud provider the Markley Group today announced plans to jointly deliver supercomputing as a service. The init Read more…

By John Russell

HPE’s Memory-centric The Machine Coming into View, Opens ARMs to 3rd-party Developers

May 16, 2017

Announced three years ago, HPE’s The Machine is said to be the largest R&D program in the venerable company’s history, one that could be progressing tow Read more…

By Doug Black

What’s Up with Hyperion as It Transitions From IDC?

May 15, 2017

If you’re wondering what’s happening with Hyperion Research – formerly the IDC HPC group – apparently you are not alone, says Steve Conway, now senior V Read more…

By John Russell

Nvidia’s Mammoth Volta GPU Aims High for AI, HPC

May 10, 2017

At Nvidia's GPU Technology Conference (GTC17) in San Jose, Calif., this morning, CEO Jensen Huang announced the company's much-anticipated Volta architecture a Read more…

By Tiffany Trader

HPE Launches Servers, Services, and Collaboration at GTC

May 10, 2017

Hewlett Packard Enterprise (HPE) today launched a new liquid cooled GPU-driven Apollo platform based on SGI ICE architecture, a new collaboration with NVIDIA, a Read more…

By John Russell

IBM PowerAI Tools Aim to Ease Deep Learning Data Prep, Shorten Training 

May 10, 2017

A new set of GPU-powered AI software announced by IBM today brings automation to many of the tedious, time consuming and complex aspects of AI project on-rampin Read more…

By Doug Black

Bright Computing 8.0 Adds Azure, Expands Machine Learning Support

May 9, 2017

Bright Computing, long a prominent provider of cluster management tools for HPC, today released version 8.0 of Bright Cluster Manager and Bright OpenStack. The Read more…

By John Russell

Quantum Bits: D-Wave and VW; Google Quantum Lab; IBM Expands Access

March 21, 2017

For a technology that’s usually characterized as far off and in a distant galaxy, quantum computing has been steadily picking up steam. Just how close real-wo Read more…

By John Russell

Trump Budget Targets NIH, DOE, and EPA; No Mention of NSF

March 16, 2017

President Trump’s proposed U.S. fiscal 2018 budget issued today sharply cuts science spending while bolstering military spending as he promised during the cam Read more…

By John Russell

Google Pulls Back the Covers on Its First Machine Learning Chip

April 6, 2017

This week Google released a report detailing the design and performance characteristics of the Tensor Processing Unit (TPU), its custom ASIC for the inference Read more…

By Tiffany Trader

HPC Compiler Company PathScale Seeks Life Raft

March 23, 2017

HPCwire has learned that HPC compiler company PathScale has fallen on difficult times and is asking the community for help or actively seeking a buyer for its a Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Last week, Google reported that its custom ASIC Tensor Processing Unit (TPU) was 15-30x faster for inferencing workloads than Nvidia's K80 GPU (see our coverage Read more…

By Tiffany Trader

CPU-based Visualization Positions for Exascale Supercomputing

March 16, 2017

Since our first formal product releases of OSPRay and OpenSWR libraries in 2016, CPU-based Software Defined Visualization (SDVis) has achieved wide-spread adopt Read more…

By Jim Jeffers, Principal Engineer and Engineering Leader, Intel

TSUBAME3.0 Points to Future HPE Pascal-NVLink-OPA Server

February 17, 2017

Since our initial coverage of the TSUBAME3.0 supercomputer yesterday, more details have come to light on this innovative project. Of particular interest is a ne Read more…

By Tiffany Trader

Nvidia’s Mammoth Volta GPU Aims High for AI, HPC

May 10, 2017

At Nvidia's GPU Technology Conference (GTC17) in San Jose, Calif., this morning, CEO Jensen Huang announced the company's much-anticipated Volta architecture a Read more…

By Tiffany Trader

Leading Solution Providers

Facebook Open Sources Caffe2; Nvidia, Intel Rush to Optimize

April 18, 2017

From its F8 developer conference in San Jose, Calif., today, Facebook announced Caffe2, a new open-source, cross-platform framework for deep learning. Caffe2 is Read more…

By Tiffany Trader

Tokyo Tech’s TSUBAME3.0 Will Be First HPE-SGI Super

February 16, 2017

In a press event Friday afternoon local time in Japan, Tokyo Institute of Technology (Tokyo Tech) announced its plans for the TSUBAME3.0 supercomputer, which w Read more…

By Tiffany Trader

Is Liquid Cooling Ready to Go Mainstream?

February 13, 2017

Lost in the frenzy of SC16 was a substantial rise in the number of vendors showing server oriented liquid cooling technologies. Three decades ago liquid cooling Read more…

By Steve Campbell

MIT Mathematician Spins Up 220,000-Core Google Compute Cluster

April 21, 2017

On Thursday, Google announced that MIT math professor and computational number theorist Andrew V. Sutherland had set a record for the largest Google Compute Eng Read more…

By Tiffany Trader

IBM Wants to be “Red Hat” of Deep Learning

January 26, 2017

IBM today announced the addition of TensorFlow and Chainer deep learning frameworks to its PowerAI suite of deep learning tools, which already includes popular Read more…

By John Russell

US Supercomputing Leaders Tackle the China Question

March 15, 2017

As China continues to prove its supercomputing mettle via the Top500 list and the forward march of its ambitious plans to stand up an exascale machine by 2020, Read more…

By Tiffany Trader

HPC Technique Propels Deep Learning at Scale

February 21, 2017

Researchers from Baidu's Silicon Valley AI Lab (SVAIL) have adapted a well-known HPC communication technique to boost the speed and scale of their neural networ Read more…

By Tiffany Trader

DOE Supercomputer Achieves Record 45-Qubit Quantum Simulation

April 13, 2017

In order to simulate larger and larger quantum systems and usher in an age of "quantum supremacy," researchers are stretching the limits of today's most advance Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This