Accelerating bioinformatics with hybrid-core computing

By Nicole Hemsoth

April 2, 2012

Advances in sequencing technology have significantly increased data generation and require commensurate computational advances for bioinformatics analysis. Advanced architectures based on reconfigurable computing can reduce application run times from hours to minutes and address problem sizes unattainable with commodity servers. The increased capability also fundamentally improves research quality by allowing more accurate, previously impractical approaches. The use of a hybrid-core computing architecture can be used to solve data-intensive problems of next-generation sequencing analysis like de novo assembly and reference mapping of short-read sequences.

Two important steps in next-generation sequencing analysis are de novo assembly and reference mapping of short-read sequences. Both of these lend themselves to high levels of acceleration with the FPGA-based coprocessor on the Convey systems. Convey’s bioinformatics applications Graph Constructor and BWA can be used in conjunction with, or replace, workflows using standard Velvet[1] and BWA[2], respectively. Graph Constructor reduces not only run time for Velvet, but also reduces memory requirements, making it capable of larger assemblies. Additional performance and workflow optimization includes a fast kmer counting tool that allows quick identification of optimal kmer length and coverage cutoffs for de novo assembly.

Convey’s Hybrid Core Architecture: Fast Compute, Faster Memory

The Convey Hybrid-Core (HC) architecture pairs Intel® x86 microprocessors with a coprocessor comprised of reconfigurable hardware (FPGAs) (Figure 1). Algorithms are implemented as instructions, called personalities, which are loaded onto the FPGAs at runtime to accelerate the applications that use them. Complementing the high performance of the reconfigurable compute elements, Convey’s hybrid-core system also has a highly parallel memory subsystem that is optimized for random accesses. Hybrid-Core Globally Shared Memory (HCGSM) provides a single coherent view of memory to the cache based x86 cores and the high throughput word optimized processing elements on the coprocessor. Bioinformatics applications that experience memory performance limitations on cache-based x86 servers greatly benefit from Convey’s memory architecture.

 The Convey Hybrid-Core Architecture

Figure 1. The Convey Hybrid-Core Architecture. The architecture pairs an Intel x86 host system tightly integrated with a reconfigurable FPGA based coprocessor. Hybrid-Core Globally Shared Memory (HCGSM) provides a single coherent view of memory to the x86 cores and the coprocessor’s highly parallel memory subsystem.

Burrows-Wheeler and de Bruijn Graph Personalities

de Bruijn graph-based assemblers such as Velvet consist of large numbers of relatively simple operations on large randomly accessed data structures. Conventional architectures lack sufficient parallelism in the core processing elements and the memory subsystem to efficiently execute these algorithms. The Convey Graph Constructor implements a high speed de Bruijn graph generator that can reduce the runtime and memory footprint for graph-based genome assembly. It can be run by itself or in conjunction with the Velvet application.

Other algorithms also benefit from massively parallel implementations of application-appropriate-data-type operations, which use logic gates more efficiently than commodity servers. In Burrows-Wheeler mapping applications, significant gains are made in the population bit count required to traverse the compressed reference suffix trees in memory. Convey has developed a personality that improves the performance of the aln step of the BWA processing pipeline, and a version of the open-source BWA application with thread parallelized single- and paired-end processing. The BWA personality has 64 alignment units which each operate on 32 sequences simultaneously, for a total of 2,048 simultaneous alignment operations.

Align and Paired End Performance for Human Genome

For these tests (Figure 1) we aligned paired-end sequence data from the 1000 Genomes project to a human reference (human_g1k_v37), consisting of 84 sequences and a total of 3.1 billion bases. SRR189815_1 and SRR189815_2 are paired-end Illumina reads from individual HG00124 containing a total of 242 million reads, average length 101. The aln steps were run using Convey accelerated BWA on HC-1 and HC-1ex systems, and the paired end step was run on a commodity x86 system using a parallelized version of bwa sampe. The results are compared to BWA 0.5.9 running on the commodity server.

 Align and Paired End Performance for Human Genome

Figure 1. Align and Paired End Performance for Human Genome. The addition of an HC-1ex and the Convey accelerated BWA pipeline to a commodity x86 system delivers 14.7x the throughput of the x86 system alone, processing 120 K reads/sec.

Results

  • Convey’s hardware accelerated aln is 7.5x (HC-1) and 9x (HC-1ex) over a 12-core x86.
  • Thread parallel sampe is 7.3x faster than the standard bwa implementation on the same hardware.
  • The addition of an HC-1ex and the Convey accelerated BWA pipeline to a commodity x86 system delivers 14.7x the throughput of the x86 system alone, processing 120 K reads/sec.

de novo Assembly Parameter Optimization

A feature of the Convey Bioinformatics Suite is the Kmer Counter. The Convey Kmer Counter generates a histogram of kmer coverage counts by hashing kmers in each read sequence. As shown in Figure 2, analysis of the read data aids in selecting optimal kmer length and coverage cutoff values for de novo assembly.

 Histogram of kmer coverage for the Assemblathon data set, as produced by Convey’s Kmer Counter for kmer length 21.

Figure 2. Histogram of kmer coverage for the Assemblathon data set, as produced by Convey’s Kmer Counter for kmer length 21. Statistics for assembly results using the selected coverage cutoffs show the impact of parameter selection on assembly quality, as compared with Velvet’s default setting. Convey’s Kmer Counter can analyze multiple kmer lengths in the same run as shown in the blue overlay.

Results:

  • Higher quality assemblies by using optimal parameters
  • Reduced run time and memory by avoiding poor kmers
  • Extremely efficient compared with VelvetOptimiser
  • Handles longer kmer lengths than Jellyfish
  • Analyzes multiple kmer lengths in a single job

Summary

Convey has developed a personality that improves the performance of the aln step of the BWA processing pipeline, and a parallelized version of the samse and sampe processing steps, that allow Convey systems to dramatically reduce time to solution and increase throughput 15x for a full BWA paired-end pipeline, processing 120 K reads/sec.

We have developed a GraphConstructor personality that interfaces to Velvet and Oases that reduces memory requirements by about 75% and accelerates throughput by an order of magnitude, making it possible to tackle previously impractical genomes with higher quality results. In addition to this work, there are several other projects recently submitted or in progress comparing the performance and accuracy of Convey’s Graph Constructor for genome and transcriptome assemblies, comparing with a range of popular assembly programs.

We are working on additional performance and workflow optimization for these applications, as well as accelerating additional applications.

References and Acknowledgements

  1. “Velvet: Algorithms for de novo Short Read Assembly Using de Bruijn Graphs”, Daniel R. Zerbino and Ewan Birney, EMBL-European Bioinformatics Institute, Genome Res. 18 (2008) 821.
  2. “Fast and Accurate Short Read Alignment with Burrows-Wheeler Transform”, Heng Li and Richard Durban, Wellcome Trust Sanger Institute, Bioinformatics 25 (2009) 1754.
  3. “Metagenomic discovery of biomass-degrading genes and genomes from cow rumen”, Hess ,et al, Science 331 (2011) 463.
  4. “Efficient Graph Based Assembly of Short-Read Sequences on a Hybrid Core Architecture“ Alex Sczyrba, Abhishek Pratap, Shane Canon, James Han, Alex Copeland, Zhong Wang, DOE Joint Genome Institute User Meeting, March 2011.

For more information go to Convey Computer.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Machine Learning at HPC User Forum: Drilling into Specific Use Cases

September 22, 2017

The 66th HPC User Forum held September 5-7, in Milwaukee, Wisconsin, at the elegant and historic Pfister Hotel, highlighting the 1893 Victorian décor and art of “The Grand Hotel Of The West,” contrasted nicely with Read more…

By Arno Kolster

Google Cloud Makes Good on Promise to Add Nvidia P100 GPUs

September 21, 2017

Google has taken down the notice on its cloud platform website that says Nvidia Tesla P100s are “coming soon.” That's because the search giant has announced the beta launch of the high-end P100 Nvidia Tesla GPUs on t Read more…

By George Leopold

Cray Wins $48M Supercomputer Contract from KISTI

September 21, 2017

It was a good day for Cray which won a $48 million contract from the Korea Institute of Science and Technology Information (KISTI) for a 128-rack CS500 cluster supercomputer. The new system, equipped with Intel Xeon Scal Read more…

By John Russell

HPE Extreme Performance Solutions

HPE Prepares Customers for Success with the HPC Software Portfolio

High performance computing (HPC) software is key to harnessing the full power of HPC environments. Development and management tools enable IT departments to streamline installation and maintenance of their systems as well as create, optimize, and run their HPC applications. Read more…

Adolfy Hoisie to Lead Brookhaven’s Computing for National Security Effort

September 21, 2017

Brookhaven National Laboratory announced today that Adolfy Hoisie will chair its newly formed Computing for National Security department, which is part of Brookhaven’s new Computational Science Initiative (CSI). Read more…

By John Russell

Machine Learning at HPC User Forum: Drilling into Specific Use Cases

September 22, 2017

The 66th HPC User Forum held September 5-7, in Milwaukee, Wisconsin, at the elegant and historic Pfister Hotel, highlighting the 1893 Victorian décor and art o Read more…

By Arno Kolster

Stanford University and UberCloud Achieve Breakthrough in Living Heart Simulations

September 21, 2017

Cardiac arrhythmia can be an undesirable and potentially lethal side effect of drugs. During this condition, the electrical activity of the heart turns chaotic, Read more…

By Wolfgang Gentzsch, UberCloud, and Francisco Sahli, Stanford University

PNNL’s Center for Advanced Tech Evaluation Seeks Wider HPC Community Ties

September 21, 2017

Two years ago the Department of Energy established the Center for Advanced Technology Evaluation (CENATE) at Pacific Northwest National Laboratory (PNNL). CENAT Read more…

By John Russell

Exascale Computing Project Names Doug Kothe as Director

September 20, 2017

The Department of Energy’s Exascale Computing Project (ECP) has named Doug Kothe as its new director effective October 1. He replaces Paul Messina, who is stepping down after two years to return to Argonne National Laboratory. Kothe is a 32-year veteran of DOE’s National Laboratory System. Read more…

Takeaways from the Milwaukee HPC User Forum

September 19, 2017

Milwaukee’s elegant Pfister Hotel hosted approximately 100 attendees for the 66th HPC User Forum (September 5-7, 2017). In the original home city of Pabst Blu Read more…

By Merle Giles

Kathy Yelick Charts the Promise and Progress of Exascale Science

September 15, 2017

On Friday, Sept. 8, Kathy Yelick of Lawrence Berkeley National Laboratory and the University of California, Berkeley, delivered the keynote address on “Breakthrough Science at the Exascale” at the ACM Europe Conference in Barcelona. In conjunction with her presentation, Yelick agreed to a short Q&A discussion with HPCwire. Read more…

By Tiffany Trader

DARPA Pledges Another $300 Million for Post-Moore’s Readiness

September 14, 2017

The Defense Advanced Research Projects Agency (DARPA) launched a giant funding effort to ensure the United States can sustain the pace of electronic innovation vital to both a flourishing economy and a secure military. Under the banner of the Electronics Resurgence Initiative (ERI), some $500-$800 million will be invested in post-Moore’s Law technologies. Read more…

By Tiffany Trader

IBM Breaks Ground for Complex Quantum Chemistry

September 14, 2017

IBM has reported the use of a novel algorithm to simulate BeH2 (beryllium-hydride) on a quantum computer. This is the largest molecule so far simulated on a quantum computer. The technique, which used six qubits of a seven-qubit system, is an important step forward and may suggest an approach to simulating ever larger molecules. Read more…

By John Russell

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

NERSC Scales Scientific Deep Learning to 15 Petaflops

August 28, 2017

A collaborative effort between Intel, NERSC and Stanford has delivered the first 15-petaflops deep learning software running on HPC platforms and is, according Read more…

By Rob Farber

Russian Researchers Claim First Quantum-Safe Blockchain

May 25, 2017

The Russian Quantum Center today announced it has overcome the threat of quantum cryptography by creating the first quantum-safe blockchain, securing cryptocurrencies like Bitcoin, along with classified government communications and other sensitive digital transfers. Read more…

By Doug Black

Oracle Layoffs Reportedly Hit SPARC and Solaris Hard

September 7, 2017

Oracle’s latest layoffs have many wondering if this is the end of the line for the SPARC processor and Solaris OS development. As reported by multiple sources Read more…

By John Russell

Six Exascale PathForward Vendors Selected; DoE Providing $258M

June 15, 2017

The much-anticipated PathForward awards for hardware R&D in support of the Exascale Computing Project were announced today with six vendors selected – AMD Read more…

By John Russell

Google Debuts TPU v2 and will Add to Google Cloud

May 25, 2017

Not long after stirring attention in the deep learning/AI community by revealing the details of its Tensor Processing Unit (TPU), Google last week announced the Read more…

By John Russell

Top500 Results: Latest List Trends and What’s in Store

June 19, 2017

Greetings from Frankfurt and the 2017 International Supercomputing Conference where the latest Top500 list has just been revealed. Although there were no major Read more…

By Tiffany Trader

Leading Solution Providers

IBM Clears Path to 5nm with Silicon Nanosheets

June 5, 2017

Two years since announcing the industry’s first 7nm node test chip, IBM and its research alliance partners GlobalFoundries and Samsung have developed a proces Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in Read more…

By Tiffany Trader

Google Releases Deeplearn.js to Further Democratize Machine Learning

August 17, 2017

Spreading the use of machine learning tools is one of the goals of Google’s PAIR (People + AI Research) initiative, which was introduced in early July. Last w Read more…

By John Russell

EU Funds 20 Million Euro ARM+FPGA Exascale Project

September 7, 2017

At the Barcelona Supercomputer Centre on Wednesday (Sept. 6), 16 partners gathered to launch the EuroEXA project, which invests €20 million over three-and-a-half years into exascale-focused research and development. Led by the Horizon 2020 program, EuroEXA picks up the banner of a triad of partner projects — ExaNeSt, EcoScale and ExaNoDe — building on their work... Read more…

By Tiffany Trader

Amazon Debuts New AMD-based GPU Instances for Graphics Acceleration

September 12, 2017

Last week Amazon Web Services (AWS) streaming service, AppStream 2.0, introduced a new GPU instance called Graphics Design intended to accelerate graphics. The Read more…

By John Russell

Cray Moves to Acquire the Seagate ClusterStor Line

July 28, 2017

This week Cray announced that it is picking up Seagate's ClusterStor HPC storage array business for an undisclosed sum. "In short we're effectively transitioning the bulk of the ClusterStor product line to Cray," said CEO Peter Ungaro. Read more…

By Tiffany Trader

GlobalFoundries: 7nm Chips Coming in 2018, EUV in 2019

June 13, 2017

GlobalFoundries has formally announced that its 7nm technology is ready for customer engagement with product tape outs expected for the first half of 2018. The Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This