A heterogeneous approach to solving big data analytics graph problems

By Nicole Hemsoth

April 9, 2012

Today’s commodity servers, as well as systems designed specifically for numerically intensive algorithms (“supercomputers”), are ill suited for many applications in the world of big data analytics. Such applications often use graph manipulation algorithms and data structures, and are best addressed by architectural extensions not found in commodity systems. Convey Computer Corporation’s hybrid-core system takes a heterogeneous approach to solving graph-type problems, and the resulting performance is characterized by results on the Graph500 Benchmark (www.graph500.org). Let’s take a look at architectural features that accelerate graph problems, and how Convey has implemented these features in its reconfigurable computing system.

Big Data Analytics and Graph Algorithms

Many analytics applications utilize graph algorithms and data structures to allow discovery of relationships between data elements in a large database. Generally, modeling these relationships in software and hardware is “reasonably” easy. (Let’s say the core graph manipulation algorithms are fairly easy, the implementation as it pertains to a several petabyte database may not be so easy!) Data structures can be constructed that contain information about specific nodes in a graph, connections and relationships to other nodes, and so on.

Certainly graph problems aren’t new. However, using graph algorithms to traverse graphs that have billions of nodes and edges and require many terabytes of storage is new (and “different”). And computer architectures that effectively execute these algorithms are also new; as the National Science Foundation states: “Data intensive computing demands a fundamentally different set of principles than mainstream computing.” [1]

Desirable architectural features

What types of architectural features are desirable in a computer system that executes graph algorithms? Following are some of the features that can give the most performance for the least cost/space/power:

Balance between compute elements and memory subsystem performance. Most data-intensive problems require minimal compute resources (especially in terms of floating operations), and require more memory subsystem performance. Ideally, as in a reconfigurable or hybrid-core computing system, the compute elements can be changed on the fly to adapt to the application’s compute needs.

High bandwidth, highly parallel memory subsystem. Attainable memory bandwidth (not peak) should be as high as possible. In addition, many thousands of simultaneous outstanding requests should be supported to support parallelism and mitigate latency.

Massive multi-threaded capability. A combination of compute and memory requirements, the ability to support tens or hundreds of thousands of concurrent execution threads is desirable. More parallelism reduces time-to-answer, improves hardware utilization, and increases efficiency.

Hardware-based synchronization primitives. With high degrees of parallelism comes the challenge of synchronizing read/write access to memory locations. Data integrity demands that a read-modify-write operation to a memory location is an indivisible operation. When the synchronization mechanism is “further away” from the operation, more time is spent waiting for the synchronization, with a corresponding reduction in efficiency of parallelization. Ideally, synchronization is implemented in hardware in the memory subsystem.

[1] http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=503324&org=IIS

The Graph 500 benchmark

Recognizing the need for a benchmark suite that will more accurately measure performance on graph-type problems, a steering committee of HPC experts from academia, industry, and national laboratories created the Graph500 benchmark. Currently the benchmark constructs an undirected graph and measures the performance of a kernel that executes a breadth-first search of graph.[2][3]

The kernel of the breadth-first search portion of the benchmark (Figure 2) contains multiple constructs that are common to many graph-type algorithms—specifically a high degree of parallelism, and indirect (or “vector of indices”) memory references.

 Convey Fig. 2

Figure 2. The kernel of the breadth-first search algorithm extracted from the graph500 release code.


Hybrid-core computing and the Graph 500 benchmark

The Convey hybrid-core systems offer a balanced architecture: reconfigurable compute elements (via Field Programmable Gate Arrays—FPGAs), and a supercomputing-inspired memory subsystem (Figure 3).

Convey Fig. 3


Figure 3. Overview of the Convey hybrid-core computing architecture.

[2] http://www.graph500.org/index.html
[3] http://en.wikipedia.org/wiki/Breadth-first_search

The benefit of hybrid-core computing is that the compute-intensive kernel of the Graph500 breadth-first search is implemented in hardware on the FPGAs in the coprocessor. The FPGA implementation allows much more parallelism than a commodity system (the Convey memory subsystem allows up to 8,192 outstanding concurrent memory references). The increase in parallelism combined with the hardware implementation of the logic portions of the algorithm allow for increased overall performance with much less hardware.

In addition to increased parallelism, the memory subsystem of the Convey systems is specifically designed to provide high bandwidth for parallel references that exhibit poor locality (e.g. offers high performance for random accesses). Thus, the vector of indices portion of the code is highly accelerated over architectures that are not well suited for random accesses.

Performance results

The architecture of the Convey hybrid-core systems lends itself exceedingly well to the Graph500 benchmark (Figure 4). While the problem size is considered “small” (which is understandable, given that the benchmark is run on a single node system), the performance-per-watt and performance-per-dollar are well beyond any other system on the list.

Figure 4 is a partial list (problem scale 28-31) of the performance results for the November 2011 release of the Graph500 benchmark. Approximate power requirements allow for an arbitrary metric illustrating power efficiency (MTEPS/kw).

Convey Fig. 4


Figure 4. Performance and power on the Graph500 benchmark (for problem size 28-31).[4]


The massive explosion of data available for analysis and understanding is creating a “whole new dimension to HPC,” with demands on existing HPC architectures that cannot be fulfilled by current commodity systems.  Future generations of HPC systems will be required to acknowledge some of the architectural requirements of data-intensive algorithms. For example, memory subsystems will need to increase effective bandwidth, more parallelism will be needed, and synchronization primitives will need to be “closer” to the memory subsystem.

By implementing a balanced, hybrid approach, Convey’s hybrid-core family of systems are able to execute problems in the data-intensive sciences much more effectively. The hybrid-core architecture is poised for exascale levels of computing in the data-intensive sciences because it offers reconfigurable compute elements balanced with a supercomputer-inspired memory subsystem.


[4] One entry was removed (#17) because it employed a different BFS algorithm.

For more information, please see http://www.conveycomputer.com/sc11/

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

SC17 Student Cluster Competition Configurations: Fewer Nodes, Way More Accelerators

November 16, 2017

The final configurations for each of the SC17 “Donnybrook in Denver” Student Cluster Competition have been released. Fortunately, each team received their equipment shipments on time and undamaged, so the teams are r Read more…

By Dan Olds

Student Clusterers Demolish HPCG Record! Nanyang Sweeps Benchmarks

November 16, 2017

Nanyang pulled off the always difficult double-play at this year’s SC Student Cluster Competition. The plucky team from Singapore posted a world record LINPACK, thus taking the Highest LINPACK Award, but also managed t Read more…

By Dan Olds

Student Cluster LINPACK Record Shattered! More LINs Packed Than Ever before!

November 16, 2017

Nanyang Technological University, the pride of Singapore, utterly destroyed the Student Cluster Competition LINPACK record by posting a score of 51.77 TFlop/s at SC17 in Denver. The previous record, established by German Read more…

By Dan Olds

HPE Extreme Performance Solutions

Harness Scalable Petabyte Storage with HPE Apollo 4510 and HPE StoreEver

As a growing number of connected devices challenges IT departments to rapidly collect, manage, and store troves of data, organizations must adopt a new generation of IT to help them operate quickly and intelligently. Read more…

Hyperion Market Update: ‘Decent’ Growth Led by HPE; AI Transparency a Risk Issue

November 15, 2017

The HPC market update from Hyperion Research (formerly IDC) at the annual SC conference is a business and social “must,” and this year’s presentation at SC17 played to a SRO crowd at a downtown Denver hotel. This w Read more…

By Doug Black

Student Cluster LINPACK Record Shattered! More LINs Packed Than Ever before!

November 16, 2017

Nanyang Technological University, the pride of Singapore, utterly destroyed the Student Cluster Competition LINPACK record by posting a score of 51.77 TFlop/s a Read more…

By Dan Olds

Hyperion Market Update: ‘Decent’ Growth Led by HPE; AI Transparency a Risk Issue

November 15, 2017

The HPC market update from Hyperion Research (formerly IDC) at the annual SC conference is a business and social “must,” and this year’s presentation at S Read more…

By Doug Black

Nvidia Focuses Its Cloud Containers on HPC Applications

November 14, 2017

Having migrated its top-of-the-line datacenter GPU to the largest cloud vendors, Nvidia is touting its Volta architecture for a range of scientific computing ta Read more…

By George Leopold

HPE Launches ARM-based Apollo System for HPC, AI

November 14, 2017

HPE doubled down on its memory-driven computing vision while expanding its processor portfolio with the announcement yesterday of the company’s first ARM-base Read more…

By Doug Black

OpenACC Shines in Global Climate/Weather Codes

November 14, 2017

OpenACC, the directive-based parallel programming model used mostly for porting codes to GPUs for use on heterogeneous systems, came to SC17 touting impressive Read more…

By John Russell

Flipping the Flops and Reading the Top500 Tea Leaves

November 13, 2017

The 50th edition of the Top500 list, the biannual publication of the world’s fastest supercomputers based on public Linpack benchmarking results, was released Read more…

By Tiffany Trader

Tensors Come of Age: Why the AI Revolution Will Help HPC

November 13, 2017

Thirty years ago, parallel computing was coming of age. A bitter battle began between stalwart vector computing supporters and advocates of various approaches to parallel computing. IBM skeptic Alan Karp, reacting to announcements of nCUBE’s 1024-microprocessor system and Thinking Machines’ 65,536-element array, made a public $100 wager that no one could get a parallel speedup of over 200 on real HPC workloads. Read more…

By John Gustafson & Lenore Mullin

AMD Showcases Growing Portfolio of EPYC and Radeon-based Systems at SC17

November 13, 2017

AMD’s charge back into HPC and the datacenter is on full display at SC17. Having launched the EPYC processor line in June along with its MI25 GPU the focus he Read more…

By John Russell

US Coalesces Plans for First Exascale Supercomputer: Aurora in 2021

September 27, 2017

At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, in Arlington, Va., yesterday (Sept. 26), it was revealed that the "Aurora" supercompute Read more…

By Tiffany Trader

NERSC Scales Scientific Deep Learning to 15 Petaflops

August 28, 2017

A collaborative effort between Intel, NERSC and Stanford has delivered the first 15-petaflops deep learning software running on HPC platforms and is, according Read more…

By Rob Farber

Oracle Layoffs Reportedly Hit SPARC and Solaris Hard

September 7, 2017

Oracle’s latest layoffs have many wondering if this is the end of the line for the SPARC processor and Solaris OS development. As reported by multiple sources Read more…

By John Russell

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Google Releases Deeplearn.js to Further Democratize Machine Learning

August 17, 2017

Spreading the use of machine learning tools is one of the goals of Google’s PAIR (People + AI Research) initiative, which was introduced in early July. Last w Read more…

By John Russell

GlobalFoundries Puts Wind in AMD’s Sails with 12nm FinFET

September 24, 2017

From its annual tech conference last week (Sept. 20), where GlobalFoundries welcomed more than 600 semiconductor professionals (reaching the Santa Clara venue Read more…

By Tiffany Trader

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in Read more…

By Tiffany Trader

Amazon Debuts New AMD-based GPU Instances for Graphics Acceleration

September 12, 2017

Last week Amazon Web Services (AWS) streaming service, AppStream 2.0, introduced a new GPU instance called Graphics Design intended to accelerate graphics. The Read more…

By John Russell

Leading Solution Providers

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

EU Funds 20 Million Euro ARM+FPGA Exascale Project

September 7, 2017

At the Barcelona Supercomputer Centre on Wednesday (Sept. 6), 16 partners gathered to launch the EuroEXA project, which invests €20 million over three-and-a-half years into exascale-focused research and development. Led by the Horizon 2020 program, EuroEXA picks up the banner of a triad of partner projects — ExaNeSt, EcoScale and ExaNoDe — building on their work... Read more…

By Tiffany Trader

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Cray Moves to Acquire the Seagate ClusterStor Line

July 28, 2017

This week Cray announced that it is picking up Seagate's ClusterStor HPC storage array business for an undisclosed sum. "In short we're effectively transitioning the bulk of the ClusterStor product line to Cray," said CEO Peter Ungaro. Read more…

By Tiffany Trader

Intel Launches Software Tools to Ease FPGA Programming

September 5, 2017

Field Programmable Gate Arrays (FPGAs) have a reputation for being difficult to program, requiring expertise in specialty languages, like Verilog or VHDL. Easin Read more…

By Tiffany Trader

HPC Chips – A Veritable Smorgasbord?

October 10, 2017

For the first time since AMD's ill-fated launch of Bulldozer the answer to the question, 'Which CPU will be in my next HPC system?' doesn't have to be 'Whichever variety of Intel Xeon E5 they are selling when we procure'. Read more…

By Dairsie Latimer

IBM Advances Web-based Quantum Programming

September 5, 2017

IBM Research is pairing its Jupyter-based Data Science Experience notebook environment with its cloud-based quantum computer, IBM Q, in hopes of encouraging a new class of entrepreneurial user to solve intractable problems that even exceed the capabilities of the best AI systems. Read more…

By Alex Woodie

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This