A New Breed of Heterogeneous Computing

By Michael Feldman

April 18, 2012

With the introduction of add-on accelerators like GPUs, Intel’s upcoming MIC chip, and, to a lesser extent, FPGAs, the foundation of high performance computing is undergoing somewhat of a revolution. But an emerging variant of this heterogenous computing approach may upend the current accelerator model in the not-too-distant future. And it’s already begun in the mobile space.

In October 2011, ARM announced their “big.LITTLE” design, a chip architecture than integrates large, performant ARM cores with small, power-efficient ones. The goal of this approach is to minimize power draw in order to extend the battery life of devices like smartphones and tablets.

The way it works is by mapping an application to the optimal cores based on performance demands and power availability. For mobile devices, big cores would be used for performance-demanding tasks like navigation and gaming, and the smaller cores for the OS and simpler tasks like social media apps. But when the battery runs low, the software can shunt everything to the low power cores in order the keep the device operational. ARM is claiming that battery life can be extended by as much as 70 percent by migrating tasks intelligently.

ARM’s first incarnation of big.LITTLE pairs its large Cortex-A15 design with the smaller Cortex-A7, along with glue technology to provide cache and I/O coherency between the two sets of cores. Companies like Samsung, Freescale, and Texas Instruments, among others, are already signing up.

ARM didn’t invent the big core/little core concept though. This model has been kicked around in the research community for nearly a decade. One of the first papers on the subject was written in 2003 by Rakesh Kumar, along with colleagues at UCSD and HP Labs. He proposed a single-ISA heterogenous multicore design, but in this case based on the Alpha microprocessors, a CPU line that, at the time, was being targeted to high-end workstations and servers.

He found that a chip with four different Alpha core microarchitectures had the potential to “increase energy efficiency by a factor of three… without dramatic losses in performance.” He also discovered that most of these gains would be possible with as little as two types of cores.

In a recent conversation with Kumar, he expressed the notion that the time may be ripe for single-ISA heterogeneous chips to find a home in the server arena, even in high performance computing. The driver, once again, is power, or the lack thereof. As server farms and supercomputers expand in size, electricity usage has become a limiting factor. Whether you’re scaling up or scaling out, everyone is now focused on more energy-efficient computers.

“The key insight was that even if you map an application to a little core, it’s not going to perform much worse than running it on a big core,” said Kumar, referring to his earlier research. “But you can save many factors of power.”

The problem with big powerful CPUs like the Xeon, Opteron, and Power is now well known. Although Moore’ Law is still working to expand transistor budgets at a good clip, clock frequencies are stagnant. That means performance and, especially, performance-per-watt are increasing more slowly. For these high-end server chips, essentially you have to spend four units of power to deliver one unit of performance on a per core basis.

That’s a result of the superscalar nature of these big-core microarchitectures, which feature a lot of instruction level parallelism (ILP) and deep pipelines. Such a design reduces execution latency, but at a hefty price in wattage. As Kumar explains it, “It takes a lot of power and a lot of [die] area to squeeze that last 5 to 10 percent of performance.”

The implication is to just switch to smaller, power-efficient cores, with simpler pipelines and less ILP. If you can parallelize an application across many smaller, simpler cores, you get the best of both worlds: better throughput and higher energy efficiency. The problem is that for many applications, decent performance is contingent upon single-threaded performance as well. That has led to the adoption of the types of accelerator-based computing platforms mentioned at the beginning of this article, which pairs a serial CPU chip with a throughput coprocessor.

What the big/little model brings to the table is having both types of cores on the same die. And perhaps more importantly, unlike the CPU-GPU integration that AMD is doing with their Fusion chips and what NVIDIA is planning to do with their “Project Denver” platform, the big/little model consolidates on a homogeneous instruction set.

That has a number of advantages, one of which is easier software development. With a common ISA, there is no need for a complex toolchain with multiple compilers, runtimes, libraries, and debuggers that are needed to deal with two sets of architectures. For supercomputing-type applications though, writing the application is likely to remain challenging, inasmuch as the developer still has to parallelize the code as well as explicitly map the serial work and throughput work to the appropriate cores. Unlike with mobile computing, for HPC, assigning tasks to cores would be more static, since maximizing throughput is the overriding goal.

But where performance has to be compromised because of power or resource constraints, a single ISA chip is a huge advantage. So at run-time, application threads can migrate across the different microarchitectures, as needed, to optimize for throughput, power or both. And since the cores share cache and memory, suspending a thread on one core and resuming it on another is a relatively quick and painless operation.

So, for example, a render server farm equipped with big/little CPUs could shuffle application threads to faster or slower cores depending up the workload mix, available processor resources, and the turnaround time required. If a service level agreement (SLA) was in effect that allowed the rendering job to meet its deadline without maxing out on the big cores, the server farm could save on its electricity bill by utilizing more of the little cores.

It should be noted that power savings can also be achieved by varying a microprocessor’s power supply voltage and clock frequency, otherwise know as voltage/frequency scaling. But as transistor geometries shrink, this technique tends to yield diminishing returns. And as even Intel has concluded, big/little cores — Intel calls them asymmetric cores — seem to deliver the best results.

The most likely architectures to adopt the big/little paradigm over the next few years are x86 and ARM. As mentioned before ARM big.LITTLE implementations are already in the works for mobile computing, but with the unveiling of the 64-bit ARM architecture last year, and with companies like HP delving into ARM-based gear for the datacenter, big/little implementations of ARM servers could appear as early as the middle of this decade.

We may see x86-based big/little server chips even sooner. Intel, in particular, is in prime position to take advantage of this technology. For one thing, the chipmaker is the best in the business at transistor shrinking, which is an important element if you’re interested in populating a die with a useful number of big and little cores. It also has a huge stable of x86 cores designs, from the Atom chip all the way up to the Xeon.

Also, since Intel has little in the way of GPU IP that can be used for computing, the company is most likely to rely on its x86 legacy for throughput cores. For example, it’s not too hard to imagine Intel’s big-core Xeon paired up with its little-core MIC chip in a future SoC geared for HPC duty. The same model, but with a different mix of x86 microarchitectures, could also be used to build more generic enterprise server processors, not to mention its own mobile chips.

Whether Intel intends to go down this path or not remains to be seen. But a recent patent the company filed regarding mixing asymmetric x86 cores in a processor suggests the chipmaker has indeed given serious thought to big/little products. And since both AMD and NVIDIA are pursing their own heterogeneous SoCs, which by the way could also incorporated this technology, Intel is not likely cede any advantage to its competitors.

The big/little approach won’t be a panacea for energy-efficient computing, but it looks like one of the most promising approaches, at least at the level of the CPU. The fact that it incorporates the advantages of a heterogeneous architecture, but with a simpler model, has much to recommend it. And while big/little CPUs may be seen as somewhat of a threat to GPU computing, it can also be viewed as a complementary technology. What is certain is that the days of one-size-fits-all architectures are coming to a close.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Geospatial Data Research Leverages GPUs

August 17, 2017

MapD Technologies, the GPU-accelerated database specialist, said it is working with university researchers on leveraging graphics processors to advance geospatial analytics. The San Francisco-based company is collabor Read more…

By George Leopold

Intel, NERSC and University Partners Launch New Big Data Center

August 17, 2017

A collaboration between the Department of Energy’s National Energy Research Scientific Computing Center (NERSC), Intel and five Intel Parallel Computing Centers (IPCCs) has resulted in a new Big Data Center (BDC) that Read more…

By Linda Barney

Google Releases Deeplearn.js to Further Democratize Machine Learning

August 17, 2017

Spreading the use of machine learning tools is one of the goals of Google’s PAIR (People + AI Research) initiative, which was introduced in early July. Last week the cloud giant released deeplearn.js as part of that in Read more…

By John Russell

HPE Extreme Performance Solutions

Leveraging Deep Learning for Fraud Detection

Advancements in computing technologies and the expanding use of e-commerce platforms have dramatically increased the risk of fraud for financial services companies and their customers. Read more…

Spoiler Alert: Glimpse Next Week’s Solar Eclipse Via Simulation from TACC, SDSC, and NASA

August 17, 2017

Can’t wait to see next week’s solar eclipse? You can at least catch glimpses of what scientists expect it will look like. A team from Predictive Science Inc. (PSI), based in San Diego, working with Stampede2 at the Read more…

By John Russell

Microsoft Bolsters Azure With Cloud HPC Deal

August 15, 2017

Microsoft has acquired cloud computing software vendor Cycle Computing in a move designed to bring orchestration tools along with high-end computing access capabilities to the cloud. Terms of the acquisition were not disclosed. Read more…

By George Leopold

HPE Ships Supercomputer to Space Station, Final Destination Mars

August 14, 2017

With a manned mission to Mars on the horizon, the demand for space-based supercomputing is at hand. Today HPE and NASA sent the first off-the-shelf HPC system i Read more…

By Tiffany Trader

AMD EPYC Video Takes Aim at Intel’s Broadwell

August 14, 2017

Let the benchmarking begin. Last week, AMD posted a YouTube video in which one of its EPYC-based systems outperformed a ‘comparable’ Intel Broadwell-based s Read more…

By John Russell

Deep Learning Thrives in Cancer Moonshot

August 8, 2017

The U.S. War on Cancer, certainly a worthy cause, is a collection of programs stretching back more than 40 years and abiding under many banners. The latest is t Read more…

By John Russell

IBM Raises the Bar for Distributed Deep Learning

August 8, 2017

IBM is announcing today an enhancement to its PowerAI software platform aimed at facilitating the practical scaling of AI models on today’s fastest GPUs. Scal Read more…

By Tiffany Trader

IBM Storage Breakthrough Paves Way for 330TB Tape Cartridges

August 3, 2017

IBM announced yesterday a new record for magnetic tape storage that it says will keep tape storage density on a Moore's law-like path far into the next decade. Read more…

By Tiffany Trader

AMD Stuffs a Petaflops of Machine Intelligence into 20-Node Rack

August 1, 2017

With its Radeon “Vega” Instinct datacenter GPUs and EPYC “Naples” server chips entering the market this summer, AMD has positioned itself for a two-head Read more…

By Tiffany Trader

Cray Moves to Acquire the Seagate ClusterStor Line

July 28, 2017

This week Cray announced that it is picking up Seagate's ClusterStor HPC storage array business for an undisclosed sum. "In short we're effectively transitioning the bulk of the ClusterStor product line to Cray," said CEO Peter Ungaro. Read more…

By Tiffany Trader

Nvidia’s Mammoth Volta GPU Aims High for AI, HPC

May 10, 2017

At Nvidia's GPU Technology Conference (GTC17) in San Jose, Calif., this morning, CEO Jensen Huang announced the company's much-anticipated Volta architecture a Read more…

By Tiffany Trader

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

Quantum Bits: D-Wave and VW; Google Quantum Lab; IBM Expands Access

March 21, 2017

For a technology that’s usually characterized as far off and in a distant galaxy, quantum computing has been steadily picking up steam. Just how close real-wo Read more…

By John Russell

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Russian Researchers Claim First Quantum-Safe Blockchain

May 25, 2017

The Russian Quantum Center today announced it has overcome the threat of quantum cryptography by creating the first quantum-safe blockchain, securing cryptocurrencies like Bitcoin, along with classified government communications and other sensitive digital transfers. Read more…

By Doug Black

HPC Compiler Company PathScale Seeks Life Raft

March 23, 2017

HPCwire has learned that HPC compiler company PathScale has fallen on difficult times and is asking the community for help or actively seeking a buyer for its a Read more…

By Tiffany Trader

Trump Budget Targets NIH, DOE, and EPA; No Mention of NSF

March 16, 2017

President Trump’s proposed U.S. fiscal 2018 budget issued today sharply cuts science spending while bolstering military spending as he promised during the cam Read more…

By John Russell

Leading Solution Providers

Groq This: New AI Chips to Give GPUs a Run for Deep Learning Money

April 24, 2017

CPUs and GPUs, move over. Thanks to recent revelations surrounding Google’s new Tensor Processing Unit (TPU), the computing world appears to be on the cusp of Read more…

By Alex Woodie

CPU-based Visualization Positions for Exascale Supercomputing

March 16, 2017

In this contributed perspective piece, Intel’s Jim Jeffers makes the case that CPU-based visualization is now widely adopted and as such is no longer a contrarian view, but is rather an exascale requirement. Read more…

By Jim Jeffers, Principal Engineer and Engineering Leader, Intel

Google Debuts TPU v2 and will Add to Google Cloud

May 25, 2017

Not long after stirring attention in the deep learning/AI community by revealing the details of its Tensor Processing Unit (TPU), Google last week announced the Read more…

By John Russell

MIT Mathematician Spins Up 220,000-Core Google Compute Cluster

April 21, 2017

On Thursday, Google announced that MIT math professor and computational number theorist Andrew V. Sutherland had set a record for the largest Google Compute Engine (GCE) job. Sutherland ran the massive mathematics workload on 220,000 GCE cores using preemptible virtual machine instances. Read more…

By Tiffany Trader

Six Exascale PathForward Vendors Selected; DoE Providing $258M

June 15, 2017

The much-anticipated PathForward awards for hardware R&D in support of the Exascale Computing Project were announced today with six vendors selected – AMD Read more…

By John Russell

Top500 Results: Latest List Trends and What’s in Store

June 19, 2017

Greetings from Frankfurt and the 2017 International Supercomputing Conference where the latest Top500 list has just been revealed. Although there were no major Read more…

By Tiffany Trader

IBM Clears Path to 5nm with Silicon Nanosheets

June 5, 2017

Two years since announcing the industry’s first 7nm node test chip, IBM and its research alliance partners GlobalFoundries and Samsung have developed a proces Read more…

By Tiffany Trader

Messina Update: The US Path to Exascale in 16 Slides

April 26, 2017

Paul Messina, director of the U.S. Exascale Computing Project, provided a wide-ranging review of ECP’s evolving plans last week at the HPC User Forum. Read more…

By John Russell

  • arrow
  • Click Here for More Headlines
  • arrow
Share This