Convey Cranks Up Performance with Latest FPGA-Accelerated Computer

By Michael Feldman

April 24, 2012

Convey Computer has launched its newest x86-FPGA “hybrid-core” server. Dubbed HC-2, it represents the first major upgrade of the system since the company introduced the HC-1 product back in 2008. The new offering promises much better performance, but with a similar price range as the original system.

The new HC-2 keeps the basic architecture Convey established with the HC-1 of an x86 host glued to a custom-wrapped FPGA board that acts as a coprocessor. Like its predecessor, the HC-2 is not a flops machine. The FPGA-based coprocessor is designed to accelerate data-intensive workloads like genome sequence alignment and other types of data mining workloads. The coprocessor memory subsystem is built like that of a vector supercomputer, able to deliver reads and write at much higher bandwidth than that of a standard commodity server.

Although there are some important hardware tweaks with the HC-2, binary compatibility has been retained so that software developed for the original HC-1 platform can execute as is on the new platform. As before, the coprocessor subsystem is tapped into via Convey-supplied libraries and tools, which allows the user to build (or reuse) customized application-specific instruction for accelerating codes. And since the platform is essentially an x86 Linux server, standard HPC software, like MPI or a workload manager, runs on the platform transparently.

Hardware-wise, most of the HC-2 upgrades are on the host side, where Convey has swapped out the older Intel Xeon X5400 (“Harpertown) used on the HC-1 with CPUs of more recent vintage, namely the Xeon X5600 (“Westmere”) and Xeon E5-2600 (“Sandy Bridge”) processors. The Westmere-based hardware will employ the 6-core X5690 CPU running at 2.93 GHz, while the Sandy Bridge-based servers will come in two basic flavors, 4-core and 8-core, but offered at clock speeds ranging from 2.4 to 3.3 GHz. The coprocessor will use the same Xilinx FPGAs present in the HC-1: Virtex-5 for the baseline server and Virtex-6 for the more performant “ex” variant.

Memory capacity is quite a bit higher on the new servers too. The Westmere-based system can reach up to 192 GB, which is a nice bump from the 128 GB limit on the HC-1 gear. Thanks to the new Sandy Bridge design, though, servers equipped with those CPUs can be outfitted with as much as 768 GB of memory. The memory capacity on the FPGA coprocessor board memory will top out at 64 GB, the same as it was on the HC-1.

I/O has been kicked up as well. Instead of just a single Gen 2 PCIe port, a SATA interface, 1 to 3 hot swap SATA drives, and an IDE optical drive, the newer servers sport up to 8 SATA drives, 2 Intel I/O modules slots, and 5 PCIe Gen 3 ports (although not all these options are available in all configurations).  Since these are essentially data-crunching machines, the extra I/O support should be much appreciated.

The biggest design change was a result of the Westmere/Sandy Bridge CPU upgrade. This forced the Convey engineers to make a decision about the host-coprocessor interconnect, which on the Harpertown-equipped HC-1 was based on Intel’s Front-Side Bus (FSB). Since Harpertown was the last FSB-based Xeon chip, with all subsequent design using the new QuickPath Interconnect (QPI), Convey had to go either stay native and build a QPI-based system or use PCIe. They opted for the latter, which, given that PCIe is an industry standard, gave them the most flexibility going forward.

Moving to PCIe also freed up a CPU socket that was taken up by the coprocessor interface under the FSB scheme. Thus the HC-2 servers can all be dual-socket servers instead of the single-socket systems of the HC-1. That’s a fortuitous development since, according to Convey CEO Bruce Toal, there was somewhat of an imbalance in the original design.

In particular, with only a single dual- or quad-core Xeon in the HC-1, in some cases there wasn’t enough x86 performance to keep up with a fully outfitted four-FPGA coprocessor, whilst simultaneously handling I/O. Now with the extra CPU on the freed socket (not to mention the more numerous cores of Westmere and Sandy Bridge), the host has a lot more cycles available to it to feed the coprocessor and I/O devices.

The company is claiming a 2- to 3-fold improvement in application performance for the HC-2 compared to the original HC-1 and a 10- to 50-fold performance boost compared to a vanilla x86 server. For example, a 12-core x86 server running a genome sequence application using the Burrows-Wheeler Aligner (BWA) algorithm can align a little over 7 thousand sequences per second. Even the older generation HC-1ex managed 27 thousand alignments per second, but with the new HC-2ex gear, that goes up to over 66 thousand alignments. A similar performance boost has been demonstrated with BLAST, the Basic Local Alignment Search Tool.

As impressive as that is, the energy efficiency of the new system is equally noteworthy. While the highest performing Sandy Bridge CPU-based servers will require an 1800 watt power supply, the majority of the HC-2 configurations will fit into a 1570 watt box. That’s only a marginally higher than the 1520 watt power supply on the original top-of-the line HC-1ex, but since the new version is promising to be at least twice as fast, performance-per-watt has improved substantially.

That plays into one of Convey’s main pitches for their hybrid-core solution: reducing the total cost of ownership (TCO). And if these HC-2 performance and power numbers hold up, that story just got better. The company says for a typical bioinformatics application you only need about 1/15 the number of HC-2ex nodes compared running the same job on a standard x86 (dual-socket Westmere) cluster. Although each Convey node is going to draw more power than a commodity server, it still works out to 83 percent less power overall for a given amount of application throughput. Likewise, datacenter floor space is just a fraction of what would be needed for an all-x86 setup. Overall, Convey estimates a three-year TCO savings of 75 percent.

Toal says it’s a bit easier to convince commercial users of the TCO advantages, since they are more sensitive to datacenter operations costs than their academic counterparts. In research environments, the electricity bill is typically paid by the institution, so these users tend to be less concerned about energy efficiency. “You have to find the guy that owns the power budget,” says Toal.

Nevertheless, a good chunk of Convey’s business is done with non-commercial customers across all their four principle application domains: bioinformatics, government, telco, and research. Not surprisingly for an FPGA-based solution, bioinformatics is the biggest vertical, which, according to Toal, represents 36 percent of their shipments. Government, which includes a lot of classified apps (think national security-type data mining) and defense work, is second at 21 percent. The research space proper, which is centered on deployments at DOE national labs like Oak Ridge and Lawrence Berkeley National Labs, is 18 percent of the business. Lastly is the telco market, which represents 17 percent of Convey’s shipments.

System pricing on the new HC-2 offerings are in line with the HC-1 products. A Westmere-based HC-2 server with a minimal configuration begins at $40,000; the corresponding Sandy Bridge box starts at $41K. Adding faster processors and more memory will kick up the price accordingly. The Westmere-based servers are already available and have been shipping for some time, including one deployment at Jackson Laboratory (JAX), in Maine. The Sandy Bridge gear won’t be available until July.

Related Articles

Convey Bends to Inflection Point

Convey Debuts Second-Generation Hybrid-Core Platform

Startup Provides a New Twist on Reconfigurable Supercomputing

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