Novel Chip Technology to Power GRAPE-8 Supercomputer

By Michael Feldman

May 10, 2012

With the fastest supercomputers on the planet sporting multi-megawatt appetites, green HPC has become all the rage. The IBM Blue Gene/Q machine is currently number one in energy-efficient flops, but a new FPGA-like technology brought to market by semiconductor startup eASIC is providing an even greener computing solution. And one HPC project in Japan, known as GRAPE, is using the chips to power its newest supercomputer.

GRAPE, which stands for Gravity Pipe, is a Japanese computing project that is focused on astrophysical simulation. (More specifically, the application uses Newtonian physics to compute the interaction of particles in N-body systems). The project, which began in 1989, has gone through eight generations of hardware, all of which were built as special-purpose supercomputer systems.

Each of the GRAPE machines was powered by a custom-built chip, specifically designed to optimize the astrophysical calculations that form the basis of the simulation work. The special-purpose processors were hooked up as external accelerators, using more conventional CPU-based host systems, in the form or workstations or servers, to drive the application.

The first-generation machine, GRAPE-1, managed just 240 single precision megaflops in 1989. The following year, the team build a double precision processor, which culminated in the 40-megaflop GRAPE-2. In 1998, they fielded GRAPE-4, their first teraflop system. The most recently system, GRAPE-DR, was designed to be a petascale machine, although its TOP500 entry showed up in 2009 as an 84.5 teraflop cluster.

Even though the GRAPE team was able to squeeze a lot more performance out of specially built hardware than they would have using general-purpose HPC machinery, it’s an expensive proposition. Each GRAPE iteration was based on a different ASIC design, necessitating the costly and time-consuming process of chip design, verification, and production. And as transistor geometries shrunk, development costs soared.

As the GRAPE team at Hitotsubashi University and the Tokyo Institute of Technology began planning the next generation, they decided that chip R&D could take up no more than a quarter of system’s cost. But given the escalating expense of processor development, they would overshoot that by a wide margin. In 2010, they estimated it would take on the order of $10 million to develop a new custom ASIC on 45nm technology. So when it came time for GRAPE-8, the engineers were looking for alternatives.

The natural candidates were GPUs and FPGAs, which offer a lot of computational horsepower in an energy-efficient package. Each had its advantages: FPGAs in customization capability, GPUs in raw computing power. Ultimately though, they opted for a technology developed by eASIC, a fabless semiconductor company that offered a special kind of purpose-built ASIC, based on an FPGA workflow.

The technology had little grounding in high performance computing, being used mostly in embedded platforms, like wireless infrastructure and enterprise storage hardware. But the GRAPE designers were impressed by the efficiency of the technology. With an eASIC chip, they could get the same computational power as an FPGA for a tenth of the size and at about a third of the cost. And although the latest GPUs were slightly more powerful flop-wise than what eASIC could deliver, power consumption was an order of magnitude higher.

In a nutshell, the company offers something between an FPGA and a conventional ASIC. According to Niall Battson, eASIC’s Senior Product Manager, it looks like a field-programmable gate array, but “all the programming circuitry has been taken out.” That saves on both chip real estate and power since that circuitry doesn’t end up on the die.

In essence, the company is able to take an FPGA design (in RTL or whatever) and produce an ASIC from it. But not a conventional one. Battson says their real secret sauce is that the logic is laid down in a single silicon layer, rather than the four or five used for conventional ASICs. That simplification greatly speeds up chip validation and manufacturing, so much so that they can turn around a production chip in 4 to 6 months, depending upon the complexity of the design.

While the logic density and power efficiency are less than that of a standard ASIC, the up-front costs are considerably lower. For customers whose volumes eventually warrant a “true” ASIC (like for disk drive controllers), eASIC provides a service that takes the customer’s design through that final step of hardening.

For the astrophysics simulation supercomputer, no such step was necessary. The 45nm chip eASIC built and delivered for the new GRAPE-8 system achieves close to 500 gigaflops (250 MHz) with a power draw of just 10 watts. The GRAPE-8 accelerator board houses two of these custom chips, plus a standard processor, delivering 960 gigaflops in 46 watts. When hooked up to a PC host, another 200 watts is added. Even in this makeshift configuration, the system achieves 6.5 gigaflops per watt, about three times better that the 2.1 gigaflops per watt held by IBM’s Blue Gene/Q, the current Green500 champ.

Of course, the Blue Gene/Q is a general-purpose supercomputer, so the comparison is bit of apples-to-oranges. But the generality of computer designs exists on a continuum, not as a binary taxonomy. In general, better performance and power efficiency can be achieved as more specialization is incorporated into the hardware. The downside is that such single-application machines are notoriously expensive, which explains why there are so few of them. Besides GRAPE, only the Anton supercomputer (for molecular dynamics simulations) is still using application-specific ASICs.

The GRAPE designers are actually interested in building a more ambidextrous machine to handle a greater variety of science applications. In fact, the GRAPE-DR machine was a bit of a departure from its predecessors and was intended for applications outside of astrophysics simulations, including genome analysis, protein modeling and molecular dynamics.

According to Battson, a more general-purpose SIMD chip is certainly possible under an eASIC scheme, and they’re considering how they might be able to tweak their technology to make that happen. The company’s next generation 28nm product is slated to deliver twice the performance, while halving power consumption, so there is some headroom for added capabilities. The main problem he says is that a general-purpose SIMD ASIC would probably need to run twice as fast as the GRAPE-8 chip to deliver reasonable performance, and that drives up power consumption.

Of course, with the prospect of energy-sucking exascale machines on the horizon, application-specific supercomputing could make a comeback, especially if spinning out purpose-built accelerators was made fast and affordable. In that case, eASIC and its technology might find itself with a lot of eager suitors.

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