Novel Chip Technology to Power GRAPE-8 Supercomputer

By Michael Feldman

May 10, 2012

With the fastest supercomputers on the planet sporting multi-megawatt appetites, green HPC has become all the rage. The IBM Blue Gene/Q machine is currently number one in energy-efficient flops, but a new FPGA-like technology brought to market by semiconductor startup eASIC is providing an even greener computing solution. And one HPC project in Japan, known as GRAPE, is using the chips to power its newest supercomputer.

GRAPE, which stands for Gravity Pipe, is a Japanese computing project that is focused on astrophysical simulation. (More specifically, the application uses Newtonian physics to compute the interaction of particles in N-body systems). The project, which began in 1989, has gone through eight generations of hardware, all of which were built as special-purpose supercomputer systems.

Each of the GRAPE machines was powered by a custom-built chip, specifically designed to optimize the astrophysical calculations that form the basis of the simulation work. The special-purpose processors were hooked up as external accelerators, using more conventional CPU-based host systems, in the form or workstations or servers, to drive the application.

The first-generation machine, GRAPE-1, managed just 240 single precision megaflops in 1989. The following year, the team build a double precision processor, which culminated in the 40-megaflop GRAPE-2. In 1998, they fielded GRAPE-4, their first teraflop system. The most recently system, GRAPE-DR, was designed to be a petascale machine, although its TOP500 entry showed up in 2009 as an 84.5 teraflop cluster.

Even though the GRAPE team was able to squeeze a lot more performance out of specially built hardware than they would have using general-purpose HPC machinery, it’s an expensive proposition. Each GRAPE iteration was based on a different ASIC design, necessitating the costly and time-consuming process of chip design, verification, and production. And as transistor geometries shrunk, development costs soared.

As the GRAPE team at Hitotsubashi University and the Tokyo Institute of Technology began planning the next generation, they decided that chip R&D could take up no more than a quarter of system’s cost. But given the escalating expense of processor development, they would overshoot that by a wide margin. In 2010, they estimated it would take on the order of $10 million to develop a new custom ASIC on 45nm technology. So when it came time for GRAPE-8, the engineers were looking for alternatives.

The natural candidates were GPUs and FPGAs, which offer a lot of computational horsepower in an energy-efficient package. Each had its advantages: FPGAs in customization capability, GPUs in raw computing power. Ultimately though, they opted for a technology developed by eASIC, a fabless semiconductor company that offered a special kind of purpose-built ASIC, based on an FPGA workflow.

The technology had little grounding in high performance computing, being used mostly in embedded platforms, like wireless infrastructure and enterprise storage hardware. But the GRAPE designers were impressed by the efficiency of the technology. With an eASIC chip, they could get the same computational power as an FPGA for a tenth of the size and at about a third of the cost. And although the latest GPUs were slightly more powerful flop-wise than what eASIC could deliver, power consumption was an order of magnitude higher.

In a nutshell, the company offers something between an FPGA and a conventional ASIC. According to Niall Battson, eASIC’s Senior Product Manager, it looks like a field-programmable gate array, but “all the programming circuitry has been taken out.” That saves on both chip real estate and power since that circuitry doesn’t end up on the die.

In essence, the company is able to take an FPGA design (in RTL or whatever) and produce an ASIC from it. But not a conventional one. Battson says their real secret sauce is that the logic is laid down in a single silicon layer, rather than the four or five used for conventional ASICs. That simplification greatly speeds up chip validation and manufacturing, so much so that they can turn around a production chip in 4 to 6 months, depending upon the complexity of the design.

While the logic density and power efficiency are less than that of a standard ASIC, the up-front costs are considerably lower. For customers whose volumes eventually warrant a “true” ASIC (like for disk drive controllers), eASIC provides a service that takes the customer’s design through that final step of hardening.

For the astrophysics simulation supercomputer, no such step was necessary. The 45nm chip eASIC built and delivered for the new GRAPE-8 system achieves close to 500 gigaflops (250 MHz) with a power draw of just 10 watts. The GRAPE-8 accelerator board houses two of these custom chips, plus a standard processor, delivering 960 gigaflops in 46 watts. When hooked up to a PC host, another 200 watts is added. Even in this makeshift configuration, the system achieves 6.5 gigaflops per watt, about three times better that the 2.1 gigaflops per watt held by IBM’s Blue Gene/Q, the current Green500 champ.

Of course, the Blue Gene/Q is a general-purpose supercomputer, so the comparison is bit of apples-to-oranges. But the generality of computer designs exists on a continuum, not as a binary taxonomy. In general, better performance and power efficiency can be achieved as more specialization is incorporated into the hardware. The downside is that such single-application machines are notoriously expensive, which explains why there are so few of them. Besides GRAPE, only the Anton supercomputer (for molecular dynamics simulations) is still using application-specific ASICs.

The GRAPE designers are actually interested in building a more ambidextrous machine to handle a greater variety of science applications. In fact, the GRAPE-DR machine was a bit of a departure from its predecessors and was intended for applications outside of astrophysics simulations, including genome analysis, protein modeling and molecular dynamics.

According to Battson, a more general-purpose SIMD chip is certainly possible under an eASIC scheme, and they’re considering how they might be able to tweak their technology to make that happen. The company’s next generation 28nm product is slated to deliver twice the performance, while halving power consumption, so there is some headroom for added capabilities. The main problem he says is that a general-purpose SIMD ASIC would probably need to run twice as fast as the GRAPE-8 chip to deliver reasonable performance, and that drives up power consumption.

Of course, with the prospect of energy-sucking exascale machines on the horizon, application-specific supercomputing could make a comeback, especially if spinning out purpose-built accelerators was made fast and affordable. In that case, eASIC and its technology might find itself with a lot of eager suitors.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Rockport Networks Launches 300 Gbps Switchless Fabric, Reveals 396-Node Deployment at TACC

October 27, 2021

Rockport Networks emerged from stealth this week with the launch of its 300 Gbps switchless networking architecture focused on the needs of the high-performance computing and the advanced-scale AI market. Early customers Read more…

AWS Adds Gaudi-Powered, ML-Optimized EC2 DL1 Instances, Now in GA

October 27, 2021

As machine learning becomes a dominating use case for local and cloud computing, companies are racing to provide solutions specifically optimized and accelerated for AI applications. Now, Amazon Web Services (AWS) is int Read more…

Fireside Chat with LBNL’s Advanced Quantum Testbed Director

October 26, 2021

Last week, Irfan Siddiqi led a “fireside chat” with a few media and analysts to introduce the Department of Energy’s relatively new Advanced Quantum Testbed (AQT), which is based at Lawrence Berkeley National Labor Read more…

Graphcore Introduces Larger-Than-Ever IPU-Based Pods

October 22, 2021

After launching its second-generation intelligence processing units (IPUs) in 2020, four years after emerging from stealth, Graphcore is now boosting its product line with its largest commercially-available IPU-based sys Read more…

Quantum Chemistry Project to Be Among the First on EuroHPC’s LUMI System

October 22, 2021

Finland’s CSC has just installed the first module of LUMI, a 550-peak petaflops system supported by the European Union’s EuroHPC Joint Undertaking. While LUMI -- pictured in the header -- isn’t slated to complete i Read more…

AWS Solution Channel

Royalty-free stock illustration ID: 577238446

Putting bitrates into perspective

Recently, we talked about the advances NICE DCV has made to push pixels from cloud-hosted desktops or applications over the internet even more efficiently than before. Read more…

Killer Instinct: AMD’s Multi-Chip MI200 GPU Readies for a Major Global Debut

October 21, 2021

AMD’s next-generation supercomputer GPU is on its way – and by all appearances, it’s about to make a name for itself. The AMD Radeon Instinct MI200 GPU (a successor to the MI100) will, over the next year, begin to power three massive systems on three continents: the United States’ exascale Frontier system; the European Union’s pre-exascale LUMI system; and Australia’s petascale Setonix system. Read more…

Rockport Networks Launches 300 Gbps Switchless Fabric, Reveals 396-Node Deployment at TACC

October 27, 2021

Rockport Networks emerged from stealth this week with the launch of its 300 Gbps switchless networking architecture focused on the needs of the high-performance Read more…

AWS Adds Gaudi-Powered, ML-Optimized EC2 DL1 Instances, Now in GA

October 27, 2021

As machine learning becomes a dominating use case for local and cloud computing, companies are racing to provide solutions specifically optimized and accelerate Read more…

Fireside Chat with LBNL’s Advanced Quantum Testbed Director

October 26, 2021

Last week, Irfan Siddiqi led a “fireside chat” with a few media and analysts to introduce the Department of Energy’s relatively new Advanced Quantum Testb Read more…

Killer Instinct: AMD’s Multi-Chip MI200 GPU Readies for a Major Global Debut

October 21, 2021

AMD’s next-generation supercomputer GPU is on its way – and by all appearances, it’s about to make a name for itself. The AMD Radeon Instinct MI200 GPU (a successor to the MI100) will, over the next year, begin to power three massive systems on three continents: the United States’ exascale Frontier system; the European Union’s pre-exascale LUMI system; and Australia’s petascale Setonix system. Read more…

D-Wave Embraces Gate-Based Quantum Computing; Charts Path Forward

October 21, 2021

Earlier this month D-Wave Systems, the quantum computing pioneer that has long championed quantum annealing-based quantum computing (and sometimes taken heat fo Read more…

LLNL Prepares the Water and Power Infrastructure for El Capitan

October 21, 2021

When it’s (ostensibly) ready in early 2023, El Capitan is expected to deliver in excess of two exaflops of peak computing power – around four times the powe Read more…

Intel Reorgs HPC Group, Creates Two ‘Super Compute’ Groups

October 15, 2021

Following on changes made in June that moved Intel’s HPC unit out of the Data Platform Group and into the newly created Accelerated Computing Systems and Graphics (AXG) business unit, led by Raja Koduri, Intel is making further updates to the HPC group and announcing... Read more…

Quantum Workforce – NSTC Report Highlights Need for International Talent

October 13, 2021

Attracting and training the needed quantum workforce to fuel the ongoing quantum information sciences (QIS) revolution is a hot topic these days. Last week, the U.S. National Science and Technology Council issued a report – The Role of International Talent in Quantum Information Science... Read more…

Enter Dojo: Tesla Reveals Design for Modular Supercomputer & D1 Chip

August 20, 2021

Two months ago, Tesla revealed a massive GPU cluster that it said was “roughly the number five supercomputer in the world,” and which was just a precursor to Tesla’s real supercomputing moonshot: the long-rumored, little-detailed Dojo system. Read more…

Esperanto, Silicon in Hand, Champions the Efficiency of Its 1,092-Core RISC-V Chip

August 27, 2021

Esperanto Technologies made waves last December when it announced ET-SoC-1, a new RISC-V-based chip aimed at machine learning that packed nearly 1,100 cores onto a package small enough to fit six times over on a single PCIe card. Now, Esperanto is back, silicon in-hand and taking aim... Read more…

US Closes in on Exascale: Frontier Installation Is Underway

September 29, 2021

At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, held by Zoom this week (Sept. 29-30), it was revealed that the Frontier supercomputer is currently being installed at Oak Ridge National Laboratory in Oak Ridge, Tenn. The staff at the Oak Ridge Leadership... Read more…

Intel Reorgs HPC Group, Creates Two ‘Super Compute’ Groups

October 15, 2021

Following on changes made in June that moved Intel’s HPC unit out of the Data Platform Group and into the newly created Accelerated Computing Systems and Graphics (AXG) business unit, led by Raja Koduri, Intel is making further updates to the HPC group and announcing... Read more…

Ahead of ‘Dojo,’ Tesla Reveals Its Massive Precursor Supercomputer

June 22, 2021

In spring 2019, Tesla made cryptic reference to a project called Dojo, a “super-powerful training computer” for video data processing. Then, in summer 2020, Tesla CEO Elon Musk tweeted: “Tesla is developing a [neural network] training computer... Read more…

Intel Completes LLVM Adoption; Will End Updates to Classic C/C++ Compilers in Future

August 10, 2021

Intel reported in a blog this week that its adoption of the open source LLVM architecture for Intel’s C/C++ compiler is complete. The transition is part of In Read more…

Hot Chips: Here Come the DPUs and IPUs from Arm, Nvidia and Intel

August 25, 2021

The emergence of data processing units (DPU) and infrastructure processing units (IPU) as potentially important pieces in cloud and datacenter architectures was Read more…

AMD-Xilinx Deal Gains UK, EU Approvals — China’s Decision Still Pending

July 1, 2021

AMD’s planned acquisition of FPGA maker Xilinx is now in the hands of Chinese regulators after needed antitrust approvals for the $35 billion deal were receiv Read more…

Leading Solution Providers

Contributors

HPE Wins $2B GreenLake HPC-as-a-Service Deal with NSA

September 1, 2021

In the heated, oft-contentious, government IT space, HPE has won a massive $2 billion contract to provide HPC and AI services to the United States’ National Security Agency (NSA). Following on the heels of the now-canceled $10 billion JEDI contract (reissued as JWCC) and a $10 billion... Read more…

Intel Unveils New Node Names; Sapphire Rapids Is Now an ‘Intel 7’ CPU

July 27, 2021

What's a preeminent chip company to do when its process node technology lags the competition by (roughly) one generation, but outmoded naming conventions make i Read more…

Quantum Roundup: IBM, Rigetti, Phasecraft, Oxford QC, China, and More

July 13, 2021

IBM yesterday announced a proof for a quantum ML algorithm. A week ago, it unveiled a new topology for its quantum processors. Last Friday, the Technical Univer Read more…

The Latest MLPerf Inference Results: Nvidia GPUs Hold Sway but Here Come CPUs and Intel

September 22, 2021

The latest round of MLPerf inference benchmark (v 1.1) results was released today and Nvidia again dominated, sweeping the top spots in the closed (apples-to-ap Read more…

10nm, 7nm, 5nm…. Should the Chip Nanometer Metric Be Replaced?

June 1, 2020

The biggest cool factor in server chips is the nanometer. AMD beating Intel to a CPU built on a 7nm process node* – with 5nm and 3nm on the way – has been i Read more…

Frontier to Meet 20MW Exascale Power Target Set by DARPA in 2008

July 14, 2021

After more than a decade of planning, the United States’ first exascale computer, Frontier, is set to arrive at Oak Ridge National Laboratory (ORNL) later this year. Crossing this “1,000x” horizon required overcoming four major challenges: power demand, reliability, extreme parallelism and data movement. Read more…

Julia Update: Adoption Keeps Climbing; Is It a Python Challenger?

January 13, 2021

The rapid adoption of Julia, the open source, high level programing language with roots at MIT, shows no sign of slowing according to data from Julialang.org. I Read more…

D-Wave Embraces Gate-Based Quantum Computing; Charts Path Forward

October 21, 2021

Earlier this month D-Wave Systems, the quantum computing pioneer that has long championed quantum annealing-based quantum computing (and sometimes taken heat fo Read more…

  • arrow
  • Click Here for More Headlines
  • arrow
HPCwire