Intel Rolls Out New Server CPUs

By Michael Feldman

May 14, 2012

Intel Corp. has launched three new families of Xeon processors, joining the Xeon E5-2600 series the chipmaker introduced in March. These latest chips span the entire market for the Xeon line, from four- and two-socket servers, down to entry-level workstations and microservers. A number of HPC server makers, including SGI, Dell, and Appro announced updated hardware based on the new silicon.

The newest Xeon of greatest interest to high performance computing is the Sandy Bridge E5-4600 series, which is built for four-socket servers. At the CPU level, the E5-4600 is more or less identical to the E5-2600 for two-socket systems, both of which are available in 4-, 6-, and 8-core flavors, support 4 memory channels, include 40 lanes of integrated PCIe 3.0, and come with up to 20 MB of last level cache. The four-socket E5-4600 can support twice as much memory per system (up to 1.5 TB) as its two-socket counterpart, but that just serves to keep the per processor and per core memory ratio in line.

In normal times, the new four-socket Xeon would simply take the place of the older technology, in this case the Xeon E7 (“Westmere-EX”), but Intel has moved the new chip into a somewhat different role. According to Michele Fisher, a senior product marketing engineer at Intel, the E5-4600 is intended to complement the E7, rather than replace it. Specifically, the Sandy Bridge version is a “cost and density optimized” CPU for four-socket servers, which in this case is reflected in less cores (maxing out at 8 instead of 10 on the Westmere-EX), a lower memory capacity (1.5 TB instead of 2.0 TB), and less RAS support. It’s also less expensive. The price range on the new four-socket Xeons is $551 to $3,616; on the older Westmere E7 chips, it’s $774 to $4,616.

The idea, says Fisher, is to target the new four-socket CPUs for dense, scale-out systems in domains like HPC and telco, and to support growing geographies like China, which are especially cost-conscious. And because of their density and better energy efficiency, the new CPUs are especially suitable for four-socket blade servers. The older E7 chips will continue to be sold into more traditional enterprise systems, in particular, high-end transactional database machines, where the larger memory footprint and high reliability features are most appreciated.

Since the E5-4600 supports the Advanced Vector Extensions (AVX), courtesy of the Sandy Bridge microarchitecture, the new chip can do floating point operations at twice the clip of its pre-AVX predecessors. According to Intel, a four-socket server outfitted with E5-4650 CPUs can deliver 602 gigaflops on Linpack, which is nearly twice the flops that can be achieved with the top-of the-line E7 technology. That makes this chip a fairly obvious replacement for the E7 when the application domain is scientific computing.

Which explains why SGI is upgrading its Altix UV shared memory supercomputing platform from the E7 to the E5-4600. Also, since the UV has SGI’s custom NUMAlink interconnect and node controller, that system can scale well beyond the four sockets and 1.5 TB of cache coherent memory based on the native Intel chipset.

In fact, SGI’s new Sandy Bridge-based UV can scale up to 4,096 cores and 64 TB of memory in a single system. That’s twice the number of cores and four times the memory of the older Westmere-based UV. And because of the chip’s AVX support, peak flops per UV rack has doubled, from 5.4 to 11 teraflops.

SGI has already sold one of its new UVs to the COSMOS Consortium, a group that uses HPC to support origin-of-the-universe type research associated with Stephen Hawking’s cosmology work. Some of the simulations are designed to reveal the nature of the universe immediately after — as in one second after — the Big Bang. The computer will also support other cosmology research, including searching for planets outside our solar system.

Dell is also using the E5-4600, but in more conventional HPC gear. It’s putting the new Xeon into its four-socket PowerEdge M820 and R820, a blade and rackmount server, respectively. The M820 can house up to 10 full-height blades in 10U chassis, while the half-as-dense rackmount R820 puts a single four-socket server into a 2U box.

A couple steps down performance-wise from the E5-4600 is Intel’s new Sandy Bridge E5-2400, aimed at lower-end two socket servers. It’s designed to be a more energy-efficient alternative to the original two-socket E5-2600. It’s also considerably cheaper, with a price range of $188 to $1,440.

The E5-2400 series spans the same core counts as E5-2600, but gets by with one less memory channel (3), fewer PCIe lanes (24), and maxes out at half the memory (384 GB) of its older sibling. More importantly, they tend to be slower chips; the top-end E5-2440 is nearly full gigahertz slower (2.4 GHz) than the fastest E5-2600. But that translates into less power draw — from 60 watts on the low end part, up to 95 watts at the top end.

Their energy efficiency and cost make them suitable for scale-out clusters that don’t require a lot of single-threaded horsepower. Dell, for example, is using the E5-2400 processors in their new M420 blade, which is being positioned for some HPC-type workloads, especially animation and CGI rendering. The M420 is the first quarter-height dual-socket blade in the market; 32 of the mini-blades (1024 cores) can be squeezed into a 10U chassis. As with the four-socket gear, Dell is also offering a rackmount counterpart, the R420.

SGI is using the E5-2400 CPU as the base processor for its the Hadoop clusters, as well as in its Rackable server line for more general enterprise duty. For many Hadoop applications, which tend to be bound by data movement, rather than raw computational muscle, this chip could be a nice fit. And even though it’s slower than the mainline E5-2600 chips, SGI is still promising 22 percent better price-performance and 27 percent better performance/watt than the corresponding Westmere EP-based Hadoop gear.

The third new Xeon is the one-socket E3-1200 v2, a 22nm Ivy Bridge CPU for entry-level servers and workstations. Offered in dual-core and quad-core configurations, prices range from $189 to $884. The fastest part, at 3.7 GHz, offers quite respectable performance, but with only 8 MB of cache and a maximum memory capacity of 32 GB, the chip might be a bit of a stretch for HPC duty.

The family also includes two interesting new CPUs aimed at the microserver market, including Intel’s lowest powered Xeon, the E3-1220L v2. With a TDP of just 17 watts, that’s approaching ARM CPU territory. For example, Calexda makes a quad-core ARM chip for microservers that draws 5 watts, but that’s a 32-bit CPU, which limits its application in the server room rather substantially. The 64-bit E3 Xeon would have no such problem.

Intel is not positioning these new microserver Xeons for high performance computing; ostensibly they’re targeted for front-end web workloads, content delivery, and dedicated hosting. However, some creative server maker might be able to design a nifty little one-socket box with the E3-1220L v2 that could be used for some types of embarrassingly parallel codes. But since Intel would much rather sell its higher end E5 Xeons to its HPC customers, we’re not likely to see a Xeon-based microservers in supercomputers anytime soon.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Data Vortex Users Contemplate the Future of Supercomputing

October 19, 2017

Last month (Sept. 11-12), HPC networking company Data Vortex held its inaugural users group at Pacific Northwest National Laboratory (PNNL) bringing together about 30 participants from industry, government and academia t Read more…

By Tiffany Trader

AI Self-Training Goes Forward at Google DeepMind

October 19, 2017

DeepMind, Google’s AI research organization, announced today in a blog that AlphaGo Zero, the latest evolution of AlphaGo (the first computer program to defeat a Go world champion) trained itself within three days to play Go at a superhuman level (i.e., better than any human) – and to beat the old version of AlphaGo – without leveraging human expertise, data or training. Read more…

By Doug Black

Researchers Scale COSMO Climate Code to 4888 GPUs on Piz Daint

October 17, 2017

Effective global climate simulation, sorely needed to anticipate and cope with global warming, has long been computationally challenging. Two of the major obstacles are the needed resolution and prolonged time to compute Read more…

By John Russell

HPE Extreme Performance Solutions

Transforming Genomic Analytics with HPC-Accelerated Insights

Advancements in the field of genomics are revolutionizing our understanding of human biology, rapidly accelerating the discovery and treatment of genetic diseases, and dramatically improving human health. Read more…

Student Cluster Competition Coverage New Home

October 16, 2017

Hello computer sports fans! This is the first of many (many!) articles covering the world-wide phenomenon of Student Cluster Competitions. Finally, the Student Cluster Competition coverage has come to its natural home: H Read more…

By Dan Olds

Data Vortex Users Contemplate the Future of Supercomputing

October 19, 2017

Last month (Sept. 11-12), HPC networking company Data Vortex held its inaugural users group at Pacific Northwest National Laboratory (PNNL) bringing together ab Read more…

By Tiffany Trader

AI Self-Training Goes Forward at Google DeepMind

October 19, 2017

DeepMind, Google’s AI research organization, announced today in a blog that AlphaGo Zero, the latest evolution of AlphaGo (the first computer program to defeat a Go world champion) trained itself within three days to play Go at a superhuman level (i.e., better than any human) – and to beat the old version of AlphaGo – without leveraging human expertise, data or training. Read more…

By Doug Black

Student Cluster Competition Coverage New Home

October 16, 2017

Hello computer sports fans! This is the first of many (many!) articles covering the world-wide phenomenon of Student Cluster Competitions. Finally, the Student Read more…

By Dan Olds

Intel Delivers 17-Qubit Quantum Chip to European Research Partner

October 10, 2017

On Tuesday, Intel delivered a 17-qubit superconducting test chip to research partner QuTech, the quantum research institute of Delft University of Technology (TU Delft) in the Netherlands. The announcement marks a major milestone in the 10-year, $50-million collaborative relationship with TU Delft and TNO, the Dutch Organization for Applied Research, to accelerate advancements in quantum computing. Read more…

By Tiffany Trader

Fujitsu Tapped to Build 37-Petaflops ABCI System for AIST

October 10, 2017

Fujitsu announced today it will build the long-planned AI Bridging Cloud Infrastructure (ABCI) which is set to become the fastest supercomputer system in Japan Read more…

By John Russell

HPC Chips – A Veritable Smorgasbord?

October 10, 2017

For the first time since AMD's ill-fated launch of Bulldozer the answer to the question, 'Which CPU will be in my next HPC system?' doesn't have to be 'Whichever variety of Intel Xeon E5 they are selling when we procure'. Read more…

By Dairsie Latimer

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Intel Debuts Programmable Acceleration Card

October 5, 2017

With a view toward supporting complex, data-intensive applications, such as AI inference, video streaming analytics, database acceleration and genomics, Intel i Read more…

By Doug Black

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

NERSC Scales Scientific Deep Learning to 15 Petaflops

August 28, 2017

A collaborative effort between Intel, NERSC and Stanford has delivered the first 15-petaflops deep learning software running on HPC platforms and is, according Read more…

By Rob Farber

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Oracle Layoffs Reportedly Hit SPARC and Solaris Hard

September 7, 2017

Oracle’s latest layoffs have many wondering if this is the end of the line for the SPARC processor and Solaris OS development. As reported by multiple sources Read more…

By John Russell

US Coalesces Plans for First Exascale Supercomputer: Aurora in 2021

September 27, 2017

At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, in Arlington, Va., yesterday (Sept. 26), it was revealed that the "Aurora" supercompute Read more…

By Tiffany Trader

Google Releases Deeplearn.js to Further Democratize Machine Learning

August 17, 2017

Spreading the use of machine learning tools is one of the goals of Google’s PAIR (People + AI Research) initiative, which was introduced in early July. Last w Read more…

By John Russell

GlobalFoundries Puts Wind in AMD’s Sails with 12nm FinFET

September 24, 2017

From its annual tech conference last week (Sept. 20), where GlobalFoundries welcomed more than 600 semiconductor professionals (reaching the Santa Clara venue Read more…

By Tiffany Trader

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in Read more…

By Tiffany Trader

Leading Solution Providers

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Amazon Debuts New AMD-based GPU Instances for Graphics Acceleration

September 12, 2017

Last week Amazon Web Services (AWS) streaming service, AppStream 2.0, introduced a new GPU instance called Graphics Design intended to accelerate graphics. The Read more…

By John Russell

EU Funds 20 Million Euro ARM+FPGA Exascale Project

September 7, 2017

At the Barcelona Supercomputer Centre on Wednesday (Sept. 6), 16 partners gathered to launch the EuroEXA project, which invests €20 million over three-and-a-half years into exascale-focused research and development. Led by the Horizon 2020 program, EuroEXA picks up the banner of a triad of partner projects — ExaNeSt, EcoScale and ExaNoDe — building on their work... Read more…

By Tiffany Trader

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Cray Moves to Acquire the Seagate ClusterStor Line

July 28, 2017

This week Cray announced that it is picking up Seagate's ClusterStor HPC storage array business for an undisclosed sum. "In short we're effectively transitioning the bulk of the ClusterStor product line to Cray," said CEO Peter Ungaro. Read more…

By Tiffany Trader

Intel Launches Software Tools to Ease FPGA Programming

September 5, 2017

Field Programmable Gate Arrays (FPGAs) have a reputation for being difficult to program, requiring expertise in specialty languages, like Verilog or VHDL. Easin Read more…

By Tiffany Trader

IBM Advances Web-based Quantum Programming

September 5, 2017

IBM Research is pairing its Jupyter-based Data Science Experience notebook environment with its cloud-based quantum computer, IBM Q, in hopes of encouraging a new class of entrepreneurial user to solve intractable problems that even exceed the capabilities of the best AI systems. Read more…

By Alex Woodie

HPC Chips – A Veritable Smorgasbord?

October 10, 2017

For the first time since AMD's ill-fated launch of Bulldozer the answer to the question, 'Which CPU will be in my next HPC system?' doesn't have to be 'Whichever variety of Intel Xeon E5 they are selling when we procure'. Read more…

By Dairsie Latimer

  • arrow
  • Click Here for More Headlines
  • arrow
Share This