Intel Releases Knights Corner ISA, Lays Groundwork for MIC Launch

By Michael Feldman

June 11, 2012

Intel has released a partial software stack for Knights Corner, the company’s first commercial chip based on its Many Integrated Core (MIC) architecture. Also released were a number of documents describing the processor’s micro-architecture, including the Knights Corner Instruction Set (ISA) Manual, which will help toolmakers and application developers build software for the upcoming chip. The newly released information was described in a couple of blog posts last week by James Reinders, Intel’s chief evangelist and director of marketing for the company’s software development portfolio.

Up until now, Intel had not shared this software or documentation with anyone outside of its partner network. That posed something of a problem for third-party developers who don’t have that relationship with the Intel, but are looking to get MIC software products out the door in time for the upcoming Knights Corner launch. That chip is expected to go into production sometime in late 2012 or early 2013. Giving this first MIC product a running start is crucial, since it going to be competing against a GPU computing ecosystem with a five-year head start and an already-established product portfolio.

The newly released software from Intel includes source modifications for Linux, the GCC compiler and the GDB debugger, as well as new MIC drivers, which, together, will allow developers to build a Linux OS kernel capable of running on the manycore coprocessor. In this case, that applies to the current Knights Ferry prototype hardware, which is currently being used as a development platform at a number of sites, as well as the future Knights Corner chips.

Embedding an operating system on a coprocessor might seem a bit exotic since usually the host CPU, alone, runs the OS. But since the MIC architecture is essentially a variant of a Pentium CPU, it’s quite capable of acting as its own host. That will allow the Knights Corner to behave as a peer to the CPU, rather than just its slave. How that gets used in practice is still up in the air, but it would certainly make for a more flexible development environment, inasmuch as entire Linux apps could be launched and controlled locally on the MIC chip.

Even though this software is now public, the mods still have to work their way into the various Linux, GCC and GDB distributions, which could take awhile. In the meantime, anyone with a Knights Ferry test setup or simulator can pick up the new code on Intel’s MIC software resource page and have at it.

It’s important to note that the current set of mods delivered last week does not include MIC application support, which would have to encompass GCC and GDB support for the Knight Corner vector instructions. (The Linux kernel running on the coprocessor has no need for vector instructions.) That means for the time being, developers will still have to rely on Intel’s own compilers (or a CAPS enterprise compiler that is hooked into the Intel MIC back-end) if they want to build Knights Ferry or Knights Corner applications.

Also left out is compiler support for any coprocessor offload directives (text that can be inserted into high-level source that tells the compiler to execute specific code on the accelerator). Intel has not endorsed OpenACC, the budding accelerator directives standard backed by NVIDIA and some of its partners (PGI, CAPS enterprise, and Cray). Instead it has invented its own offload technology, known as LEO (Language Extensions for Offload), which users of the Intel compiler can tap into to offload chunks of their application onto the MIC hardware.

LEO is a less restrictive and more generalized set of offload directives than OpenACC since its allows the programmer to offload virtually any function or even a whole application to the MIC hardware. Remember that MIC is based on the Pentium, an older Intel architecture chosen for its simpler design, which is more suitable for a manycore throughput processor. Although the individual cores are relatively slow, they have almost all the functional capabilities of Xeon cores. Thus MIC can behave as a general-purpose CPU, albeit one with limited single-thread performance and smaller memory.

In any case, LEO will likely never become a public standard on its own. The end game for Intel is to get its capabilities incorporated into OpenMP’s future extension for accelerator directives. That effort will somehow have to blend the more GPU-oriented OpenACC standard with the CPU-oriented LEO model and come up with a platform-independent standard that can be applied across all types of accelerators.

Although the MIC software stack that Intel donated last week didn’t do much for application developers, the documentation that was made public should help them, at least indirectly. In addition to the Knights Corner ISA manual, the chip maker also provided the ABI (Application Binary Interface) and Performance Monitoring Unit documents. With this documentation in hand, software tool makers now have the information needed to build their own MIC compilers, libraries and other developer gadgets like debuggers and simulators. All the docs are available for download on the MIC resources page mentioned above.

The ISA and the ABI documents are more like addendums to the standard IA versions since MIC itself is just an x86 variant. MIC, though, overlays 64-bit processing, extra wide vector instructions, and a manycore design on top of the original Pentium architecture, which makes it a unique IA64 processor family.

Not surprisingly, most of the ISA doc focuses on the 512-bit wide vector instructions, along with all the fancy vector masking and shifting that turns the new chip into a SIMD powerhouse. MIC’s vector width is twice that of AVX (256 bits), the SIMD instruction set in the latest Intel Sandy Bridge and AMD Bulldozer CPUs. AVX, in turn, doubled the 128-bit wide vectors available in the previous SSE vector units.

Although the ISA is intended to grease the wheels for third-party MIC software tools, the information can also be used by application developers who are looking to access MIC instruction directly via intrinsics (assembly instructions that can be inserted into high level source code). With the intrinsics, bare-metal programmers can tap directly into the hardware to eke out maximum performance.

Now that some of the software and supporting docs are in the public domain, Intel will be able to work more openly with MIC developers and third-party toolmakers. All of this should help to jumpstart the ecosystem in preparation for the upcoming Knights Corner launch, which is only about half a year away. At the International Supercomputing Conference (ISC’12) next week in Germany, we should get a much better sense of how far along Intel is with its MIC rollout.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

SC Bids Farewell to Denver, Heads to Dallas for 30th

November 17, 2017

After a jam-packed four-day expo and intensive six-day technical program, SC17 has wrapped up another successful event that brought together nearly 13,000 visitors to the Colorado Convention Center in Denver for the larg Read more…

By Tiffany Trader

SC17 Keynote – HPC Powers SKA Efforts to Peer Deep into the Cosmos

November 17, 2017

This week’s SC17 keynote – Life, the Universe and Computing: The Story of the SKA Telescope – was a powerful pitch for the potential of Big Science projects that also showcased the foundational role of high performance computing in modern science. It was also visually stunning. Read more…

By John Russell

How Cities Use HPC at the Edge to Get Smarter

November 17, 2017

Cities are sensoring up, collecting vast troves of data that they’re running through predictive models and using the insights to solve problems that, in some cases, city managers didn’t even know existed. Speaking Read more…

By Doug Black

HPE Extreme Performance Solutions

Harness Scalable Petabyte Storage with HPE Apollo 4510 and HPE StoreEver

As a growing number of connected devices challenges IT departments to rapidly collect, manage, and store troves of data, organizations must adopt a new generation of IT to help them operate quickly and intelligently. Read more…

SC17 Student Cluster Competition Configurations: Fewer Nodes, Way More Accelerators

November 16, 2017

The final configurations for each of the SC17 “Donnybrook in Denver” Student Cluster Competition have been released. Fortunately, each team received their equipment shipments on time and undamaged, so the teams are r Read more…

By Dan Olds

SC Bids Farewell to Denver, Heads to Dallas for 30th

November 17, 2017

After a jam-packed four-day expo and intensive six-day technical program, SC17 has wrapped up another successful event that brought together nearly 13,000 visit Read more…

By Tiffany Trader

SC17 Keynote – HPC Powers SKA Efforts to Peer Deep into the Cosmos

November 17, 2017

This week’s SC17 keynote – Life, the Universe and Computing: The Story of the SKA Telescope – was a powerful pitch for the potential of Big Science projects that also showcased the foundational role of high performance computing in modern science. It was also visually stunning. Read more…

By John Russell

How Cities Use HPC at the Edge to Get Smarter

November 17, 2017

Cities are sensoring up, collecting vast troves of data that they’re running through predictive models and using the insights to solve problems that, in some Read more…

By Doug Black

Student Cluster LINPACK Record Shattered! More LINs Packed Than Ever before!

November 16, 2017

Nanyang Technological University, the pride of Singapore, utterly destroyed the Student Cluster Competition LINPACK record by posting a score of 51.77 TFlop/s a Read more…

By Dan Olds

Hyperion Market Update: ‘Decent’ Growth Led by HPE; AI Transparency a Risk Issue

November 15, 2017

The HPC market update from Hyperion Research (formerly IDC) at the annual SC conference is a business and social “must,” and this year’s presentation at S Read more…

By Doug Black

Nvidia Focuses Its Cloud Containers on HPC Applications

November 14, 2017

Having migrated its top-of-the-line datacenter GPU to the largest cloud vendors, Nvidia is touting its Volta architecture for a range of scientific computing ta Read more…

By George Leopold

HPE Launches ARM-based Apollo System for HPC, AI

November 14, 2017

HPE doubled down on its memory-driven computing vision while expanding its processor portfolio with the announcement yesterday of the company’s first ARM-base Read more…

By Doug Black

OpenACC Shines in Global Climate/Weather Codes

November 14, 2017

OpenACC, the directive-based parallel programming model used mostly for porting codes to GPUs for use on heterogeneous systems, came to SC17 touting impressive Read more…

By John Russell

US Coalesces Plans for First Exascale Supercomputer: Aurora in 2021

September 27, 2017

At the Advanced Scientific Computing Advisory Committee (ASCAC) meeting, in Arlington, Va., yesterday (Sept. 26), it was revealed that the "Aurora" supercompute Read more…

By Tiffany Trader

NERSC Scales Scientific Deep Learning to 15 Petaflops

August 28, 2017

A collaborative effort between Intel, NERSC and Stanford has delivered the first 15-petaflops deep learning software running on HPC platforms and is, according Read more…

By Rob Farber

Oracle Layoffs Reportedly Hit SPARC and Solaris Hard

September 7, 2017

Oracle’s latest layoffs have many wondering if this is the end of the line for the SPARC processor and Solaris OS development. As reported by multiple sources Read more…

By John Russell

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Google Releases Deeplearn.js to Further Democratize Machine Learning

August 17, 2017

Spreading the use of machine learning tools is one of the goals of Google’s PAIR (People + AI Research) initiative, which was introduced in early July. Last w Read more…

By John Russell

GlobalFoundries Puts Wind in AMD’s Sails with 12nm FinFET

September 24, 2017

From its annual tech conference last week (Sept. 20), where GlobalFoundries welcomed more than 600 semiconductor professionals (reaching the Santa Clara venue Read more…

By Tiffany Trader

Amazon Debuts New AMD-based GPU Instances for Graphics Acceleration

September 12, 2017

Last week Amazon Web Services (AWS) streaming service, AppStream 2.0, introduced a new GPU instance called Graphics Design intended to accelerate graphics. The Read more…

By John Russell

EU Funds 20 Million Euro ARM+FPGA Exascale Project

September 7, 2017

At the Barcelona Supercomputer Centre on Wednesday (Sept. 6), 16 partners gathered to launch the EuroEXA project, which invests €20 million over three-and-a-half years into exascale-focused research and development. Led by the Horizon 2020 program, EuroEXA picks up the banner of a triad of partner projects — ExaNeSt, EcoScale and ExaNoDe — building on their work... Read more…

By Tiffany Trader

Leading Solution Providers

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

Delays, Smoke, Records & Markets – A Candid Conversation with Cray CEO Peter Ungaro

October 5, 2017

Earlier this month, Tom Tabor, publisher of HPCwire and I had a very personal conversation with Cray CEO Peter Ungaro. Cray has been on something of a Cinderell Read more…

By Tiffany Trader & Tom Tabor

Cray Moves to Acquire the Seagate ClusterStor Line

July 28, 2017

This week Cray announced that it is picking up Seagate's ClusterStor HPC storage array business for an undisclosed sum. "In short we're effectively transitioning the bulk of the ClusterStor product line to Cray," said CEO Peter Ungaro. Read more…

By Tiffany Trader

Intel Launches Software Tools to Ease FPGA Programming

September 5, 2017

Field Programmable Gate Arrays (FPGAs) have a reputation for being difficult to program, requiring expertise in specialty languages, like Verilog or VHDL. Easin Read more…

By Tiffany Trader

HPC Chips – A Veritable Smorgasbord?

October 10, 2017

For the first time since AMD's ill-fated launch of Bulldozer the answer to the question, 'Which CPU will be in my next HPC system?' doesn't have to be 'Whichever variety of Intel Xeon E5 they are selling when we procure'. Read more…

By Dairsie Latimer

IBM Advances Web-based Quantum Programming

September 5, 2017

IBM Research is pairing its Jupyter-based Data Science Experience notebook environment with its cloud-based quantum computer, IBM Q, in hopes of encouraging a new class of entrepreneurial user to solve intractable problems that even exceed the capabilities of the best AI systems. Read more…

By Alex Woodie

AMD Showcases Growing Portfolio of EPYC and Radeon-based Systems at SC17

November 13, 2017

AMD’s charge back into HPC and the datacenter is on full display at SC17. Having launched the EPYC processor line in June along with its MI25 GPU the focus he Read more…

By John Russell

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This