NERSC Signs Up for Multi-Petaflop “Cascade” Supercomputer

By Michael Feldman

July 3, 2012

The US Department of Energy’s National Energy Research Scientific Computing Center (NERSC) has ordered a two-petaflop “Cascade” supercomputer, Cray’s next-generation HPC platform. The DOE is shelling out $40 million dollars for the system, including about 6.5 petabytes of the company’s Sonexion storage. The contract covers both hardware and services, which will extend over multiple years. Installation is scheduled for sometime in 2013.

The NERSC acquisition represents Cray’s third publicly announced pre-sale of a Cascade system and the first in the US. The other two deals in the pipeline include a multi-petaflop machine destined for HLRS, at the University of Stuttgart, and a 400-teraflop one for Kyoto University.

Cascade is a big step for Cray. Not only does it represent the company’s first foray in Intel-based supercomputing, but it also fills out Cray’s Adaptive Supercomputing vision to a much greater degree than the previous XT and XE product lines. DARPA, which poured hundreds of millions of dollars into the design via the agency’s High Productivity Computing Systems (HPCS) program, helped to make Cascade a much bigger deal than just a platform refresh.

For example, a good portion of the funding went into developing more sophisticated compilers, tools and libraries, including the creation of the Chapel language, all aimed at making the platform more productive and easier to use. The extra money also allowed Cray the breathing room for a critical system redesign, in particular, the opportunity to ditch its AMD Opteron-only architecture.

Although much of the talk surrounding Cascade has been about putting Intel silicon into Cray hardware, the platform is actually designed to support multiple processor types. According to Cray CEO Peter Ungaro, they’ll be able to build blades with AMD processors, as they do now, as well as those with accelerators, like GPUs and Intel MIC (Xeon Phi) coprocessors, and even blades with future ARM chips, if they so desire. “It’s really going to open up our options to have targeted nodes for targeted workloads,” he told HPCwire.

The key is the new Aries interconnect, which is integrated with PCI Express (PCIe), a standard on-board bus that virtually all server processors will support. Prior to this, Cray’s interconnect technology (SeaStar, then Gemini) was tied to HyperTransport, which restricted the company’s supercomputers to AMD CPUs. With the faster speeds of PCIe 3.0, and its ubiquity, the bus technology is now in a position to serve as the underlying substrate for system networks, even for custom interconnects.

All of this potential heterogeneity is likely to be bypassed by NERSC though, at least initially. At a time when many other national labs are opting for GPUs on their fastest machines, NERSC-7 will be based entirely on Intel Xeon CPUs. No GPU or Intel MIC parts are to be used, although future upgrades with those accelerators are theoretically possible. According to Jeff Broughton, who heads NERSC’s Systems Department, the deployment will be based on “the latest generation of Intel processors available at the time of installation.” Given the 2013 timeframe, those chips could very well be Ivy Bridge CPUs rather than the Sandy Bridge parts in the field today.

By going with the more traditional CPU-only platform for NERSC’s first multi-petaflop super, the DOE lab has bucked a trend begun by other national labs like Oak Ridge, NCSA, and TACC , which are using GPUs or, in the case of TACC, Intel MIC accelerators, to get into the double-digit petaflop realm. NERSC-7 was also originally supposed to be a 10-petaflop machine, but getting there via x86 CPUs (that is, not with an IBM Blue Gene or Fujitsu K-type architecture) is not really economically feasible right now without accelerator add-ons.

According to NERSC director Kathy Yelick, the lab supports 4,500 users running hundreds of different codes, across many science disciplines and there is concern about forcing all that software to be rewritten for PCIe-based GPUs or Intel MIC devices. “Current accelerators have a separate memory space and are configured as coprocessors rather than first-class cores, both features that we are hoping will change,” she explained. “So while we are encouraging users to experiment with low-power processor technology, such as GPUs, in our testbeds, we do not think the time is right to transition all of the users.”

They do expect to move their users to some type of low-power manycore architecture over the next several years, but would like to make this transition just once. The first opportunity is likely to present itself with NERSC-8, the next major system procurement following NERSC-7. By the time that system is deployed a few years down the road, the system planners are probably thinking (or at least hoping) there will be a range of integrated low-power manycore architectures to choose from.

That’s a reasonable bet. Certainly, by the middle of the decade, we should at least see the appearance of NVIDIA’s ARM64-GPU “Maxwell” processor, an AMD server-class APU, and an Intel MIC chip integrated with some big Xeon CPU cores.

In the meantime, it should be relatively straightforward to run current user codes on NERSC-7 hardware since the lab’s existing petascale machine, Hopper, is a Cray XE6 system, and from an application point of view, will be nearly indistinguishable from its successor. Getting those codes to scale up to a machine with about twice the performance of Hopper could be somewhat of a challenge, but NERSC sees many potential candidates, both for simulation (LQCD, fusion, turbulence, astrophysics, chemistry, quantum Monte Carlo, molecular dynamics and cloud resolving climate models) and data analysis (bioinformatics and material screening). Of course, few if any applications are expected to use all two petaflops, but these big machines also function quite nicely as capacity clusters.

NERSC is likely to be only one of a number of US national labs signing up for Cascade supercomputers over the next few years. Given DARPA’s DoD pedigree, we should expect, at the very least, to see some defense labs acquire these next-generation Cray machines as they upgrade their HPC machinery.

Cascade will also be an opportunity for Cray to re-establish its dominance at the top of the supercomputing heap in the face of renewed competition from IBM. In the world’s top 100 systems, Blue Gene supercomputers are now the most numerous single platform, outdistancing Cray XT/XE installations by a 21 to 17 margin. That was the result of the recent surge of Blue Gene/Q deployments over the last six months, which was able to capture a lot of new business as it squared off against the now two-year-old Cray XE6.

Cray is certainly expecting great things from Cascade. Over the past eight years, the company has managed to steadily expand sales of its x86 supercomputing portfolio. Starting with its Red Storm supercomputer in 2004, which led to the company’s first commercial x86-based product, XT3, and then to subsequent platforms, XT4, XT5, XT6 and XE6/XK6, Cray has sold more cabinets with each successive generation. “If we keep that trend going,” says Ungaro, “we’ll be in good shape.”

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