AMD Unveils Teraflop GPU with ECC Support

By Michael Feldman

August 8, 2012

Advanced Micro Devices (AMD) has launched six new FirePro processors for workstation users who want high-end graphics and computation in a single box. One of them promises a teraflop of double precision performance as well as support for error correcting code (ECC) memory. The new offerings also includes two APUs (Accelerated Processing Units) that glue four CPU cores and hundreds of FirePro GPU stream processors onto the same chip.

The straight-up GPU-based cards are the FirePro W9000, W8000, W7000 and W5000. All are meant to provide hefty graphics support as well as respectable number-crunching performance. They are based on AMD’s new Graphics Core Next Architecture, which according to the company is their “first design specifically engineered for general computing.” Application development is supported via C++ AMP (Accelerated Massive Parallelism) and OpenCL, two open standard languages that are meant to offer an alternative to NVIDIA’s CUDA programming framework.

The top-of-the-line W9000 and W8000 are the ones built to chew on heavy-duty numeric codes such as CAD, CAE, medical imaging, and digital content creation, while also providing enough graphics muscle to drive up to six 30-inch displays. Both are double-slot cards that support the newer, faster PCIe Gen3 interface.

Performance-wise, the W9000 and W8000 are rather impressive beasts. The W9000 is the one that will deliver a double precision (DP) teraflop of peak performance. If only 32 bits of precision are required, this same chip will provide a whopping four teraflops in single precision (SP). That outruns NVIDIA’s fastest Tesla GPU (665 DP gigaflops and 1330 SP gigaflops) by a fair margin, although their newer Kepler K10 card edges out the W9000 in the single precision department with 4.58 teraflops, and the upcoming Kepler K20 is likely to be well above a DP teraflop when it’s launched in a few months. The K20 will be NVIDIA’s flagship supercomputing chip, but like these FirePros, will also be tapped for workstation duty.

The most interesting new feature in the FirePro lineup is the addition of ECC support, which is incorporated in the W9000 and W8000 products. ECC is used to insure that errant memory bits flips don’t mess up numeric calculations and is specifically aimed at high performance computing (HPC) codes. NVIDIA introduced this feature into its GPGPU Tesla lineup back in 2009.

The introduction of ECC suggests AMD is taking GPU computing a lot more seriously that it did when it was hawking its non-ECC FireStream GPU cards a few years ago. It also suggest that we may soon see some server-class FirePro offering with this capability in the near future. In fact, ECC actually has limited use in workstations. It’s real value becomes apparent when applications are deployed at scale, across multiple nodes of a cluster, where there is a much more likelihood that flipped memory bits will result in software failures.

ECC aside, the latest FirePro cards have a decent amount of memory and bandwidth for both graphics or computation (and a lot more than the older FireStream offerings). The top-end W9000 sports 6 GB of on-board GDDR5 memory and 264 GB/sec of bandwidth. Those specs are pretty much on par with the latest NVIDIA Tesla modules, but again, the upcoming Kepler parts will probably leapfrog the W9000 in this area. The W9000 card draws 274 watts at peak load and its suggested retail price is $3,999.

For $2,400 less, the W8000 comes with nearly as much number-crunching capability (3.23 SP teraflops and 806 DP gigaflops), but just two-thirds the memory (4 GB) and bandwidth (176 GB/sec). The less muscular W7000 and W5000 represent the mid-range FirePro lineup. Both provide more than one SP teraflop and a token number of DP flops, but they lack ECC support. MSRP is $899 and $599, respectively.

AMD’s new APUs, the FirePro A300 and A320, are a different breed altogether. They represent the chipmaker’s first heterogeneous processors aimed at science and engineering, albeit only for the workstation market. Unlike the company’s previous APUs for desktops and laptops, these latest ones include a lot more GPU heft. That gives users something akin to a mid-range discrete GPU on the same chip as a quad-core CPU. The advantage here is that it’s much easier to share data between the two compute engines on the chip; there’s no need to be sending bytes back and forth across a relatively slow PCIe bus.

These new APUs aren’t computational powerhouses however. At 28nm, there’s just not enough room to lay down a lot of GPU silicon on the same die as a CPU with reasonable-sized memory caches. As a result, AMD is aiming these cards at 2D modeling and entry-level 3D modeling, rather than more demanding applications like CAE and medical imaging.

The 100 watt A300 delivers 736 SP gigaflops and 184 DP gigaflops, with the 65 watt A320 just a tad slower at 693 SP gigaflops and 173 DP gigaflops. From the standpoint of double precision performance, that’s not much better than a top bin Sandy Bridge CPU, but with the APU, of course, you get the added functionality of graphics support, not to mention a lot more SP flops. If you need more compute than the A300 or A320 can provide, AMD offers what they call Discrete Compute Offload, which enables the devices to work with a separate FirePro GPU running in parallel.

For HPC users, perhaps the most interesting news here is that AMD is gearing up its GPU computing portfolio, both for its discrete and heterogeneous lines. What we’re likely seeing are the precursors to server-capable GPUs and APUs that will be aimed at HPC and related types pf applications. In all likelihood, the server GPUs will come first, perhaps as early as this year.

But with NVIDIA’s dominance of the HPC accelerator market and Intel’s imminent entry into that space with its upcoming Knights Corner coprocessor, AMD will have an uphill battle against a couple of formidable competitors. The company’s natural advantage in CPU-GPU integration may eventually give them a leg up when transistor geometries allow teraflop graphics engines to inhabit the same die with multicore CPUs. But until then, AMD will have to play catch up.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

NSF Awards $10M to Extend Chameleon Cloud Testbed Project

September 19, 2017

The National Science Foundation has awarded a second phase, $10 million grant to the Chameleon cloud computing testbed project led by University of Chicago with partners at the Texas Advanced Computing Center (TACC), Ren Read more…

By John Russell

NERSC Simulations Shed Light on Fusion Reaction Turbulence

September 19, 2017

Understanding fusion reactions in detail – particularly plasma turbulence – is critical to the effort to bring fusion power to reality. Recent work including roughly 70 million hours of compute time at the National E Read more…

Kathy Yelick Charts the Promise and Progress of Exascale Science

September 15, 2017

On Friday, Sept. 8, Kathy Yelick of Lawrence Berkeley National Laboratory and the University of California, Berkeley, delivered the keynote address on “Breakthrough Science at the Exascale” at the ACM Europe Conferen Read more…

By Tiffany Trader

HPE Extreme Performance Solutions

HPE Prepares Customers for Success with the HPC Software Portfolio

High performance computing (HPC) software is key to harnessing the full power of HPC environments. Development and management tools enable IT departments to streamline installation and maintenance of their systems as well as create, optimize, and run their HPC applications. Read more…

U of Illinois, NCSA Launch First US Nanomanufacturing Node

September 14, 2017

The University of Illinois at Urbana-Champaign together with the National Center for Supercomputing Applications (NCSA) have launched the United States's first computational node aimed at the development of nanomanufactu Read more…

By Tiffany Trader

Kathy Yelick Charts the Promise and Progress of Exascale Science

September 15, 2017

On Friday, Sept. 8, Kathy Yelick of Lawrence Berkeley National Laboratory and the University of California, Berkeley, delivered the keynote address on “Breakt Read more…

By Tiffany Trader

DARPA Pledges Another $300 Million for Post-Moore’s Readiness

September 14, 2017

The Defense Advanced Research Projects Agency (DARPA) launched a giant funding effort to ensure the United States can sustain the pace of electronic innovation vital to both a flourishing economy and a secure military. Under the banner of the Electronics Resurgence Initiative (ERI), some $500-$800 million will be invested in post-Moore’s Law technologies. Read more…

By Tiffany Trader

IBM Breaks Ground for Complex Quantum Chemistry

September 14, 2017

IBM has reported the use of a novel algorithm to simulate BeH2 (beryllium-hydride) on a quantum computer. This is the largest molecule so far simulated on a quantum computer. The technique, which used six qubits of a seven-qubit system, is an important step forward and may suggest an approach to simulating ever larger molecules. Read more…

By John Russell

Cubes, Culture, and a New Challenge: Trish Damkroger Talks about Life at Intel—and Why HPC Matters More Than Ever

September 13, 2017

Trish Damkroger wasn’t looking to change jobs when she attended SC15 in Austin, Texas. Capping a 15-year career within Department of Energy (DOE) laboratories, she was acting Associate Director for Computation at Lawrence Livermore National Laboratory (LLNL). Her mission was to equip the lab’s scientists and research partners with resources that would advance their cutting-edge work... Read more…

By Jan Rowell

EU Funds 20 Million Euro ARM+FPGA Exascale Project

September 7, 2017

At the Barcelona Supercomputer Centre on Wednesday (Sept. 6), 16 partners gathered to launch the EuroEXA project, which invests €20 million over three-and-a-half years into exascale-focused research and development. Led by the Horizon 2020 program, EuroEXA picks up the banner of a triad of partner projects — ExaNeSt, EcoScale and ExaNoDe — building on their work... Read more…

By Tiffany Trader

MIT-IBM Watson AI Lab Targets Algorithms, AI Physics

September 7, 2017

Investment continues to flow into artificial intelligence research, especially in key areas such as AI algorithms that promise to move the technology from speci Read more…

By George Leopold

Need Data Science CyberInfrastructure? Check with RENCI’s xDCI Concierge

September 6, 2017

For about a year the Renaissance Computing Institute (RENCI) has been assembling best practices and open source components around data-driven scientific researc Read more…

By John Russell

IBM Advances Web-based Quantum Programming

September 5, 2017

IBM Research is pairing its Jupyter-based Data Science Experience notebook environment with its cloud-based quantum computer, IBM Q, in hopes of encouraging a new class of entrepreneurial user to solve intractable problems that even exceed the capabilities of the best AI systems. Read more…

By Alex Woodie

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

NERSC Scales Scientific Deep Learning to 15 Petaflops

August 28, 2017

A collaborative effort between Intel, NERSC and Stanford has delivered the first 15-petaflops deep learning software running on HPC platforms and is, according Read more…

By Rob Farber

Russian Researchers Claim First Quantum-Safe Blockchain

May 25, 2017

The Russian Quantum Center today announced it has overcome the threat of quantum cryptography by creating the first quantum-safe blockchain, securing cryptocurrencies like Bitcoin, along with classified government communications and other sensitive digital transfers. Read more…

By Doug Black

Oracle Layoffs Reportedly Hit SPARC and Solaris Hard

September 7, 2017

Oracle’s latest layoffs have many wondering if this is the end of the line for the SPARC processor and Solaris OS development. As reported by multiple sources Read more…

By John Russell

Google Debuts TPU v2 and will Add to Google Cloud

May 25, 2017

Not long after stirring attention in the deep learning/AI community by revealing the details of its Tensor Processing Unit (TPU), Google last week announced the Read more…

By John Russell

Six Exascale PathForward Vendors Selected; DoE Providing $258M

June 15, 2017

The much-anticipated PathForward awards for hardware R&D in support of the Exascale Computing Project were announced today with six vendors selected – AMD Read more…

By John Russell

Top500 Results: Latest List Trends and What’s in Store

June 19, 2017

Greetings from Frankfurt and the 2017 International Supercomputing Conference where the latest Top500 list has just been revealed. Although there were no major Read more…

By Tiffany Trader

Leading Solution Providers

IBM Clears Path to 5nm with Silicon Nanosheets

June 5, 2017

Two years since announcing the industry’s first 7nm node test chip, IBM and its research alliance partners GlobalFoundries and Samsung have developed a proces Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in Read more…

By Tiffany Trader

Google Releases Deeplearn.js to Further Democratize Machine Learning

August 17, 2017

Spreading the use of machine learning tools is one of the goals of Google’s PAIR (People + AI Research) initiative, which was introduced in early July. Last w Read more…

By John Russell

EU Funds 20 Million Euro ARM+FPGA Exascale Project

September 7, 2017

At the Barcelona Supercomputer Centre on Wednesday (Sept. 6), 16 partners gathered to launch the EuroEXA project, which invests €20 million over three-and-a-half years into exascale-focused research and development. Led by the Horizon 2020 program, EuroEXA picks up the banner of a triad of partner projects — ExaNeSt, EcoScale and ExaNoDe — building on their work... Read more…

By Tiffany Trader

Cray Moves to Acquire the Seagate ClusterStor Line

July 28, 2017

This week Cray announced that it is picking up Seagate's ClusterStor HPC storage array business for an undisclosed sum. "In short we're effectively transitioning the bulk of the ClusterStor product line to Cray," said CEO Peter Ungaro. Read more…

By Tiffany Trader

Amazon Debuts New AMD-based GPU Instances for Graphics Acceleration

September 12, 2017

Last week Amazon Web Services (AWS) streaming service, AppStream 2.0, introduced a new GPU instance called Graphics Design intended to accelerate graphics. The Read more…

By John Russell

GlobalFoundries: 7nm Chips Coming in 2018, EUV in 2019

June 13, 2017

GlobalFoundries has formally announced that its 7nm technology is ready for customer engagement with product tape outs expected for the first half of 2018. The Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This