Intel Parts the Curtains on Xeon Phi… A Little Bit

By Michael Feldman

August 28, 2012

As Intel’s Xeon Phi processor family gets ready to debut later this year, the chipmaker continues to reveal some of the details of its first manycore offering.  Although the company isn’t yet ready to talk speeds and feeds, this week they did divulge some of their design decisions that they believe will make the Xeon Phi coprocessor shine as an HPC accelerator. The new revelations were presented on Tuesday at the IEEE-sponsored Hot Chips conference in Cupertino, California.

The Hot Chips presentation was manned by George Chrysos, chief architect of “Knights Corner,” the code name for Intel’s first Xeon Phi product.  This fall, new chip is scheduled to debut in supercomputers, most notably the 10-petaflop “Stampede” system at the Texas Advanced Computing Center.  Although Knights Corner silicon will act as a coprocessors to the Xeon CPUs in that system, they will represents 80 percent of the total flops.

HPCwire talked with Chrysos (before Hot Chips) to get a preview of what he’d be talking about.  In essence, Intel is divulging some of the architectural details of the core and interconnect design, but is not releasing core counts, processor frequency, or memory bandwidth. That information will be forthcoming at the official product launch, which is more than likely to occur during the Supercomputing Conference (SC12) in November.

The major design goal of the Knights Corner microarchitecture was to pack a lot of number-crunching capability into a very power-efficient package. They did this by gluing a big vector processor onto a bare-bones x86 core.  In fact, according to Chrysos, only two percent of the Knights Corner die is dedicated to decoding x86 instructions.  The majority of the silicon real estate is devoted to the L1 and L2 caches, the memory I/O, and of course, the vector unit.

With regard to the latter, the 512-bit vector unit is the largest ever developed by Intel. Each one can dispatch 8 double precision or 16 single precision SIMD operations (integer or floating point) per clock cycle.  That’s twice as many as can be delivered by the latest x86 CPUs — the Intel Xeon Sandy Bridge and AMD Bulldozer processors.  And since there will be 50-plus cores on Knights Corner, we’re talking over 400 double precision flops per cycle. Even on a 2 GHz processor, that works out to 800 gigaflops. But since Intel is using its latest 22nm technology process, you know they’re going to be much more aggressive than that.

It’s more than just extra-wide vectors though  Chrysos says the design also incorporates other features optimized for HPC-type workloads.  In particular, they added a special math accelerator they call the Extended Map Unit (EMU), which does polynomial approximations of transcendent functions like square roots, reciprocals, exponents, and so.  The idea is to speed up execution of these functions in hardware.  According to Chrysos, it’s the first EMU for an x86-based processor.

The Knights Corner vector unit also includes a scatter-gather capability, another first for the x86 line. Scatter-gather , which is sometime referred to as vector addressing or vector I/O, is a way to optimize storing and fetching of data from non-contiguous memory addresses. It’s especially useful for processing sparse matrices, which is fundamental to many HPC applications.

As far as memory bandwidth, Chrysos didn’t volunteer information in that regard, other than to say the memory subsystem on Knights Corner will be “very competitive.” Multiple memory controllers will be sprinkled among the cores, and, in such a way as to optimize speed and latency.

Which bring us to the Knights Corner cache setup. Like traditional CPUs, the new chip will incorporate cache coherency in hardware, but in this case, extended to handle a manycore environment. On Knights Corner, L2 cache is 512 KB per core — twice the size of those on the Sandy Bridge Xeons. On top of that they’ve added a translation lookaside buffer (TLB) to speed address translation, tag directories (TDs) to snoop across all of the cores’ L2 caches, and a Dcache capability to simultaneously load and store 512 bits per clock cycle. Finally, Intel included a prefetch capability for the L2, to boost the performance when data is streaming from memory.

All of these capabilities are designed to keep the cores well fed with data, and, as much as possible, avoid the much larger amount of time and energy required to access main memory off the chip. According to Chrysos, based on the Spec FP 2006 benchmarks, these cache features in aggregate have increased per core performance by an average of 80 percent.

For CPU-type architectures, cache coherency is pretty much business as usual. This is quite different from the GPU, which relies less on caches and more on maximizing bandwidth for memory streaming and lots of cores to hide latency. Although the general-purpose GPUs, especially the latest from NVIDIA, have cache hierarchies, they are not globally coherent.

NVIDIA, though, does have a more flexible approach. For example, its L1 cache on Fermi, and now Kepler, is user configurable and can be split between L1 cache and scratchpad memory. The L2 cache is just shared across all the streaming multiprocessors, which are roughly analogous to CPU cores. If coherency is to be maintained on the GPU it must be done in software.

Intel believes it has a “fundamental advantage” in its hardware-based cache coherency, since not only does it minimize the more expensive memory I/O, but it is also easier to program. Along those same lines, Intel will continue to promote x86 programmability as a big advantage of Knights Corner compared to the more specialized CUDA- or OpenCL-based approaches of GPUs. All of this is about to tested on the HPC battlefield later this year. Stay tuned.

 


 

Related Articles

Tracking Xeon Phi’s Roots

Intel Will Ship Knights Corner Chip in 2012

Intel Releases Knights Corner ISA, Lays Groundwork for MIC Launch

 

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “pre-exascale” award), parsed out additional information ab Read more…

By Tiffany Trader

Tsinghua Crowned Eight-Time Student Cluster Champions at ISC

June 22, 2017

Always a hard-fought competition, the Student Cluster Competition awards were announced Wednesday, June 21, at the ISC High Performance Conference 2017. Amid whoops and hollers from the crowd, Thomas Sterling presented t Read more…

By Kim McMahon

GPUs, Power9, Figure Prominently in IBM’s Bet on Weather Forecasting

June 22, 2017

IBM jumped into the weather forecasting business roughly a year and a half ago by purchasing The Weather Company. This week at ISC 2017, Big Blue rolled out plans to push deeper into climate science and develop more gran Read more…

By John Russell

Intersect 360 at ISC: HPC Industry at $44B by 2021

June 22, 2017

The care, feeding and sustained growth of the HPC industry increasingly is in the hands of the commercial market sector – in particular, it’s the hyperscale companies and their embrace of AI and deep learning – tha Read more…

By Doug Black

HPE Extreme Performance Solutions

Creating a Roadmap for HPC Innovation at ISC 2017

In an era where technological advancements are driving innovation to every sector, and powering major economic and scientific breakthroughs, high performance computing (HPC) is crucial to tackle the challenges of today and tomorrow. Read more…

At ISC – Goh on Go: Humans Can’t Scale, the Data-Centric Learning Machine Can

June 22, 2017

I've seen the future this week at ISC, it’s on display in prototype or Powerpoint form, and it’s going to dumbfound you. The future is an AI neural network designed to emulate and compete with the human brain. In thi Read more…

By Doug Black

Cray Brings AI and HPC Together on Flagship Supers

June 20, 2017

Cray took one more step toward the convergence of big data and high performance computing (HPC) today when it announced that it’s adding a full suite of big data and artificial intelligence software to its top-of-the-l Read more…

By Alex Woodie

AMD Charges Back into the Datacenter and HPC Workflows with EPYC Processor

June 20, 2017

AMD is charging back into the enterprise datacenter and select HPC workflows with its new EPYC 7000 processor line, code-named Naples, announced today at a “global” launch event in Austin TX. In many ways it was a fu Read more…

By John Russell

Hyperion: Deep Learning, AI Helping Drive Healthy HPC Industry Growth

June 20, 2017

To be at the ISC conference in Frankfurt this week is to experience deep immersion in deep learning. Users want to learn about it, vendors want to talk about it, analysts and journalists want to report on it. Deep learni Read more…

By Doug Black

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Tsinghua Crowned Eight-Time Student Cluster Champions at ISC

June 22, 2017

Always a hard-fought competition, the Student Cluster Competition awards were announced Wednesday, June 21, at the ISC High Performance Conference 2017. Amid wh Read more…

By Kim McMahon

GPUs, Power9, Figure Prominently in IBM’s Bet on Weather Forecasting

June 22, 2017

IBM jumped into the weather forecasting business roughly a year and a half ago by purchasing The Weather Company. This week at ISC 2017, Big Blue rolled out pla Read more…

By John Russell

Intersect 360 at ISC: HPC Industry at $44B by 2021

June 22, 2017

The care, feeding and sustained growth of the HPC industry increasingly is in the hands of the commercial market sector – in particular, it’s the hyperscale Read more…

By Doug Black

At ISC – Goh on Go: Humans Can’t Scale, the Data-Centric Learning Machine Can

June 22, 2017

I've seen the future this week at ISC, it’s on display in prototype or Powerpoint form, and it’s going to dumbfound you. The future is an AI neural network Read more…

By Doug Black

Cray Brings AI and HPC Together on Flagship Supers

June 20, 2017

Cray took one more step toward the convergence of big data and high performance computing (HPC) today when it announced that it’s adding a full suite of big d Read more…

By Alex Woodie

AMD Charges Back into the Datacenter and HPC Workflows with EPYC Processor

June 20, 2017

AMD is charging back into the enterprise datacenter and select HPC workflows with its new EPYC 7000 processor line, code-named Naples, announced today at a “g Read more…

By John Russell

Hyperion: Deep Learning, AI Helping Drive Healthy HPC Industry Growth

June 20, 2017

To be at the ISC conference in Frankfurt this week is to experience deep immersion in deep learning. Users want to learn about it, vendors want to talk about it Read more…

By Doug Black

Quantum Bits: D-Wave and VW; Google Quantum Lab; IBM Expands Access

March 21, 2017

For a technology that’s usually characterized as far off and in a distant galaxy, quantum computing has been steadily picking up steam. Just how close real-wo Read more…

By John Russell

Trump Budget Targets NIH, DOE, and EPA; No Mention of NSF

March 16, 2017

President Trump’s proposed U.S. fiscal 2018 budget issued today sharply cuts science spending while bolstering military spending as he promised during the cam Read more…

By John Russell

HPC Compiler Company PathScale Seeks Life Raft

March 23, 2017

HPCwire has learned that HPC compiler company PathScale has fallen on difficult times and is asking the community for help or actively seeking a buyer for its a Read more…

By Tiffany Trader

Google Pulls Back the Covers on Its First Machine Learning Chip

April 6, 2017

This week Google released a report detailing the design and performance characteristics of the Tensor Processing Unit (TPU), its custom ASIC for the inference Read more…

By Tiffany Trader

CPU-based Visualization Positions for Exascale Supercomputing

March 16, 2017

In this contributed perspective piece, Intel’s Jim Jeffers makes the case that CPU-based visualization is now widely adopted and as such is no longer a contrarian view, but is rather an exascale requirement. Read more…

By Jim Jeffers, Principal Engineer and Engineering Leader, Intel

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Nvidia’s Mammoth Volta GPU Aims High for AI, HPC

May 10, 2017

At Nvidia's GPU Technology Conference (GTC17) in San Jose, Calif., this morning, CEO Jensen Huang announced the company's much-anticipated Volta architecture a Read more…

By Tiffany Trader

Facebook Open Sources Caffe2; Nvidia, Intel Rush to Optimize

April 18, 2017

From its F8 developer conference in San Jose, Calif., today, Facebook announced Caffe2, a new open-source, cross-platform framework for deep learning. Caffe2 is the successor to Caffe, the deep learning framework developed by Berkeley AI Research and community contributors. Read more…

By Tiffany Trader

Leading Solution Providers

MIT Mathematician Spins Up 220,000-Core Google Compute Cluster

April 21, 2017

On Thursday, Google announced that MIT math professor and computational number theorist Andrew V. Sutherland had set a record for the largest Google Compute Engine (GCE) job. Sutherland ran the massive mathematics workload on 220,000 GCE cores using preemptible virtual machine instances. Read more…

By Tiffany Trader

Google Debuts TPU v2 and will Add to Google Cloud

May 25, 2017

Not long after stirring attention in the deep learning/AI community by revealing the details of its Tensor Processing Unit (TPU), Google last week announced the Read more…

By John Russell

US Supercomputing Leaders Tackle the China Question

March 15, 2017

Joint DOE-NSA report responds to the increased global pressures impacting the competitiveness of U.S. supercomputing. Read more…

By Tiffany Trader

Groq This: New AI Chips to Give GPUs a Run for Deep Learning Money

April 24, 2017

CPUs and GPUs, move over. Thanks to recent revelations surrounding Google’s new Tensor Processing Unit (TPU), the computing world appears to be on the cusp of Read more…

By Alex Woodie

Russian Researchers Claim First Quantum-Safe Blockchain

May 25, 2017

The Russian Quantum Center today announced it has overcome the threat of quantum cryptography by creating the first quantum-safe blockchain, securing cryptocurrencies like Bitcoin, along with classified government communications and other sensitive digital transfers. Read more…

By Doug Black

DOE Supercomputer Achieves Record 45-Qubit Quantum Simulation

April 13, 2017

In order to simulate larger and larger quantum systems and usher in an age of “quantum supremacy,” researchers are stretching the limits of today’s most advanced supercomputers. Read more…

By Tiffany Trader

Messina Update: The US Path to Exascale in 16 Slides

April 26, 2017

Paul Messina, director of the U.S. Exascale Computing Project, provided a wide-ranging review of ECP’s evolving plans last week at the HPC User Forum. Read more…

By John Russell

Knights Landing Processor with Omni-Path Makes Cloud Debut

April 18, 2017

HPC cloud specialist Rescale is partnering with Intel and HPC resource provider R Systems to offer first-ever cloud access to Xeon Phi "Knights Landing" processors. The infrastructure is based on the 68-core Intel Knights Landing processor with integrated Omni-Path fabric (the 7250F Xeon Phi). Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This