Intel Weaves Strategy To Put Interconnect Fabrics On Chip

By Michael Feldman

September 10, 2012

Intel has begun to formulate a strategy that will integrate fabric controllers with its server processors. According to Raj Hazra, general manager of the Technical Computing unit at Intel, the company is planning to use the recently acquired IP from Cray, QLogic and Fulcrum to deliver chips that put what is essentially a NIC onto the processor die. In a recent conversation with Hazra, he outlined their new fabric interconnect strategy.

Intel apparently started thinking along these lines at least a year ago when the company began collecting interconnect technology in earnest. In July 2011, the chipmaker acquired Fulcrum, a maker of Ethernet switch chips. Six months later, it bought QLogic’s InfiniBand adapter and switch business. And then three months after that, Intel brought Cray’s interconnect IP and expertise on board. With the three technologies in hand, the chipmaker now believes it has the makings for a wider play.

As with other types of processor integration, the idea is to deliver more capability, in this case, greater performance, scalability and energy efficiency. According to Hazra, as the scope of distributed computing systems has grown from HPC to the cloud and beyond, interconnect fabrics like Ethernet and InfiniBand have become much more intimate with the processor, or at least, would like to. These fabrics are now an integral part of the systems and applications they connect. “We are seeing the role of the fabric far less like a network, in a loosely coupled sense, and far more like a system bus at the datacenter level,” Hazra told HPCwire.

In that sense, a fabric is just an extension of the system bus and the memory and storage hierarchies that it glues together. But as compute density per server increases, these fabric can become communication bottlenecks. This is especially true in large-scale systems, like supercomputers and datacenter-sized clouds, where the number of nodes can run into the thousands. But even in smaller-scale HPC clusters or data appliances, performance can be limited by interconnect bandwidth and latency.

Putting the fabric controller on the die with the processor could go a long way toward alleviating some of the performance and power issues. For example, giving the controller a direct line to the CPU could deliver more bandwidth along with less latency. And since the system I/O interface (PCIe) would no longer be needed to drive the fabric, power could be significantly reduced — on the order of tens of watts per server. Also, from a system point of view, placing the controller on the processor would eliminate yet another component on the server motherboard, reducing system price and complexity.

The proximity of the fabric logic to the CPU could also make it easier to provide intelligent data movement (exploiting data locality, doing smart prefetching, etc.), inasmuch as programming an on-chip controller is far simpler than managing an external third-party device. In the HPC space, it could, for example, drive a greater adoption of Partitioned Global Address Space (PGAS) languages, which present distributed memory as a unified address space. With more intimate control of the fabric, it should be easier for system software to support such a model.

It’s not just for high performance computing though. Intel is looking to apply fabric integration across all its datacenter offerings (Xeon, Xeon Phi, and Atom processors), which encompass HPC/supercomputers, clouds, enterprise appliances and microservers. Essentially any chip destined for a multi-node system is fair game. Each application area has different requirements — bandwidth, latency, scalability, security, and so on — so it’s unlikely, for example, that Intel will use Cray’s supercomputing interconnect technology in its Atoms and Xeons destined for microservers, or Fulcrum’s 10 GigE IP for exascale-grade Xeons.

What will make all this integration possible is Moore’s Law, the continual shrinking of transistor geometries that enables extra logic and storage to be laid down on the die. At this point, nobody enforces Moore’s Law better than Intel, and combined with their interconnect collection as well as their extensive set of parallel software tools and libraries, the chipmaker is in a rather unique position to bring this new architecture to fruition.

Making the interconnect logic a first-class citizen on the processor, rather than just an I/O device would be a huge paradigm shift for the server market. If successfully executed at Intel, other chip vendors will be forced to follow suit. (AMD is likely already conjuring up something similar with the fabric technology it acquired from SeaMicro.) Meanwhile makers of discrete NICs and host adapter silicon will have to rethink their strategy, perhaps allying themselves with other chipmakers to offer competitive products.

Intel is not ready to talk about specific product plans and timelines, but since Hazra is charged with developing this architecture, it’s reasonable to assume that the processors aimed at HPC will get a good deal of the initial attention. And we probably won’t have to wait for exascale systems at the end of the decade to see some of these fabric controller-equipped chips in the field. According to Hazra, the first such hardware should show up prior to the first exaflop supercomputer deployments.

“Without this integration, many of the challenges around having a scalable, extensible fabric architecture is not going to be possible,” he says. “We think the time has come when this is not only possible, but our intent is to drive this aggressively to make it possible.”

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