This is the first of several articles discussing the various technologies and design criteria used for HPC systems. Building computer systems of any sort, but especially very large systems, is somewhat akin to the process an apartment real-estate developer goes through. The developer has to have an idea of what the final product will look like, its compelling features, and the go-to-market strategy.
Do they build each unit the same, or provide some level of heterogeneity, different floor plans. Do they construct one monolithic building or a village with walkways? What level of customization, if any, should be permitted?
In contemporary HPC design we face similar decision-making. Do we build tightly coupled systems, emphasizing floating point and internode bandwidth, or do we build nodes with extensive multi-threading that can randomly reference data sets? In either case, we always need to scale out as much as possible.
And finally we have the marketing picture of the system under a beautiful clouded-blue sky with mountains or lake in the background. Since we intend to market to international buyers, we have to figure out which languages to support on our marketing web site. Almost forgot: do we sell these systems outright or base our financial model on a timeshare condo arrangement?
Is programming an HPC system equivalent to the above? For example, there’s a choice to be made between extending existing languages or creating new ones. Are the languages domain specific unique to a particular application space, like HTML, Verilog or SQL; or do we add new features to existing languages, like global address space primitives, such as UPC?
For this initial piece, we will discuss these design issues in the context of “big data.” It’s seems reasonable to suggest that building an exaOPS system for big data systems is different from building an exaFLOPS machine for technical applications. But is it? While clearly the applications are different, that doesn’t necessarily mean the underlying architecture has to be as well.
The following table compares some of the characteristics of OPS versus FLOPS at the node level.
Examining the attributes listed above would initially lead one to the observation that there are substantive differences between the two. However, looking at a hardware logic design reveals a somewhat different perspective. Both systems need as much physical memory as can be directly supported, subject to cooling and power constraints. Both systems also would like as much real memory bandwidth as possible.
For both systems, the logic used by the ALU’s tends to be minimal. Thus the amount of actual space used for a custom design floating point ALU is relatively small. This is especially true when one considers that 64×64 integer multiplication is an often-used primitive address calculation in big data and HPC applications. In many cases, integer multiplication is part of the design of an IEEE floating point ALU.
If we dig a little deeper, we come to the conclusion that the major gating item is sustained memory bandwidth and latency. We have to determine how long it takes to access an operand and how many can be accessed at once, Given a specific memory architecture, we need to figure out the best machine state model for computation. Is it compiler managed-registers using the RAM that would normally be associated with a L3 cache, or keep scaling a floor plan similar to the one below?
The overriding issue is efficiency. We can argue incessantly about this. As the datasets get bigger, the locality of references — temporal and spatial — decreases and the randomness of references increase. What are the solutions?
In HPC classic, programmers (and some compilers) generate code that explicitly blocks the data sets into cache, typically the L2 private or L3 shared cache. This technique tends to work quite well for traditional HPC applications. Its major deficiencies are the extra coding work and the lack of performance portability among different cache architectures.
Several techniques, especially the ones supported by the auto-tune capabilities of LAPACK, work quite well for many applications that manipulate dense matrices. Consequently, the memory systems are block-oriented and support is inherent in the memory controllers of all contemporary microprocessors.
For big data, however, accesses are relatively random, and this block approach tends not to work. As a function of the data structure — a tree, a graph, a string — different approaches are used to make memory references more efficient.
Additionally, for big data work, performance is measured in throughput of transactions or queries per second and not FLOPS. Coincidentally, perhaps, the optimal memory structure is HPC classic, meaning, highly interleaved, word-scatter/gather-oriented main memory. This was the approach used in Cray, Convex, Fujitsu, NEC, and Hitachi machines.
There is another interesting dynamic of cache- or register-based internal processor storage: power consumption and design complexity. While not immediately obvious, for a given amount of user-visible machine state, a cache has additional transistors for maintaining its transparency, which translates into additional power consumption.
For example, there is storage for tags and logic for the comparison of generated address tags with stored cache tags. There is additional logic required for the control of the cache. It is difficult to quantify the incremental power required, but it is incremental.
Another aspect of cache versus internal state, especially for big data, is the reference pattern. Random references have poor cache hit characteristics. But if the data can be blocked, then the hit rate increases substantially. The efficiency of managing large amounts of internal machine is proportional to the thread architecture.
We have to determine if we have lots of threads with reasonable size register sets, or a smaller number of threads, like a vector machine, with a large amount of machine state. The latter approach places a burden on physical memory design.
Attaching private L1 and L2 caches per core is relatively straightforward and scales as the number of cores increases. A shared L3 cache increases the complexity of the internal design. We need to trade off bandwidth, simultaneous accesses, and latency and cache coherency. The question that needs to asked is if we are better off using internal static RAM for compiler-managed data registers per core/thread.
Obviously both memory structures have their own cost/performance tradeoffs. A cache-based memory system tends to be more cost-effective, but of lower performance. The design of the memory subsystem is easier, given that off-the-shelf DRAM DIMMS are commercially available.
The HPC classic architecture results in higher performance and is applicable to a wider range of applications. The available memory bandwidth is more effectively used, and operands are only loaded and stored when needed; there is no block size to deal with.
In summary, this article discusses the single-node processor architecture for data-centric and conventional high performance computing. There are many similarities and many differences. The major divergence is in the main memory reference model and interface. Data caches were created decades ago, but it’s not clear if that this architecture is still optimal. Will Hybrid Memory Cube (HMC) and Processor in Memory (PIM) architectures make tradeoffs for newer designs that move away from the traditional memory designs? Time will tell.
The next article will discuss the design approaches for global interconnects.