Intel Brings Manycore x86 to Market with Knights Corner

By Michael Feldman

November 12, 2012

Intel Corp. officially made its entry into the manycore realm today as it debuted “Knights Corner,” the company’s first Xeon Phi coprocessor. The new products clock in at just over a teraflop, double precision, setting the stage for an HPC accelerator battle that will pit Intel against GPU makers NVIDIA and AMD. Both of those companies also released their latest HPC accelerators into the wild earlier today at the annual Supercomputing Conference in Salt Lake City.

The 22nm Knights Corner chips will initially be going into two Xeon Phi products: the 3120A and 5110P, both of which are PCIe cards outfitted with a single coprocessor and several gigabytes of GDDR5 memory. A pre-production part, the SE10P, is also in circulation, but will not be generally available.

FLOPS-wise, the two cards are rather similar. The 3120A delivers 1.003 double precision teraflops with 60 cores (1.053 GHZ), while the 5110P offers a skosh more, at 1.011 teraflops, but does so with just 57 cores that are clocked somewhat higher (1.1 GHz). The big difference is memory. The 5110P houses 8 GB and delivers 320 GB/sec of peak bandwidth; the 3120A, comes with 6 GB and 240 GB/sec of bandwidth.

The memory gap between the two cards defines their different application targets. The 3120A is aimed at compute-bound workloads, where the data can be keep locally on the card or, better yet, in on-chip cache. That makes it the device of choice for many applications in financial services, life sciences, and codes that rely a lot on linear algebra calculations.

For applications that lean more toward the data-intensive side of the spectrum, or that rely on streaming data, Intel will point you to the 5110P. There, the higher memory capacity and bandwidth will be better for apps like digital content creation, seismic modeling, and ray tracing.

There’s a significant difference in power consumption too. The 5110P draws 225 watts at peak load, while the 3120A is rated at 300 watts, which is going to limit its deployment in densely configured servers. Nevertheless, Intel says this latter card is the go-to product for situations where you want to maximize FLOPS per dollar. Intel’s recommended price is below $2,000 for this part, while the higher memory 5110P is being targeted at $2,649.

The two product also differ in cooling regimes. The P in the 5110P means it’s a passively cooled card, which is more convenient for servers, especially denser set-ups that are all the rage these days in HPC. The 3120A is actively cooled, so it would be more applicable to less densely configured servers and workstations. Intel also intends to offer a passively cooled 3100 part at some point.

The 5110P is shipping today, with general availability on January 28. The 3120A is scheduled for availability sometime in the first half of 2013.

The aforementioned SE10P has also been shipping for a while to satisfy early customers, namely TACC (The Texas Advanced Computing Center), for its 10-petaflop Stampede supercomputer. Stampede is already up and running, but apparently not at full capacity. The Linpack submission for the TOP500 had it at 4 peak petaflops (2.6 petaflops Linpack), which is less than half it’s final  FLOPS level.

According to Intel, the SE10P has essentially the same feature set as the 5110P, but it runs at 300 watts and with about 10 percent better peak memory bandwidth. As mentioned before, this part is not slated for general production, so it’s possible that the remainder of Stampede will be built out with the 5110P, or perhaps some other yet to be announced Xeon Phi.

Because the SE10P has been available for awhile, a lot of the benchmarks Intel is initially touting (including the ones mentioned here), are based on this card. The other two products shouldn’t be too far off though, especially the 5110P. For Linpack, Intel has clocked this pre-production part at 803 teraflops and DGEMM (double precision matrix multiply) at 883 teraflops, and SGEMM (single precision matrix multiply) at 1,860 gigaflops. STREAM Triad, which measures memory performance, checks in at 181 GB/sec with error correction (ECC) off and 175 GB/sec when it’s on. All those results are between two to three times better than that delivered by a 2-socket server equipped with Xeon E5-2670 (Sandy Bridge) CPUs.

In fact, Intel is telling customers that for parallel applications that can take advantage of the Xeon Phi’s vector capabilities, codes will generally see a 2X to 3X speedup when you drop in a Knights Corner coprocessor. For example, the chipmaker is reporting a 2.53X performance bump for a seismic imaging code, 2.52X for molecular dynamics, 2.27X for lattice QCD, 1.7X for a finite element solver, and 1.88X for ray tracing. There are a few outliers for certain single-precision financial codes: 10.75X for Black Scholes and 8.92X for Monte Carlo, thanks mainly to on-chip support for transcendental functions in the Xeon Phi platform.

Overall though, Intel is promising 2X to 3X speedups, and only for software that lends itself to parallelization and vectorization. According to Joe Curley, Intel’s director of marketing for the Data Center Group, that entails a relatively small portion of HPC applications. “But,” he says, “customers who have those applications are motivated to find ways to get performance breakthroughs.”

Intel has to thread the needle here. It can’t tout the Xeon Phi at the expense of its mainstream Xeon CPUs. The idea is to speed up applications or portions of applications that are out of reach for straight Xeons. But the chipmaker wants to sell you both products — one for maximizing single-threaded codes, the other for highly parallel, vector-intensive ones. That’s not really different from how NVIDIA has positioned its GPU accelerators relative to CPUs.

NVIDIA, though, is more aggressive about pointing to big performance increases over CPU-only platforms, more on the order of 5X to 30X and beyond. For its new K20X Tesla part announced earlier today, the GPU-maker is claiming a 7X performance advantage over to a Sandy Bridge Xeon. Although that makes it seem like the GPU competition is three times faster than Knights Corner, the NVIDIA comparison is GPU-to-CPU, while Intel prefers to match its coprocessor against two Xeons.

Nevertheless, NVIDIA’s K20 does top Knights Corner in both raw performance and performance per watt. The 235 watt K20X offers 1.31 double precision teraflops, while the 225 watt 5110P, at 1.011 teraflops, delivers 300 gigaflops less. Advantage NVIDIA.

It appears to be even more skewed for single precision FLOPS, where the K20X offers three times its double precision performance; for the Knights Corner, single precision appears to be just twice that of its double precision results.

On the other hand, the 5110P is top in memory capacity and bandwidth. At 8 GB and 320 GB/sec, respectively, this Knights Corner part outruns the K20X’s 6 GB and 250 GB/sec by a wide margin. For codes that are more data-bound than compute-bound, that could be a decided advantage.

But Intel believes its biggest hammer against GPUs is its programming environment. It allows developers to use the same Intel parallel compilers, libraries and tools they are using for their Xeon codes. Third-party development tools from CAPS enterprise, PGI, Rogue Wave, Allinea, NAG, and others also now include Xeon Phi support.

Intel also likes to point out that GPUs are best at speeding up data parallel apps, and a number of HPC applications do not map very well to that model. “An awful lot of scientific programs really don’t tolerate some of the limitations of explicit data parallelism,” Curley told HPCwire. “Codes can branch; codes can have a great deal of recursion in them; codes can be self-modifying; codes can use sparse irregular data sets. All of which can become vexing for explicitly data parallel architectures, and all of which run on the Intel Xeon Phi.”

That’s not to say it will be a snap to create high-performing Xeon Phi codes. You may be able get applications up and running in a matter of days via some simple code tweaks and a recompilation, but Xeon Phi represents a true throughput accelerator design, and trying to treat it as a manycore CPU, as Intel has sometimes implied, will probably not lead to accelerated applications.

The proof will be in the application pudding. At this point, NVIDIA and the CUDA faithful have a six-year head start in porting codes to HPC accelerators. Intel, though, is a force to be reckoned with, so if the chipmaker can garner enough enthusiasm on the software side, it could make up for lost time rather quickly.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

NSF Project Sets Up First Machine Learning Cyberinfrastructure – CHASE-CI

July 25, 2017

Earlier this month, the National Science Foundation issued a $1 million grant to Larry Smarr, director of Calit2, and a group of his colleagues to create a community infrastructure in support of machine learning research Read more…

By John Russell

DARPA Continues Investment in Post-Moore’s Technologies

July 24, 2017

The U.S. military long ago ceded dominance in electronics innovation to Silicon Valley, the DoD-backed powerhouse that has driven microelectronic generation for decades. With Moore's Law clearly running out of steam, the Read more…

By George Leopold

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in 2017 with scale-up production for enterprise datacenters and Read more…

By Tiffany Trader

HPE Extreme Performance Solutions

HPE Servers Deliver High Performance Remote Visualization

Whether generating seismic simulations, locating new productive oil reservoirs, or constructing complex models of the earth’s subsurface, energy, oil, and gas (EO&G) is a highly data-driven industry. Read more…

Trinity Supercomputer’s Haswell and KNL Partitions Are Merged

July 19, 2017

Trinity supercomputer’s two partitions – one based on Intel Xeon Haswell processors and the other on Xeon Phi Knights Landing – have been fully integrated are now available for use on classified work in the Nationa Read more…

By HPCwire Staff

NSF Project Sets Up First Machine Learning Cyberinfrastructure – CHASE-CI

July 25, 2017

Earlier this month, the National Science Foundation issued a $1 million grant to Larry Smarr, director of Calit2, and a group of his colleagues to create a comm Read more…

By John Russell

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in Read more…

By Tiffany Trader

Fujitsu Continues HPC, AI Push

July 19, 2017

Summer is well under way, but the so-called summertime slowdown, linked with hot temperatures and longer vacations, does not seem to have impacted Fujitsu's out Read more…

By Tiffany Trader

Researchers Use DNA to Store and Retrieve Digital Movie

July 18, 2017

From abacus to pencil and paper to semiconductor chips, the technology of computing has always been an ever-changing target. The human brain is probably the com Read more…

By John Russell

The Exascale FY18 Budget – The Next Step

July 17, 2017

On July 12, 2017, the U.S. federal budget for its Exascale Computing Initiative (ECI) took its next step forward. On that day, the full Appropriations Committee Read more…

By Alex R. Larzelere

Women in HPC Luncheon Shines Light on Female-Friendly Hiring Practices

July 13, 2017

The second annual Women in HPC luncheon was held on June 20, 2017, during the International Supercomputing Conference in Frankfurt, Germany. The luncheon provid Read more…

By Tiffany Trader

Satellite Advances, NSF Computation Power Rapid Mapping of Earth’s Surface

July 13, 2017

New satellite technologies have completely changed the game in mapping and geographical data gathering, reducing costs and placing a new emphasis on time series Read more…

By Ken Chiacchia and Tiffany Jolley

Intel Skylake: Xeon Goes from Chip to Platform

July 13, 2017

With yesterday’s New York unveiling of the new “Skylake” Xeon Scalable processors, Intel made multiple runs at multiple competitive threats and strategic Read more…

By Doug Black

Google Pulls Back the Covers on Its First Machine Learning Chip

April 6, 2017

This week Google released a report detailing the design and performance characteristics of the Tensor Processing Unit (TPU), its custom ASIC for the inference Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Quantum Bits: D-Wave and VW; Google Quantum Lab; IBM Expands Access

March 21, 2017

For a technology that’s usually characterized as far off and in a distant galaxy, quantum computing has been steadily picking up steam. Just how close real-wo Read more…

By John Russell

HPC Compiler Company PathScale Seeks Life Raft

March 23, 2017

HPCwire has learned that HPC compiler company PathScale has fallen on difficult times and is asking the community for help or actively seeking a buyer for its a Read more…

By Tiffany Trader

Trump Budget Targets NIH, DOE, and EPA; No Mention of NSF

March 16, 2017

President Trump’s proposed U.S. fiscal 2018 budget issued today sharply cuts science spending while bolstering military spending as he promised during the cam Read more…

By John Russell

CPU-based Visualization Positions for Exascale Supercomputing

March 16, 2017

In this contributed perspective piece, Intel’s Jim Jeffers makes the case that CPU-based visualization is now widely adopted and as such is no longer a contrarian view, but is rather an exascale requirement. Read more…

By Jim Jeffers, Principal Engineer and Engineering Leader, Intel

Nvidia’s Mammoth Volta GPU Aims High for AI, HPC

May 10, 2017

At Nvidia's GPU Technology Conference (GTC17) in San Jose, Calif., this morning, CEO Jensen Huang announced the company's much-anticipated Volta architecture a Read more…

By Tiffany Trader

Facebook Open Sources Caffe2; Nvidia, Intel Rush to Optimize

April 18, 2017

From its F8 developer conference in San Jose, Calif., today, Facebook announced Caffe2, a new open-source, cross-platform framework for deep learning. Caffe2 is the successor to Caffe, the deep learning framework developed by Berkeley AI Research and community contributors. Read more…

By Tiffany Trader

Leading Solution Providers

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

Russian Researchers Claim First Quantum-Safe Blockchain

May 25, 2017

The Russian Quantum Center today announced it has overcome the threat of quantum cryptography by creating the first quantum-safe blockchain, securing cryptocurrencies like Bitcoin, along with classified government communications and other sensitive digital transfers. Read more…

By Doug Black

MIT Mathematician Spins Up 220,000-Core Google Compute Cluster

April 21, 2017

On Thursday, Google announced that MIT math professor and computational number theorist Andrew V. Sutherland had set a record for the largest Google Compute Engine (GCE) job. Sutherland ran the massive mathematics workload on 220,000 GCE cores using preemptible virtual machine instances. Read more…

By Tiffany Trader

Google Debuts TPU v2 and will Add to Google Cloud

May 25, 2017

Not long after stirring attention in the deep learning/AI community by revealing the details of its Tensor Processing Unit (TPU), Google last week announced the Read more…

By John Russell

Groq This: New AI Chips to Give GPUs a Run for Deep Learning Money

April 24, 2017

CPUs and GPUs, move over. Thanks to recent revelations surrounding Google’s new Tensor Processing Unit (TPU), the computing world appears to be on the cusp of Read more…

By Alex Woodie

Six Exascale PathForward Vendors Selected; DoE Providing $258M

June 15, 2017

The much-anticipated PathForward awards for hardware R&D in support of the Exascale Computing Project were announced today with six vendors selected – AMD Read more…

By John Russell

Top500 Results: Latest List Trends and What’s in Store

June 19, 2017

Greetings from Frankfurt and the 2017 International Supercomputing Conference where the latest Top500 list has just been revealed. Although there were no major Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This