Intel Brings Manycore x86 to Market with Knights Corner

By Michael Feldman

November 12, 2012

Intel Corp. officially made its entry into the manycore realm today as it debuted “Knights Corner,” the company’s first Xeon Phi coprocessor. The new products clock in at just over a teraflop, double precision, setting the stage for an HPC accelerator battle that will pit Intel against GPU makers NVIDIA and AMD. Both of those companies also released their latest HPC accelerators into the wild earlier today at the annual Supercomputing Conference in Salt Lake City.

The 22nm Knights Corner chips will initially be going into two Xeon Phi products: the 3120A and 5110P, both of which are PCIe cards outfitted with a single coprocessor and several gigabytes of GDDR5 memory. A pre-production part, the SE10P, is also in circulation, but will not be generally available.

FLOPS-wise, the two cards are rather similar. The 3120A delivers 1.003 double precision teraflops with 60 cores (1.053 GHZ), while the 5110P offers a skosh more, at 1.011 teraflops, but does so with just 57 cores that are clocked somewhat higher (1.1 GHz). The big difference is memory. The 5110P houses 8 GB and delivers 320 GB/sec of peak bandwidth; the 3120A, comes with 6 GB and 240 GB/sec of bandwidth.

The memory gap between the two cards defines their different application targets. The 3120A is aimed at compute-bound workloads, where the data can be keep locally on the card or, better yet, in on-chip cache. That makes it the device of choice for many applications in financial services, life sciences, and codes that rely a lot on linear algebra calculations.

For applications that lean more toward the data-intensive side of the spectrum, or that rely on streaming data, Intel will point you to the 5110P. There, the higher memory capacity and bandwidth will be better for apps like digital content creation, seismic modeling, and ray tracing.

There’s a significant difference in power consumption too. The 5110P draws 225 watts at peak load, while the 3120A is rated at 300 watts, which is going to limit its deployment in densely configured servers. Nevertheless, Intel says this latter card is the go-to product for situations where you want to maximize FLOPS per dollar. Intel’s recommended price is below $2,000 for this part, while the higher memory 5110P is being targeted at $2,649.

The two product also differ in cooling regimes. The P in the 5110P means it’s a passively cooled card, which is more convenient for servers, especially denser set-ups that are all the rage these days in HPC. The 3120A is actively cooled, so it would be more applicable to less densely configured servers and workstations. Intel also intends to offer a passively cooled 3100 part at some point.

The 5110P is shipping today, with general availability on January 28. The 3120A is scheduled for availability sometime in the first half of 2013.

The aforementioned SE10P has also been shipping for a while to satisfy early customers, namely TACC (The Texas Advanced Computing Center), for its 10-petaflop Stampede supercomputer. Stampede is already up and running, but apparently not at full capacity. The Linpack submission for the TOP500 had it at 4 peak petaflops (2.6 petaflops Linpack), which is less than half it’s final  FLOPS level.

According to Intel, the SE10P has essentially the same feature set as the 5110P, but it runs at 300 watts and with about 10 percent better peak memory bandwidth. As mentioned before, this part is not slated for general production, so it’s possible that the remainder of Stampede will be built out with the 5110P, or perhaps some other yet to be announced Xeon Phi.

Because the SE10P has been available for awhile, a lot of the benchmarks Intel is initially touting (including the ones mentioned here), are based on this card. The other two products shouldn’t be too far off though, especially the 5110P. For Linpack, Intel has clocked this pre-production part at 803 teraflops and DGEMM (double precision matrix multiply) at 883 teraflops, and SGEMM (single precision matrix multiply) at 1,860 gigaflops. STREAM Triad, which measures memory performance, checks in at 181 GB/sec with error correction (ECC) off and 175 GB/sec when it’s on. All those results are between two to three times better than that delivered by a 2-socket server equipped with Xeon E5-2670 (Sandy Bridge) CPUs.

In fact, Intel is telling customers that for parallel applications that can take advantage of the Xeon Phi’s vector capabilities, codes will generally see a 2X to 3X speedup when you drop in a Knights Corner coprocessor. For example, the chipmaker is reporting a 2.53X performance bump for a seismic imaging code, 2.52X for molecular dynamics, 2.27X for lattice QCD, 1.7X for a finite element solver, and 1.88X for ray tracing. There are a few outliers for certain single-precision financial codes: 10.75X for Black Scholes and 8.92X for Monte Carlo, thanks mainly to on-chip support for transcendental functions in the Xeon Phi platform.

Overall though, Intel is promising 2X to 3X speedups, and only for software that lends itself to parallelization and vectorization. According to Joe Curley, Intel’s director of marketing for the Data Center Group, that entails a relatively small portion of HPC applications. “But,” he says, “customers who have those applications are motivated to find ways to get performance breakthroughs.”

Intel has to thread the needle here. It can’t tout the Xeon Phi at the expense of its mainstream Xeon CPUs. The idea is to speed up applications or portions of applications that are out of reach for straight Xeons. But the chipmaker wants to sell you both products — one for maximizing single-threaded codes, the other for highly parallel, vector-intensive ones. That’s not really different from how NVIDIA has positioned its GPU accelerators relative to CPUs.

NVIDIA, though, is more aggressive about pointing to big performance increases over CPU-only platforms, more on the order of 5X to 30X and beyond. For its new K20X Tesla part announced earlier today, the GPU-maker is claiming a 7X performance advantage over to a Sandy Bridge Xeon. Although that makes it seem like the GPU competition is three times faster than Knights Corner, the NVIDIA comparison is GPU-to-CPU, while Intel prefers to match its coprocessor against two Xeons.

Nevertheless, NVIDIA’s K20 does top Knights Corner in both raw performance and performance per watt. The 235 watt K20X offers 1.31 double precision teraflops, while the 225 watt 5110P, at 1.011 teraflops, delivers 300 gigaflops less. Advantage NVIDIA.

It appears to be even more skewed for single precision FLOPS, where the K20X offers three times its double precision performance; for the Knights Corner, single precision appears to be just twice that of its double precision results.

On the other hand, the 5110P is top in memory capacity and bandwidth. At 8 GB and 320 GB/sec, respectively, this Knights Corner part outruns the K20X’s 6 GB and 250 GB/sec by a wide margin. For codes that are more data-bound than compute-bound, that could be a decided advantage.

But Intel believes its biggest hammer against GPUs is its programming environment. It allows developers to use the same Intel parallel compilers, libraries and tools they are using for their Xeon codes. Third-party development tools from CAPS enterprise, PGI, Rogue Wave, Allinea, NAG, and others also now include Xeon Phi support.

Intel also likes to point out that GPUs are best at speeding up data parallel apps, and a number of HPC applications do not map very well to that model. “An awful lot of scientific programs really don’t tolerate some of the limitations of explicit data parallelism,” Curley told HPCwire. “Codes can branch; codes can have a great deal of recursion in them; codes can be self-modifying; codes can use sparse irregular data sets. All of which can become vexing for explicitly data parallel architectures, and all of which run on the Intel Xeon Phi.”

That’s not to say it will be a snap to create high-performing Xeon Phi codes. You may be able get applications up and running in a matter of days via some simple code tweaks and a recompilation, but Xeon Phi represents a true throughput accelerator design, and trying to treat it as a manycore CPU, as Intel has sometimes implied, will probably not lead to accelerated applications.

The proof will be in the application pudding. At this point, NVIDIA and the CUDA faithful have a six-year head start in porting codes to HPC accelerators. Intel, though, is a force to be reckoned with, so if the chipmaker can garner enough enthusiasm on the software side, it could make up for lost time rather quickly.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

ExxonMobil, NCSA, Cray Scale Reservoir Simulation to 700,000+ Processors

February 17, 2017

In a scaling breakthrough for oil and gas discovery, ExxonMobil geoscientists report they have harnessed the power of 717,000 processors – the equivalent of 22,000 32-processor computers – to run complex oil and gas reservoir simulation models. Read more…

By Doug Black

TSUBAME3.0 Points to Future HPE Pascal-NVLink-OPA Server

February 17, 2017

Since our initial coverage of the TSUBAME3.0 supercomputer yesterday, more details have come to light on this innovative project. Of particular interest is a new board design for NVLink-equipped Pascal P100 GPUs that will create another entrant to the space currently occupied by Nvidia's DGX-1 system, IBM's "Minsky" platform and the Supermicro SuperServer (1028GQ-TXR). Read more…

By Tiffany Trader

Tokyo Tech’s TSUBAME3.0 Will Be First HPE-SGI Super

February 16, 2017

In a press event Friday afternoon local time in Japan, Tokyo Institute of Technology (Tokyo Tech) announced its plans for the TSUBAME3.0 supercomputer, which will be Japan’s “fastest AI supercomputer,” Read more…

By Tiffany Trader

Drug Developers Use Google Cloud HPC in the Fight Against ALS

February 16, 2017

Within the haystack of a lethal disease such as ALS (amyotrophic lateral sclerosis / Lou Gehrig’s Disease) there exists, somewhere, the needle that will pierce this therapy-resistant affliction. Read more…

By Doug Black

HPE Extreme Performance Solutions

Object Storage is the Ideal Storage Method for CME Companies

The communications, media, and entertainment (CME) sector is experiencing a massive paradigm shift driven by rising data volumes and the demand for high-performance data analytics. Read more…

Weekly Twitter Roundup (Feb. 16, 2017)

February 16, 2017

Here at HPCwire, we aim to keep the HPC community apprised of the most relevant and interesting news items that get tweeted throughout the week. Read more…

By Thomas Ayres

Alexander Named Dep. Dir. of Brookhaven Computational Initiative

February 15, 2017

Francis Alexander, a physicist with extensive management and leadership experience in computational science research, has been named Deputy Director of the Computational Science Initiative at the U.S. Read more…

Here’s What a Neural Net Looks Like On the Inside

February 15, 2017

Ever wonder what the inside of a machine learning model looks like? Today Graphcore released fascinating images that show how the computational graph concept maps to a new graph processor and graph programming framework it’s creating. Read more…

By Alex Woodie

Azure Edges AWS in Linpack Benchmark Study

February 15, 2017

The “when will clouds be ready for HPC” question has ebbed and flowed for years. Read more…

By John Russell

TSUBAME3.0 Points to Future HPE Pascal-NVLink-OPA Server

February 17, 2017

Since our initial coverage of the TSUBAME3.0 supercomputer yesterday, more details have come to light on this innovative project. Of particular interest is a new board design for NVLink-equipped Pascal P100 GPUs that will create another entrant to the space currently occupied by Nvidia's DGX-1 system, IBM's "Minsky" platform and the Supermicro SuperServer (1028GQ-TXR). Read more…

By Tiffany Trader

Tokyo Tech’s TSUBAME3.0 Will Be First HPE-SGI Super

February 16, 2017

In a press event Friday afternoon local time in Japan, Tokyo Institute of Technology (Tokyo Tech) announced its plans for the TSUBAME3.0 supercomputer, which will be Japan’s “fastest AI supercomputer,” Read more…

By Tiffany Trader

Drug Developers Use Google Cloud HPC in the Fight Against ALS

February 16, 2017

Within the haystack of a lethal disease such as ALS (amyotrophic lateral sclerosis / Lou Gehrig’s Disease) there exists, somewhere, the needle that will pierce this therapy-resistant affliction. Read more…

By Doug Black

Azure Edges AWS in Linpack Benchmark Study

February 15, 2017

The “when will clouds be ready for HPC” question has ebbed and flowed for years. Read more…

By John Russell

Is Liquid Cooling Ready to Go Mainstream?

February 13, 2017

Lost in the frenzy of SC16 was a substantial rise in the number of vendors showing server oriented liquid cooling technologies. Three decades ago liquid cooling was pretty much the exclusive realm of the Cray-2 and IBM mainframe class products. That’s changing. We are now seeing an emergence of x86 class server products with exotic plumbing technology ranging from Direct-to-Chip to servers and storage completely immersed in a dielectric fluid. Read more…

By Steve Campbell

Cray Posts Best-Ever Quarter, Visibility Still Limited

February 10, 2017

On its Wednesday earnings call, Cray announced the largest revenue quarter in the company’s history and the second-highest revenue year. Read more…

By Tiffany Trader

HPC Cloud Startup Launches ‘App Store’ for HPC Workflows

February 9, 2017

“Civilization advances by extending the number of important operations which we can perform without thinking about them,” Read more…

By Tiffany Trader

Intel and Trump Announce $7B for Fab 42 Targeting 7nm

February 8, 2017

In what may be an attempt by President Trump to reset his turbulent relationship with the high tech industry, he and Intel CEO Brian Krzanich today announced plans to invest more than $7 billion to complete Fab 42. Read more…

By John Russell

For IBM/OpenPOWER: Success in 2017 = (Volume) Sales

January 11, 2017

To a large degree IBM and the OpenPOWER Foundation have done what they said they would – assembling a substantial and growing ecosystem and bringing Power-based products to market, all in about three years. Read more…

By John Russell

US, China Vie for Supercomputing Supremacy

November 14, 2016

The 48th edition of the TOP500 list is fresh off the presses and while there is no new number one system, as previously teased by China, there are a number of notable entrants from the US and around the world and significant trends to report on. Read more…

By Tiffany Trader

Lighting up Aurora: Behind the Scenes at the Creation of the DOE’s Upcoming 200 Petaflops Supercomputer

December 1, 2016

In April 2015, U.S. Department of Energy Undersecretary Franklin Orr announced that Intel would be the prime contractor for Aurora: Read more…

By Jan Rowell

D-Wave SC16 Update: What’s Bo Ewald Saying These Days

November 18, 2016

Tucked in a back section of the SC16 exhibit hall, quantum computing pioneer D-Wave has been talking up its new 2000-qubit processor announced in September. Forget for a moment the criticism sometimes aimed at D-Wave. This small Canadian company has sold several machines including, for example, ones to Lockheed and NASA, and has worked with Google on mapping machine learning problems to quantum computing. In July Los Alamos National Laboratory took possession of a 1000-quibit D-Wave 2X system that LANL ordered a year ago around the time of SC15. Read more…

By John Russell

Enlisting Deep Learning in the War on Cancer

December 7, 2016

Sometime in Q2 2017 the first ‘results’ of the Joint Design of Advanced Computing Solutions for Cancer (JDACS4C) will become publicly available according to Rick Stevens. He leads one of three JDACS4C pilot projects pressing deep learning (DL) into service in the War on Cancer. Read more…

By John Russell

HPC Startup Advances Auto-Parallelization’s Promise

January 23, 2017

The shift from single core to multicore hardware has made finding parallelism in codes more important than ever, but that hasn’t made the task of parallel programming any easier. Read more…

By Tiffany Trader

IBM Wants to be “Red Hat” of Deep Learning

January 26, 2017

IBM today announced the addition of TensorFlow and Chainer deep learning frameworks to its PowerAI suite of deep learning tools, which already includes popular offerings such as Caffe, Theano, and Torch. Read more…

By John Russell

CPU Benchmarking: Haswell Versus POWER8

June 2, 2015

With OpenPOWER activity ramping up and IBM’s prominent role in the upcoming DOE machines Summit and Sierra, it’s a good time to look at how the IBM POWER CPU stacks up against the x86 Xeon Haswell CPU from Intel. Read more…

By Tiffany Trader

Leading Solution Providers

Nvidia Sees Bright Future for AI Supercomputing

November 23, 2016

Graphics chipmaker Nvidia made a strong showing at SC16 in Salt Lake City last week. Read more…

By Tiffany Trader

BioTeam’s Berman Charts 2017 HPC Trends in Life Sciences

January 4, 2017

Twenty years ago high performance computing was nearly absent from life sciences. Today it’s used throughout life sciences and biomedical research. Genomics and the data deluge from modern lab instruments are the main drivers, but so is the longer-term desire to perform predictive simulation in support of Precision Medicine (PM). There’s even a specialized life sciences supercomputer, ‘Anton’ from D.E. Shaw Research, and the Pittsburgh Supercomputing Center is standing up its second Anton 2 and actively soliciting project proposals. There’s a lot going on. Read more…

By John Russell

Container App ‘Singularity’ Eases Scientific Computing

October 20, 2016

HPC container platform Singularity is just six months out from its 1.0 release but already is making inroads across the HPC research landscape. It's in use at Lawrence Berkeley National Laboratory (LBNL), where Singularity founder Gregory Kurtzer has worked in the High Performance Computing Services (HPCS) group for 16 years. Read more…

By Tiffany Trader

Dell Knights Landing Machine Sets New STAC Records

November 2, 2016

The Securities Technology Analysis Center, commonly known as STAC, has released a new report characterizing the performance of the Knight Landing-based Dell PowerEdge C6320p server on the STAC-A2 benchmarking suite, widely used by the financial services industry to test and evaluate computing platforms. The Dell machine has set new records for both the baseline Greeks benchmark and the large Greeks benchmark. Read more…

By Tiffany Trader

IDG to Be Bought by Chinese Investors; IDC to Spin Out HPC Group

January 19, 2017

US-based publishing and investment firm International Data Group, Inc. (IDG) will be acquired by a pair of Chinese investors, China Oceanwide Holdings Group Co., Ltd. Read more…

By Tiffany Trader

What Knights Landing Is Not

June 18, 2016

As we get ready to launch the newest member of the Intel Xeon Phi family, code named Knights Landing, it is natural that there be some questions and potentially some confusion. Read more…

By James Reinders, Intel

KNUPATH Hermosa-based Commercial Boards Expected in Q1 2017

December 15, 2016

Last June tech start-up KnuEdge emerged from stealth mode to begin spreading the word about its new processor and fabric technology that’s been roughly a decade in the making. Read more…

By John Russell

Intel and Trump Announce $7B for Fab 42 Targeting 7nm

February 8, 2017

In what may be an attempt by President Trump to reset his turbulent relationship with the high tech industry, he and Intel CEO Brian Krzanich today announced plans to invest more than $7 billion to complete Fab 42. Read more…

By John Russell

  • arrow
  • Click Here for More Headlines
  • arrow
Share This