Intel Brings Manycore x86 to Market with Knights Corner

By Michael Feldman

November 12, 2012

Intel Corp. officially made its entry into the manycore realm today as it debuted “Knights Corner,” the company’s first Xeon Phi coprocessor. The new products clock in at just over a teraflop, double precision, setting the stage for an HPC accelerator battle that will pit Intel against GPU makers NVIDIA and AMD. Both of those companies also released their latest HPC accelerators into the wild earlier today at the annual Supercomputing Conference in Salt Lake City.

The 22nm Knights Corner chips will initially be going into two Xeon Phi products: the 3120A and 5110P, both of which are PCIe cards outfitted with a single coprocessor and several gigabytes of GDDR5 memory. A pre-production part, the SE10P, is also in circulation, but will not be generally available.

FLOPS-wise, the two cards are rather similar. The 3120A delivers 1.003 double precision teraflops with 60 cores (1.053 GHZ), while the 5110P offers a skosh more, at 1.011 teraflops, but does so with just 57 cores that are clocked somewhat higher (1.1 GHz). The big difference is memory. The 5110P houses 8 GB and delivers 320 GB/sec of peak bandwidth; the 3120A, comes with 6 GB and 240 GB/sec of bandwidth.

The memory gap between the two cards defines their different application targets. The 3120A is aimed at compute-bound workloads, where the data can be keep locally on the card or, better yet, in on-chip cache. That makes it the device of choice for many applications in financial services, life sciences, and codes that rely a lot on linear algebra calculations.

For applications that lean more toward the data-intensive side of the spectrum, or that rely on streaming data, Intel will point you to the 5110P. There, the higher memory capacity and bandwidth will be better for apps like digital content creation, seismic modeling, and ray tracing.

There’s a significant difference in power consumption too. The 5110P draws 225 watts at peak load, while the 3120A is rated at 300 watts, which is going to limit its deployment in densely configured servers. Nevertheless, Intel says this latter card is the go-to product for situations where you want to maximize FLOPS per dollar. Intel’s recommended price is below $2,000 for this part, while the higher memory 5110P is being targeted at $2,649.

The two product also differ in cooling regimes. The P in the 5110P means it’s a passively cooled card, which is more convenient for servers, especially denser set-ups that are all the rage these days in HPC. The 3120A is actively cooled, so it would be more applicable to less densely configured servers and workstations. Intel also intends to offer a passively cooled 3100 part at some point.

The 5110P is shipping today, with general availability on January 28. The 3120A is scheduled for availability sometime in the first half of 2013.

The aforementioned SE10P has also been shipping for a while to satisfy early customers, namely TACC (The Texas Advanced Computing Center), for its 10-petaflop Stampede supercomputer. Stampede is already up and running, but apparently not at full capacity. The Linpack submission for the TOP500 had it at 4 peak petaflops (2.6 petaflops Linpack), which is less than half it’s final  FLOPS level.

According to Intel, the SE10P has essentially the same feature set as the 5110P, but it runs at 300 watts and with about 10 percent better peak memory bandwidth. As mentioned before, this part is not slated for general production, so it’s possible that the remainder of Stampede will be built out with the 5110P, or perhaps some other yet to be announced Xeon Phi.

Because the SE10P has been available for awhile, a lot of the benchmarks Intel is initially touting (including the ones mentioned here), are based on this card. The other two products shouldn’t be too far off though, especially the 5110P. For Linpack, Intel has clocked this pre-production part at 803 teraflops and DGEMM (double precision matrix multiply) at 883 teraflops, and SGEMM (single precision matrix multiply) at 1,860 gigaflops. STREAM Triad, which measures memory performance, checks in at 181 GB/sec with error correction (ECC) off and 175 GB/sec when it’s on. All those results are between two to three times better than that delivered by a 2-socket server equipped with Xeon E5-2670 (Sandy Bridge) CPUs.

In fact, Intel is telling customers that for parallel applications that can take advantage of the Xeon Phi’s vector capabilities, codes will generally see a 2X to 3X speedup when you drop in a Knights Corner coprocessor. For example, the chipmaker is reporting a 2.53X performance bump for a seismic imaging code, 2.52X for molecular dynamics, 2.27X for lattice QCD, 1.7X for a finite element solver, and 1.88X for ray tracing. There are a few outliers for certain single-precision financial codes: 10.75X for Black Scholes and 8.92X for Monte Carlo, thanks mainly to on-chip support for transcendental functions in the Xeon Phi platform.

Overall though, Intel is promising 2X to 3X speedups, and only for software that lends itself to parallelization and vectorization. According to Joe Curley, Intel’s director of marketing for the Data Center Group, that entails a relatively small portion of HPC applications. “But,” he says, “customers who have those applications are motivated to find ways to get performance breakthroughs.”

Intel has to thread the needle here. It can’t tout the Xeon Phi at the expense of its mainstream Xeon CPUs. The idea is to speed up applications or portions of applications that are out of reach for straight Xeons. But the chipmaker wants to sell you both products — one for maximizing single-threaded codes, the other for highly parallel, vector-intensive ones. That’s not really different from how NVIDIA has positioned its GPU accelerators relative to CPUs.

NVIDIA, though, is more aggressive about pointing to big performance increases over CPU-only platforms, more on the order of 5X to 30X and beyond. For its new K20X Tesla part announced earlier today, the GPU-maker is claiming a 7X performance advantage over to a Sandy Bridge Xeon. Although that makes it seem like the GPU competition is three times faster than Knights Corner, the NVIDIA comparison is GPU-to-CPU, while Intel prefers to match its coprocessor against two Xeons.

Nevertheless, NVIDIA’s K20 does top Knights Corner in both raw performance and performance per watt. The 235 watt K20X offers 1.31 double precision teraflops, while the 225 watt 5110P, at 1.011 teraflops, delivers 300 gigaflops less. Advantage NVIDIA.

It appears to be even more skewed for single precision FLOPS, where the K20X offers three times its double precision performance; for the Knights Corner, single precision appears to be just twice that of its double precision results.

On the other hand, the 5110P is top in memory capacity and bandwidth. At 8 GB and 320 GB/sec, respectively, this Knights Corner part outruns the K20X’s 6 GB and 250 GB/sec by a wide margin. For codes that are more data-bound than compute-bound, that could be a decided advantage.

But Intel believes its biggest hammer against GPUs is its programming environment. It allows developers to use the same Intel parallel compilers, libraries and tools they are using for their Xeon codes. Third-party development tools from CAPS enterprise, PGI, Rogue Wave, Allinea, NAG, and others also now include Xeon Phi support.

Intel also likes to point out that GPUs are best at speeding up data parallel apps, and a number of HPC applications do not map very well to that model. “An awful lot of scientific programs really don’t tolerate some of the limitations of explicit data parallelism,” Curley told HPCwire. “Codes can branch; codes can have a great deal of recursion in them; codes can be self-modifying; codes can use sparse irregular data sets. All of which can become vexing for explicitly data parallel architectures, and all of which run on the Intel Xeon Phi.”

That’s not to say it will be a snap to create high-performing Xeon Phi codes. You may be able get applications up and running in a matter of days via some simple code tweaks and a recompilation, but Xeon Phi represents a true throughput accelerator design, and trying to treat it as a manycore CPU, as Intel has sometimes implied, will probably not lead to accelerated applications.

The proof will be in the application pudding. At this point, NVIDIA and the CUDA faithful have a six-year head start in porting codes to HPC accelerators. Intel, though, is a force to be reckoned with, so if the chipmaker can garner enough enthusiasm on the software side, it could make up for lost time rather quickly.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

AWS Embraces FPGAs, ‘Elastic’ GPUs

December 2, 2016

A new instance type rolled out this week by Amazon Web Services is based on customizable field programmable gate arrays that promise to strike a balance between performance and cost as emerging workloads create requirements often unmet by general-purpose processors. Read more…

By George Leopold

AWS Launches Massive 100 Petabyte ‘Sneakernet’

December 1, 2016

Amazon Web Services now offers a way to move data into its cloud by the truckload. Read more…

By Tiffany Trader

Weekly Twitter Roundup (Dec. 1, 2016)

December 1, 2016

Here at HPCwire, we aim to keep the HPC community apprised of the most relevant and interesting news items that get tweeted throughout the week. Read more…

By Thomas Ayres

HPC Career Notes (Dec. 2016)

December 1, 2016

In this monthly feature, we’ll keep you up-to-date on the latest career developments for individuals in the high performance computing community. Read more…

By Thomas Ayres

Lighting up Aurora: Behind the Scenes at the Creation of the DOE’s Upcoming 200 Petaflops Supercomputer

December 1, 2016

In April 2015, U.S. Department of Energy Undersecretary Franklin Orr announced that Intel would be the prime contractor for Aurora: Read more…

By Jan Rowell

IBM and NSF Computing Pioneer Erich Bloch Dies at 91

November 30, 2016

Erich Bloch, a computational pioneer whose competitive zeal and commercial bent helped transform the National Science Foundation while he was its director, died last Friday at age 91. Bloch was a productive force to be reckoned. During his long stint at IBM prior to joining NSF Bloch spearheaded development of the “Stretch” supercomputer and IBM’s phenomenally successful System/360. Read more…

By John Russell

Pioneering Programmers Awarded Presidential Medal of Freedom

November 30, 2016

In an awards ceremony on November 22, President Barack Obama recognized 21 recipients with the Presidential Medal of Freedom, the Nation’s highest civilian honor. Read more…

By Tiffany Trader

Seagate-led SAGE Project Delivers Update on Exascale Goals

November 29, 2016

Roughly a year and a half after its launch, the SAGE exascale storage project led by Seagate has delivered a substantive interim report – Data Storage for Extreme Scale. Read more…

By John Russell

AWS Launches Massive 100 Petabyte ‘Sneakernet’

December 1, 2016

Amazon Web Services now offers a way to move data into its cloud by the truckload. Read more…

By Tiffany Trader

Lighting up Aurora: Behind the Scenes at the Creation of the DOE’s Upcoming 200 Petaflops Supercomputer

December 1, 2016

In April 2015, U.S. Department of Energy Undersecretary Franklin Orr announced that Intel would be the prime contractor for Aurora: Read more…

By Jan Rowell

Seagate-led SAGE Project Delivers Update on Exascale Goals

November 29, 2016

Roughly a year and a half after its launch, the SAGE exascale storage project led by Seagate has delivered a substantive interim report – Data Storage for Extreme Scale. Read more…

By John Russell

Nvidia Sees Bright Future for AI Supercomputing

November 23, 2016

Graphics chipmaker Nvidia made a strong showing at SC16 in Salt Lake City last week. Read more…

By Tiffany Trader

HPE-SGI to Tackle Exascale and Enterprise Targets

November 22, 2016

At first blush, and maybe second blush too, Hewlett Packard Enterprise’s (HPE) purchase of SGI seems like an unambiguous win-win. SGI’s advanced shared memory technology, its popular UV product line (Hanna), deep vertical market expertise, and services-led go-to-market capability all give HPE a leg up in its drive to remake itself. Bear in mind HPE came into existence just a year ago with the split of Hewlett-Packard. The computer landscape, including HPC, is shifting with still unclear consequences. One wonders who’s next on the deal block following Dell’s recent merger with EMC. Read more…

By John Russell

Intel Details AI Hardware Strategy for Post-GPU Age

November 21, 2016

Last week at SC16, Intel revealed its product roadmap for embedding its processors with key capabilities and attributes needed to take artificial intelligence (AI) to the next level. Read more…

By Alex Woodie

SC Says Farewell to Salt Lake City, See You in Denver

November 18, 2016

After an intense four-day flurry of activity (and a cold snap that brought some actual snow flurries), the SC16 show floor closed yesterday (Thursday) and the always-extensive technical program wound down today. Read more…

By Tiffany Trader

D-Wave SC16 Update: What’s Bo Ewald Saying These Days

November 18, 2016

Tucked in a back section of the SC16 exhibit hall, quantum computing pioneer D-Wave has been talking up its new 2000-qubit processor announced in September. Forget for a moment the criticism sometimes aimed at D-Wave. This small Canadian company has sold several machines including, for example, ones to Lockheed and NASA, and has worked with Google on mapping machine learning problems to quantum computing. In July Los Alamos National Laboratory took possession of a 1000-quibit D-Wave 2X system that LANL ordered a year ago around the time of SC15. Read more…

By John Russell

Why 2016 Is the Most Important Year in HPC in Over Two Decades

August 23, 2016

In 1994, two NASA employees connected 16 commodity workstations together using a standard Ethernet LAN and installed open-source message passing software that allowed their number-crunching scientific application to run on the whole “cluster” of machines as if it were a single entity. Read more…

By Vincent Natoli, Stone Ridge Technology

IBM Advances Against x86 with Power9

August 30, 2016

After offering OpenPower Summit attendees a limited preview in April, IBM is unveiling further details of its next-gen CPU, Power9, which the tech mainstay is counting on to regain market share ceded to rival Intel. Read more…

By Tiffany Trader

AWS Beats Azure to K80 General Availability

September 30, 2016

Amazon Web Services has seeded its cloud with Nvidia Tesla K80 GPUs to meet the growing demand for accelerated computing across an increasingly-diverse range of workloads. The P2 instance family is a welcome addition for compute- and data-focused users who were growing frustrated with the performance limitations of Amazon's G2 instances, which are backed by three-year-old Nvidia GRID K520 graphics cards. Read more…

By Tiffany Trader

Think Fast – Is Neuromorphic Computing Set to Leap Forward?

August 15, 2016

Steadily advancing neuromorphic computing technology has created high expectations for this fundamentally different approach to computing. Read more…

By John Russell

The Exascale Computing Project Awards $39.8M to 22 Projects

September 7, 2016

The Department of Energy’s Exascale Computing Project (ECP) hit an important milestone today with the announcement of its first round of funding, moving the nation closer to its goal of reaching capable exascale computing by 2023. Read more…

By Tiffany Trader

HPE Gobbles SGI for Larger Slice of $11B HPC Pie

August 11, 2016

Hewlett Packard Enterprise (HPE) announced today that it will acquire rival HPC server maker SGI for $7.75 per share, or about $275 million, inclusive of cash and debt. The deal ends the seven-year reprieve that kept the SGI banner flying after Rackable Systems purchased the bankrupt Silicon Graphics Inc. for $25 million in 2009 and assumed the SGI brand. Bringing SGI into its fold bolsters HPE's high-performance computing and data analytics capabilities and expands its position... Read more…

By Tiffany Trader

ARM Unveils Scalable Vector Extension for HPC at Hot Chips

August 22, 2016

ARM and Fujitsu today announced a scalable vector extension (SVE) to the ARMv8-A architecture intended to enhance ARM capabilities in HPC workloads. Fujitsu is the lead silicon partner in the effort (so far) and will use ARM with SVE technology in its post K computer, Japan’s next flagship supercomputer planned for the 2020 timeframe. This is an important incremental step for ARM, which seeks to push more aggressively into mainstream and HPC server markets. Read more…

By John Russell

IBM Debuts Power8 Chip with NVLink and Three New Systems

September 8, 2016

Not long after revealing more details about its next-gen Power9 chip due in 2017, IBM today rolled out three new Power8-based Linux servers and a new version of its Power8 chip featuring Nvidia’s NVLink interconnect. Read more…

By John Russell

Leading Solution Providers

Vectors: How the Old Became New Again in Supercomputing

September 26, 2016

Vector instructions, once a powerful performance innovation of supercomputing in the 1970s and 1980s became an obsolete technology in the 1990s. But like the mythical phoenix bird, vector instructions have arisen from the ashes. Here is the history of a technology that went from new to old then back to new. Read more…

By Lynd Stringer

US, China Vie for Supercomputing Supremacy

November 14, 2016

The 48th edition of the TOP500 list is fresh off the presses and while there is no new number one system, as previously teased by China, there are a number of notable entrants from the US and around the world and significant trends to report on. Read more…

By Tiffany Trader

Intel Launches Silicon Photonics Chip, Previews Next-Gen Phi for AI

August 18, 2016

At the Intel Developer Forum, held in San Francisco this week, Intel Senior Vice President and General Manager Diane Bryant announced the launch of Intel's Silicon Photonics product line and teased a brand-new Phi product, codenamed "Knights Mill," aimed at machine learning workloads. Read more…

By Tiffany Trader

CPU Benchmarking: Haswell Versus POWER8

June 2, 2015

With OpenPOWER activity ramping up and IBM’s prominent role in the upcoming DOE machines Summit and Sierra, it’s a good time to look at how the IBM POWER CPU stacks up against the x86 Xeon Haswell CPU from Intel. Read more…

By Tiffany Trader

Beyond von Neumann, Neuromorphic Computing Steadily Advances

March 21, 2016

Neuromorphic computing – brain inspired computing – has long been a tantalizing goal. The human brain does with around 20 watts what supercomputers do with megawatts. And power consumption isn’t the only difference. Fundamentally, brains ‘think differently’ than the von Neumann architecture-based computers. While neuromorphic computing progress has been intriguing, it has still not proven very practical. Read more…

By John Russell

Dell EMC Engineers Strategy to Democratize HPC

September 29, 2016

The freshly minted Dell EMC division of Dell Technologies is on a mission to take HPC mainstream with a strategy that hinges on engineered solutions, beginning with a focus on three industry verticals: manufacturing, research and life sciences. "Unlike traditional HPC where everybody bought parts, assembled parts and ran the workloads and did iterative engineering, we want folks to focus on time to innovation and let us worry about the infrastructure," said Jim Ganthier, senior vice president, validated solutions organization at Dell EMC Converged Platforms Solution Division. Read more…

By Tiffany Trader

Container App ‘Singularity’ Eases Scientific Computing

October 20, 2016

HPC container platform Singularity is just six months out from its 1.0 release but already is making inroads across the HPC research landscape. It's in use at Lawrence Berkeley National Laboratory (LBNL), where Singularity founder Gregory Kurtzer has worked in the High Performance Computing Services (HPCS) group for 16 years. Read more…

By Tiffany Trader

Micron, Intel Prepare to Launch 3D XPoint Memory

August 16, 2016

Micron Technology used last week’s Flash Memory Summit to roll out its new line of 3D XPoint memory technology jointly developed with Intel while demonstrating the technology in solid-state drives. Micron claimed its Quantx line delivers PCI Express (PCIe) SSD performance with read latencies at less than 10 microseconds and writes at less than 20 microseconds. Read more…

By George Leopold

  • arrow
  • Click Here for More Headlines
  • arrow
Share This