Polish HPC Consortium Boosts Prospects for Local Scientists

By Nicole Hemsoth

January 2, 2013

Poland is not usually thought of as a supercomputing powerhouse. Until recently, most of the local research and academic centers housed only modest-sized HPC clusters for Polish researchers. That is now changing with the POWIEW project, a consortium devoted to bringing world-class high performance computing to the nation’s scientists.

POWIEW provides five state-of-the art systems, based on the latest processor technology from Intel, AMD, IBM, and NVIDIA. The machines are spread across the consortium’s three member organizations: the Interdisciplinary Centre for Mathematical and Computational Modeling (ICM) in Warsaw, Krakow’s Academic Computer Centre (CYFRONET), and the Poznan Supercomputing and Networking Center (PSNC).

We asked Maciej Filocha, POWIEW’s project manager and director of its HPC division, to describe the impetus behind the organization and how they serve local researchers and scientists.

HPCwire: Can you describe the mission of POWIEW and the rationale for developing an indigenous supercomputing project for Poland?

Maciej Filocha: The POWIEW project sets up a unified strategy concept for the HPC development in Poland addressing research and academia. It encompasses a program of significant computational infrastructure enhancement, associated R&D programs and graduate and postgraduate education.

Since the early 2000s, the Polish HPC ecosystem was dominated by capacity-level cluster solutions — still relevant for many scientists, but obviously less so for “real” large-scale parallelism. To ensure competitiveness and attractiveness of Polish research organizations, local computational infrastructure was to be enhanced accordingly.

HPCwire: How do Polish scientists and researchers view the significance of HPC for their work?

Filocha: The POWIEW consortium consists of three leading research and academic HPC centers, founded about 20 years ago. From the beginning, the number of users has been growing and includes representatives of “classical” computational and life sciences as well as material sciences, engineering and environmental sciences.

HPCwire: What’s the level of funding for the project and where does it come from?

Filocha: The project is founded by the EU from the Innovative Economy Programme (85 percent), complemented by domestic sources (15 percent), with total budget of about 23 million euros (17 million USD). This covers not only acquisition and deployment of new computing systems but also R&D activities related to porting and optimization of selected codes for new architectures and general enabling actions.

HPCwire: What supercomputers are currently up and running at POWIEW, and how are they being used?

Filocha: The POWIEW Project focuses on two major HPC application areas: massively parallel processing (MPP) that delivers high scalability in fine-grained parallelism and symmetric multiprocessing for intensively coarse-grain parallel computational applications.

For the MPP class, the Blue Gene/P solution was chosen and has been running for almost two years with a full system load. The Blue Gene/P system is maintained by the CM) in Warsaw. This architecture is particularly useful by material science and life science researchers for its performance with high scalability on MPI applications. The system is also heavily used by neuroscientists where it enables simulations of large neural networks with reasonable performance. Most of the jobs running on the Blue Gene/P utilize a few thousand CPU cores.

For the second class of systems two solutions were identified: the IBM Power775 system installed at ICM in Warsaw and the SGI Altix UV SMP machine at the PSNC in Poznan. Both systems use the fat-node approach with the SGI UV implementing “true” SMP — one super node — while the Power775 represents a cluster of super nodes.

The Power775 machine is currently in operation for almost one year. It is used for the most demanding workloads, including high resolution atmosphere studies for weather predictions and very large cosmological simulations. The system has proven its high performance for memory-intensive and computing-intensive tasks.

The SGI machine in Poznan, being also a PRACE Tier-1 site, is the only SMP system of comparable size in Poland. It is used for memory-intensive tasks including reservoir modeling and complex simulations in astrophysics.

As a third technology choice, hardware-accelerated clusters have been identified. Both HPC centers in Poznan, and CYFRONET in Cracow, installed accelerated clusters choosing GPGPU solutions. GPUs in Cracow constitute a part of the largest supercomputer in Poland. Accelerators are widely utilized there to optimize locally developed codes for quantum chemistry computations and complex dynamics in astrophysics applications.

Another installation is the SGI/Rackable system maintained by PSNC, using AMD x86 servers accelerated with NVIDIA GPU cards. It is used for computing intensive tasks in molecular modeling and fluid flow dynamics in porous media — reservoir modeling.

HPCwire: Why such a wide variety of architectures? Doesn’t that create problems for users who want to share applications across platforms?

Filocha: An underlying idea for POWIEW was to provide all existing key HPC architectures based on complementarity and competencies sharing among project partners. Project experts are expected to provide support to the researchers so as optimize their choice of suitable architectures.
HPCwire: Poland is a member of PRACE. How does POWIEW fit into that consortium?

Filocha: All POWIEW project members are actively involved in PRACE activities since their beginning. They work in applications, hardware and policy-related tasks. Selected systems deployed within POWIEW project are now included as a Tier-1 systems in current Distributed European Computing Initiative (DECI) calls. Some of our computers, including the IBM 775 system are the first of its kind available for PRACE users. Our experience of day-to-day use of such systems allowed us to contribute significantly to best practices guides for PRACE users.

HPCwire: As far as the future of POWIEW, what’s being planned: new systems, collaborations, new application areas…?

Filocha: Formally, POWIEW will run until mid-2013, but the actual goal is to extend the deployed hardware infrastructure and acquired software competencies further, based on experience gained during last three years of intensive growth.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Google Launches Site to Share its NYC-based Algorithm Research

August 22, 2017

Much of Google’s algorithm development occurs in groups scattered throughout New York City. Yesterday, Google launched a single website - NYC Algorithms and Optimization Team page - to provide a deeper view into all of Read more…

By John Russell

Dell Strikes Reseller Deal with Atos; Supplants SGI

August 22, 2017

Dell EMC and Atos announced a reseller deal today in which Dell will offer Atos’ high-end 8- and 16-socket Bullion servers. Some move from Dell had been expected following Hewlett Packard Enterprise’s purchase of SGI Read more…

By John Russell

Glimpses of Today’s Total Solar Eclipse

August 21, 2017

Here are a few arresting images posted by NASA of today’s total solar eclipse. Such astronomical events have always captured our imagination and it’s not hard to understand why such occurrences were often greeted wit Read more…

By John Russell

HPE Extreme Performance Solutions

Leveraging Deep Learning for Fraud Detection

Advancements in computing technologies and the expanding use of e-commerce platforms have dramatically increased the risk of fraud for financial services companies and their customers. Read more…

Tech Giants Outline Battle Plans for Future HPC Market

August 21, 2017

Four companies engaged in a cage fight for leadership in the emerging HPC market of the 2020s are, despite deep differences in some areas, in violent agreement on at least one thing: the power consumption and latency pen Read more…

By Doug Black

Tech Giants Outline Battle Plans for Future HPC Market

August 21, 2017

Four companies engaged in a cage fight for leadership in the emerging HPC market of the 2020s are, despite deep differences in some areas, in violent agreement Read more…

By Doug Black

Microsoft Bolsters Azure With Cloud HPC Deal

August 15, 2017

Microsoft has acquired cloud computing software vendor Cycle Computing in a move designed to bring orchestration tools along with high-end computing access capabilities to the cloud. Terms of the acquisition were not disclosed. Read more…

By George Leopold

HPE Ships Supercomputer to Space Station, Final Destination Mars

August 14, 2017

With a manned mission to Mars on the horizon, the demand for space-based supercomputing is at hand. Today HPE and NASA sent the first off-the-shelf HPC system i Read more…

By Tiffany Trader

AMD EPYC Video Takes Aim at Intel’s Broadwell

August 14, 2017

Let the benchmarking begin. Last week, AMD posted a YouTube video in which one of its EPYC-based systems outperformed a ‘comparable’ Intel Broadwell-based s Read more…

By John Russell

Deep Learning Thrives in Cancer Moonshot

August 8, 2017

The U.S. War on Cancer, certainly a worthy cause, is a collection of programs stretching back more than 40 years and abiding under many banners. The latest is t Read more…

By John Russell

IBM Raises the Bar for Distributed Deep Learning

August 8, 2017

IBM is announcing today an enhancement to its PowerAI software platform aimed at facilitating the practical scaling of AI models on today’s fastest GPUs. Scal Read more…

By Tiffany Trader

IBM Storage Breakthrough Paves Way for 330TB Tape Cartridges

August 3, 2017

IBM announced yesterday a new record for magnetic tape storage that it says will keep tape storage density on a Moore's law-like path far into the next decade. Read more…

By Tiffany Trader

AMD Stuffs a Petaflops of Machine Intelligence into 20-Node Rack

August 1, 2017

With its Radeon “Vega” Instinct datacenter GPUs and EPYC “Naples” server chips entering the market this summer, AMD has positioned itself for a two-head Read more…

By Tiffany Trader

How ‘Knights Mill’ Gets Its Deep Learning Flops

June 22, 2017

Intel, the subject of much speculation regarding the delayed, rewritten or potentially canceled “Aurora” contract (the Argonne Lab part of the CORAL “ Read more…

By Tiffany Trader

Nvidia’s Mammoth Volta GPU Aims High for AI, HPC

May 10, 2017

At Nvidia's GPU Technology Conference (GTC17) in San Jose, Calif., this morning, CEO Jensen Huang announced the company's much-anticipated Volta architecture a Read more…

By Tiffany Trader

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

Russian Researchers Claim First Quantum-Safe Blockchain

May 25, 2017

The Russian Quantum Center today announced it has overcome the threat of quantum cryptography by creating the first quantum-safe blockchain, securing cryptocurrencies like Bitcoin, along with classified government communications and other sensitive digital transfers. Read more…

By Doug Black

Quantum Bits: D-Wave and VW; Google Quantum Lab; IBM Expands Access

March 21, 2017

For a technology that’s usually characterized as far off and in a distant galaxy, quantum computing has been steadily picking up steam. Just how close real-wo Read more…

By John Russell

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Groq This: New AI Chips to Give GPUs a Run for Deep Learning Money

April 24, 2017

CPUs and GPUs, move over. Thanks to recent revelations surrounding Google’s new Tensor Processing Unit (TPU), the computing world appears to be on the cusp of Read more…

By Alex Woodie

HPC Compiler Company PathScale Seeks Life Raft

March 23, 2017

HPCwire has learned that HPC compiler company PathScale has fallen on difficult times and is asking the community for help or actively seeking a buyer for its a Read more…

By Tiffany Trader

Leading Solution Providers

Trump Budget Targets NIH, DOE, and EPA; No Mention of NSF

March 16, 2017

President Trump’s proposed U.S. fiscal 2018 budget issued today sharply cuts science spending while bolstering military spending as he promised during the cam Read more…

By John Russell

Google Debuts TPU v2 and will Add to Google Cloud

May 25, 2017

Not long after stirring attention in the deep learning/AI community by revealing the details of its Tensor Processing Unit (TPU), Google last week announced the Read more…

By John Russell

CPU-based Visualization Positions for Exascale Supercomputing

March 16, 2017

In this contributed perspective piece, Intel’s Jim Jeffers makes the case that CPU-based visualization is now widely adopted and as such is no longer a contrarian view, but is rather an exascale requirement. Read more…

By Jim Jeffers, Principal Engineer and Engineering Leader, Intel

Six Exascale PathForward Vendors Selected; DoE Providing $258M

June 15, 2017

The much-anticipated PathForward awards for hardware R&D in support of the Exascale Computing Project were announced today with six vendors selected – AMD Read more…

By John Russell

Top500 Results: Latest List Trends and What’s in Store

June 19, 2017

Greetings from Frankfurt and the 2017 International Supercomputing Conference where the latest Top500 list has just been revealed. Although there were no major Read more…

By Tiffany Trader

IBM Clears Path to 5nm with Silicon Nanosheets

June 5, 2017

Two years since announcing the industry’s first 7nm node test chip, IBM and its research alliance partners GlobalFoundries and Samsung have developed a proces Read more…

By Tiffany Trader

Messina Update: The US Path to Exascale in 16 Slides

April 26, 2017

Paul Messina, director of the U.S. Exascale Computing Project, provided a wide-ranging review of ECP’s evolving plans last week at the HPC User Forum. Read more…

By John Russell

Graphcore Readies Launch of 16nm Colossus-IPU Chip

July 20, 2017

A second $30 million funding round for U.K. AI chip developer Graphcore sets up the company to go to market with its “intelligent processing unit” (IPU) in Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This