Moore’s Law Scaling Stymied at 14nm?

By Tiffany Trader

January 15, 2013

As surely as the sun rises and sets, so the debate over Moore’s Law rages on. How much longer will the semiconductor industry get to cash in on the dimensional scaling of integrated circuits (ICs)? The latest round of noteworthy discussions takes place over at EETimes, where prominent industry execs square off over the cost of manufacturing 14-nm wafers.

Intel wafer

Close up of the wafer as it spins during a testing procedure. Source: Intel

Zvi Or-Bach, founder of MonolithIC 3D Inc., best known for his pioneering work on Monolithic 3D-ICs, provides a nice overview, arriving at some interesting conclusions of his own.

On one side, we have expert testimony from the recent International Electron Devices Meeting, reported on by EETimes‘ Rick Merritt:

“Chips made at the 14-nm process node may deliver as little as half the typical 30 percent performance increase – and still carry a hefty cost premium – due to the lack of next-generation lithography needed to make them efficiently,” Merritt summarizes.

This is also the opinion of Luc van den Hove, CEO of the IMEC research center in Belgium. Hove tells EETimes that extreme ultraviolet (EUV) lithography tools will not be widely available until 2014, leaving today’s chipmakers in a bind.

But not everyone agrees. Mark Bohr, director of process architecture and integration at Intel, offers an opposing point of view in another EETimes piece:

Projections from an IMEC keynote that 14-nm wafers will be 90 percent more expensive than 28-nm parts due to the lack of EUV lithography are inaccurate, Bohr asserted. The cost increase for 14-nm wafers at Intel “is nowhere near that,” he said.

“Cost per wafer has always gone up marginally each generation, somewhat more so in recent generations, but that’s more than offset by increases in transistor density so that the cost per transistor continues to go down at 14 nm,” Bohr said.

So who is correct? Or-Back makes the case that both organization’s CEOs are telling the truth as they know it, and that the apparent discrepancy stems from Intel’s primacy in semiconductor manufacturing.

It’s quite plausible that Intel’s raft of unique process technologies provide it with cost advantages that the other fabs lack. This would validate Borh’s claims. And as for Luc van den Hove’s predictions, Or-Back notes that IMEC’s cost roadmap is on par with the current best practices of non-Intel foundries, e.g., TSMC and STMicroelectronics.

Or-Back smells the profit potential. If this analysis stands up, it would behoove Intel to leverage this competitive edge by rapidly growing its foundry biz, extending its lead even further, he notes. Intel’s CEO pick will have a lot to do with how this plays out.

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