XPRESS Route to Exascale

By Nicole Hemsoth

February 28, 2013

In the world of supercomputers, where the top machines can cost upwards of $100 million, $1.1 million may not sound like much. To Thomas Sterling, chief scientist at the Center for Research in Extreme Scale Computing (CREST) at Indiana University, it’s a sum that will go a long way toward funding his favorite project.

The Department of Energy awarded that amount to Indiana University’s CREST last week to fund three years of work on the XPRESS (eXascale Programming Environment and System Software) project. CREST is collaborating with work going on simultaneously at Sandia National Laboratories and several other universities and research labs. The overall goal is to enable the creation of exascale computers.

HPCwire caught up with Sterling to discuss his role in the endeavor and what it means. As usual, he has some bold and controversial opinions on the future of supercomputing.

XPRESS, based on the ParalleX parallel computation model, is being designed to enable highly parallel processing. Collectively, the work being coordinated at Sandia, according to Sterling, represents “the single most important program in high performance computing that there is.”

CREST Team
From left to right: Executive Associate Director Thomas Sterling, Director Andrew Lumsdaine, and Associate Director of Strategy Craig Stewart

Sterling’s team at CREST, which is not yet 18 months old, is working on a unique new type of runtime environment, a dynamic system that will enable the software to automatically reallocate compute tasks over time. It will be self-correcting; detecting when processor cores are sitting idle and assigning them new tasks on the fly rather than sticking to the routines established by the human programmer, the compiler and the load time system. When it detects idle processors, it should be able to make adjustments on the order of a millisecond, or even a microsecond.

Sterling believes such a system could provide a dramatic improvement in the efficiency of supercomputers. Benchmarks such as Linpack or Highly Parallel Linpack don’t always represent the real world. When even the most powerful supercomputers are running real and very complex applications, such as multi-scale, multi-physics applications, the efficiency may be as high as 70% or as low as 3%, he says. “You’ll see that the efficiencies are often well below 10%,” he adds. “You find yourself throwing away 90% of the computer.”

Sterling acknowledges that others disagree with his approach. While other prominent research teams are working on improving the popular MPI (Message Passing Interface) to create a parallel processing system, Sterling has doubts about how far that kind of work can go. While a programmer can divide tasks among many different cores with MPI, the gains are limited because each task takes a different amount of time to complete. That requires setting up global barriers that keep each core from moving on to the next task until all the other cores have completed their tasks. A lot of cores, therefore, are sitting idle at any one time.

That works fine for many HPC programs; those in which the tasks are regular, even and coarse-grained, he says. There are plenty of such tasks in HPC, and MPI has been a big success as a result. But Sterling believes it is no longer sufficient to usher in the era of exascale. Complex scientific calculations are usually highly non-linear and the processing time of different cores can vary dramatically.

Next >>

Sterling believes that it’s not always necessary to use global barriers. Not every core needs to wait for all the tasks on all the other cores to finish. The cores that finish last are the ones that need the data from all the other cores before finishing their own tasks Every other core sits idly by to wait for them to catch up and release the barrier. The idle cores could be working on new tasks if they weren’t held back by the barrier, waiting for the last cores, whose data they don’t need, to catch up.

An example comes from climate modeling, where the researcher is studying changes in temperature over the ocean. The model has to take into account a lot of different variables, such as energy and mass transfer, different chemistries in the ocean, solar radiation, and the transfer of energy from the boundary areas of the water. It also has to take into account highly irregular coastlines, islands, or the distribution of ice. But when studying a cross-section of a grid over the ocean, it’s not necessary to wait for all the calculations to be completed for every section of the grid before moving on to the next task. One grid in the middle of the Atlantic is only going to be affected by areas within tens or hundreds of kilometers, not by sections in the Pacific. Some of the calculations do not need to wait for the entire set of processors to finish.

The problem is that it’s virtually impossible for the programmer to figure out in advance all the permutations of tasks and cores that would move things along more rapidly. That’s where the ParalleX execution model comes in. Dynamic modeling means that the system can automatically detect when tasks are finished and cores are sitting idle. It can then assign new tasks to those cores. Everything still needs to be synchronized at certain points, but ParalleX sets up many smaller barriers rather than one global barrier.

Sterling has a lot of confidence in the work at CREST, which is devising a new software stack that will insert an XPRESS layer into the X-Stack system. But just creating a plug-in stack layer is not sufficient. CREST’s work is being done in conjunction with Sandia’s light weight kernel operating system, integrating them tightly together. “We’re able to redefine the OS and the runtime system jointly, which creates a whole new protocol, a whole new relationship between those two pieces of software,” he says.

Where his work goes further than other efforts as parallelism, he adds, is moving beyond an ad-hoc approach to an integrated system.

“We redefine the execution model so these things stop being hacks, stop being patches and they start being something of a comprehensive or a coherent, complete paradigm,” he says. “We feel it’s very important that everything be designed within the context and scope of everything else so it all makes sense. That will create a whole new ability to dialog between the two software layers.”

How much improvement can this approach offer? Theoretically the combined project could increase efficiency by a factor of 20. So far, his tests have managed to increase efficiency by a factor of two.

Might it be better to just figure out how to evolve MPI to do the same kind of thing? Sterling acknowledges that it might, but ultimately he doubts if that approach will be able to make the leap forward in parallelism that’s needed. He compares it to punctuated equilibrium in evolutionary biology. Evolution is not always gradual change; sometimes it encounters a rapidly changing environment and must adapt quickly.

Sterling believes we’re at such a point today. “It’s not just because of big data, although that’s the big thing right now,” he says. More importantly, he says, the big need is for dynamic graph structures. Climate modeling, for example, is a hugely complex problem that requires more than a two-dimensional approach. Accounting for hurricanes and other phenomena in oceans requires a z-axis. Industrial design, microbiology, and controlled fusion are also deep, highly non-linear problems that need solving with dynamic graphs. This kind of parallelism is key to the future of HPC, not just for number crunching, he says, but for “HPC symbolic information, which means knowledge management and understanding by machines.”

While the overall program is officially dedicated to creating exascale computing, Sterling believes it could prove its importance much sooner than that. He refers to the need for “extreme scale” computing, not exascale, which is an arbitrary benchmark. A lot of progress can be made along the way. Getting to exascale represents in increase in compute power of two orders of magnitude from today’s best supercomputers. But one order of magnitude or less would go a long way to improving materials science, industrial design, microbiology and what he sees as the most important need for the 21st century, controlled fusion. Supercomputers are already showing limitations for some of the kinds of scientific programming people want to do.

“You don’t have to wait until the end of the decade to worry about exascale,” he says. “The challenge is today, not some far future challenge. We are losing today and we need new methods today.”

He believes he has a good chance of meeting that challenge. And that makes him very happy. “There will be nothing like it,” he says. “I find it very exciting.”

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

At Long Last, Supercomputing Helps to Map the Poles

August 22, 2019

“For years,” Paul Morin wrote, “those of us that made maps of the Poles apologized. We apologized for the blank spaces on maps, we apologized for mountains being in the wrong place and out-of-date information.” Read more…

By Oliver Peckham

Xilinx Says Its New FPGA is World’s Largest

August 21, 2019

In this age of exploding “technology disaggregation” – in which the Big Bang emanating from the Intel x86 CPU has produced significant advances in CPU chips and a raft of alternative, accelerated architectures... Read more…

By Doug Black

Supercomputers Generate Universes to Illuminate Galactic Formation

August 20, 2019

With advanced imaging and satellite technologies, it’s easier than ever to see a galaxy – but understanding how they form (a process that can take billions of years) is a different story. Now, a team of researchers f Read more…

By Oliver Peckham

AWS Solution Channel

Efficiency and Cost-Optimization for HPC Workloads – AWS Batch and Amazon EC2 Spot Instances

High Performance Computing on AWS leverages the power of cloud computing and the extreme scale it offers to achieve optimal HPC price/performance. With AWS you can right size your services to meet exactly the capacity requirements you need without having to overprovision or compromise capacity. Read more…

HPE Extreme Performance Solutions

Bring the combined power of HPC and AI to your business transformation

FPGA (Field Programmable Gate Array) acceleration cards are not new, as they’ve been commercially available since 1984. Typically, the emphasis around FPGAs has centered on the fact that they’re programmable accelerators, and that they can truly offer workload specific hardware acceleration solutions without requiring custom silicon. Read more…

IBM Accelerated Insights

Keys to Attracting the Newest HPC Talent – Post-Millennials

[Connect with HPC users and learn new skills in the IBM Spectrum LSF User Community.]

For engineers and scientists growing up in the 80s, the current state of HPC makes perfect sense. Read more…

Singularity Moves Up the Container Value Chain

August 20, 2019

The enterprise version of the Singularity HPC container platform released this week by Sylabs is designed to allow users to create, secure and share the high-end containers in self-hosted production deployments. The e Read more…

By George Leopold

At Long Last, Supercomputing Helps to Map the Poles

August 22, 2019

“For years,” Paul Morin wrote, “those of us that made maps of the Poles apologized. We apologized for the blank spaces on maps, we apologized for mountains being in the wrong place and out-of-date information.” Read more…

By Oliver Peckham

IBM Deepens Plunge into Open Source; OpenPOWER to Join Linux Foundation

August 20, 2019

IBM today announced it was contributing the instruction set (ISA) for its Power microprocessor and the designs for the Open Coherent Accelerator Processor Inter Read more…

By John Russell

Ayar Labs to Demo Photonics Chiplet in FPGA Package at Hot Chips

August 19, 2019

Silicon startup Ayar Labs continues to gain momentum with its DARPA-backed optical chiplet technology that puts advanced electronics and optics on the same chip Read more…

By Tiffany Trader

Scientists to Tap Exascale Computing to Unlock the Mystery of our Accelerating Universe

August 14, 2019

The universe and everything in it roared to life with the Big Bang approximately 13.8 billion years ago. It has continued expanding ever since. While we have a Read more…

By Rob Johnson

AI is the Next Exascale – Rick Stevens on What that Means and Why It’s Important

August 13, 2019

Twelve years ago the Department of Energy (DOE) was just beginning to explore what an exascale computing program might look like and what it might accomplish. Today, DOE is repeating that process for AI, once again starting with science community town halls to gather input and stimulate conversation. The town hall program... Read more…

By Tiffany Trader and John Russell

Cray Wins NNSA-Livermore ‘El Capitan’ Exascale Contract

August 13, 2019

Cray has won the bid to build the first exascale supercomputer for the National Nuclear Security Administration (NNSA) and Lawrence Livermore National Laborator Read more…

By Tiffany Trader

AMD Launches Epyc Rome, First 7nm CPU

August 8, 2019

From a gala event at the Palace of Fine Arts in San Francisco yesterday (Aug. 7), AMD launched its second-generation Epyc Rome x86 chips, based on its 7nm proce Read more…

By Tiffany Trader

Lenovo Drives Single-Socket Servers with AMD Epyc Rome CPUs

August 7, 2019

No summer doldrums here. As part of the AMD Epyc Rome launch event in San Francisco today, Lenovo announced two new single-socket servers, the ThinkSystem SR635 Read more…

By Doug Black

High Performance (Potato) Chips

May 5, 2006

In this article, we focus on how Procter & Gamble is using high performance computing to create some common, everyday supermarket products. Tom Lange, a 27-year veteran of the company, tells us how P&G models products, processes and production systems for the betterment of consumer package goods. Read more…

By Michael Feldman

Supercomputer-Powered AI Tackles a Key Fusion Energy Challenge

August 7, 2019

Fusion energy is the Holy Grail of the energy world: low-radioactivity, low-waste, zero-carbon, high-output nuclear power that can run on hydrogen or lithium. T Read more…

By Oliver Peckham

Cray, AMD to Extend DOE’s Exascale Frontier

May 7, 2019

Cray and AMD are coming back to Oak Ridge National Laboratory to partner on the world’s largest and most expensive supercomputer. The Department of Energy’s Read more…

By Tiffany Trader

Graphene Surprises Again, This Time for Quantum Computing

May 8, 2019

Graphene is fascinating stuff with promise for use in a seeming endless number of applications. This month researchers from the University of Vienna and Institu Read more…

By John Russell

AMD Verifies Its Largest 7nm Chip Design in Ten Hours

June 5, 2019

AMD announced last week that its engineers had successfully executed the first physical verification of its largest 7nm chip design – in just ten hours. The AMD Radeon Instinct Vega20 – which boasts 13.2 billion transistors – was tested using a TSMC-certified Calibre nmDRC software platform from Mentor. Read more…

By Oliver Peckham

TSMC and Samsung Moving to 5nm; Whither Moore’s Law?

June 12, 2019

With reports that Taiwan Semiconductor Manufacturing Co. (TMSC) and Samsung are moving quickly to 5nm manufacturing, it’s a good time to again ponder whither goes the venerable Moore’s law. Shrinking feature size has of course been the primary hallmark of achieving Moore’s law... Read more…

By John Russell

Cray Wins NNSA-Livermore ‘El Capitan’ Exascale Contract

August 13, 2019

Cray has won the bid to build the first exascale supercomputer for the National Nuclear Security Administration (NNSA) and Lawrence Livermore National Laborator Read more…

By Tiffany Trader

Deep Learning Competitors Stalk Nvidia

May 14, 2019

There is no shortage of processing architectures emerging to accelerate deep learning workloads, with two more options emerging this week to challenge GPU leader Nvidia. First, Intel researchers claimed a new deep learning record for image classification on the ResNet-50 convolutional neural network. Separately, Israeli AI chip startup Hailo.ai... Read more…

By George Leopold

Leading Solution Providers

ISC 2019 Virtual Booth Video Tour

CRAY
CRAY
DDN
DDN
DELL EMC
DELL EMC
GOOGLE
GOOGLE
ONE STOP SYSTEMS
ONE STOP SYSTEMS
PANASAS
PANASAS
VERNE GLOBAL
VERNE GLOBAL

Nvidia Embraces Arm, Declares Intent to Accelerate All CPU Architectures

June 17, 2019

As the Top500 list was being announced at ISC in Frankfurt today with an upgraded petascale Arm supercomputer in the top third of the list, Nvidia announced its Read more…

By Tiffany Trader

Top500 Purely Petaflops; US Maintains Performance Lead

June 17, 2019

With the kick-off of the International Supercomputing Conference (ISC) in Frankfurt this morning, the 53rd Top500 list made its debut, and this one's for petafl Read more…

By Tiffany Trader

AMD Launches Epyc Rome, First 7nm CPU

August 8, 2019

From a gala event at the Palace of Fine Arts in San Francisco yesterday (Aug. 7), AMD launched its second-generation Epyc Rome x86 chips, based on its 7nm proce Read more…

By Tiffany Trader

A Behind-the-Scenes Look at the Hardware That Powered the Black Hole Image

June 24, 2019

Two months ago, the first-ever image of a black hole took the internet by storm. A team of scientists took years to produce and verify the striking image – an Read more…

By Oliver Peckham

Cray – and the Cray Brand – to Be Positioned at Tip of HPE’s HPC Spear

May 22, 2019

More so than with most acquisitions of this kind, HPE’s purchase of Cray for $1.3 billion, announced last week, seems to have elements of that overused, often Read more…

By Doug Black and Tiffany Trader

Chinese Company Sugon Placed on US ‘Entity List’ After Strong Showing at International Supercomputing Conference

June 26, 2019

After more than a decade of advancing its supercomputing prowess, operating the world’s most powerful supercomputer from June 2013 to June 2018, China is keep Read more…

By Tiffany Trader

Qualcomm Invests in RISC-V Startup SiFive

June 7, 2019

Investors are zeroing in on the open standard RISC-V instruction set architecture and the processor intellectual property being developed by a batch of high-flying chip startups. Last fall, Esperanto Technologies announced a $58 million funding round. Read more…

By George Leopold

Intel 7nm GPU on Roadmap for 2021, OneAPI Coming This Year

May 8, 2019

At Intel's investor meeting today in Santa Clara, Calif., the company filled in details of its roadmap and product launch plans and sought to allay concerns about delays of its 10nm chips. In laying out its 10nm and 7nm timelines, Intel revealed that its first 7nm product would be... Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This